1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * This file is part of AD5686 DAC driver 4 * 5 * Copyright 2018 Analog Devices Inc. 6 */ 7 8 #ifndef __DRIVERS_IIO_DAC_AD5686_H__ 9 #define __DRIVERS_IIO_DAC_AD5686_H__ 10 11 #include <linux/types.h> 12 #include <linux/cache.h> 13 #include <linux/mutex.h> 14 #include <linux/kernel.h> 15 16 #define AD5310_CMD(x) ((x) << 12) 17 18 #define AD5683_DATA(x) ((x) << 4) 19 20 #define AD5686_ADDR(x) ((x) << 16) 21 #define AD5686_CMD(x) ((x) << 20) 22 23 #define AD5686_ADDR_DAC(chan) (0x1 << (chan)) 24 #define AD5686_ADDR_ALL_DAC 0xF 25 26 #define AD5686_CMD_NOOP 0x0 27 #define AD5686_CMD_WRITE_INPUT_N 0x1 28 #define AD5686_CMD_UPDATE_DAC_N 0x2 29 #define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3 30 #define AD5686_CMD_POWERDOWN_DAC 0x4 31 #define AD5686_CMD_LDAC_MASK 0x5 32 #define AD5686_CMD_RESET 0x6 33 #define AD5686_CMD_INTERNAL_REFER_SETUP 0x7 34 #define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8 35 #define AD5686_CMD_READBACK_ENABLE 0x9 36 37 #define AD5686_LDAC_PWRDN_NONE 0x0 38 #define AD5686_LDAC_PWRDN_1K 0x1 39 #define AD5686_LDAC_PWRDN_100K 0x2 40 #define AD5686_LDAC_PWRDN_3STATE 0x3 41 42 #define AD5686_CMD_CONTROL_REG 0x4 43 #define AD5686_CMD_READBACK_ENABLE_V2 0x5 44 45 #define AD5310_REF_BIT_MSK BIT(8) 46 #define AD5683_REF_BIT_MSK BIT(12) 47 #define AD5693_REF_BIT_MSK BIT(12) 48 49 /** 50 * ad5686_supported_device_ids: 51 */ 52 enum ad5686_supported_device_ids { 53 ID_AD5310R, 54 ID_AD5311R, 55 ID_AD5338R, 56 ID_AD5671R, 57 ID_AD5672R, 58 ID_AD5674R, 59 ID_AD5675R, 60 ID_AD5676, 61 ID_AD5676R, 62 ID_AD5679R, 63 ID_AD5681R, 64 ID_AD5682R, 65 ID_AD5683, 66 ID_AD5683R, 67 ID_AD5684, 68 ID_AD5684R, 69 ID_AD5685R, 70 ID_AD5686, 71 ID_AD5686R, 72 ID_AD5691R, 73 ID_AD5692R, 74 ID_AD5693, 75 ID_AD5693R, 76 ID_AD5694, 77 ID_AD5694R, 78 ID_AD5695R, 79 ID_AD5696, 80 ID_AD5696R, 81 }; 82 83 enum ad5686_regmap_type { 84 AD5310_REGMAP, 85 AD5683_REGMAP, 86 AD5686_REGMAP, 87 AD5693_REGMAP 88 }; 89 90 struct ad5686_state; 91 92 typedef int (*ad5686_write_func)(struct ad5686_state *st, 93 u8 cmd, u8 addr, u16 val); 94 95 typedef int (*ad5686_read_func)(struct ad5686_state *st, u8 addr); 96 97 /** 98 * struct ad5686_chip_info - chip specific information 99 * @int_vref_mv: AD5620/40/60: the internal reference voltage 100 * @num_channels: number of channels 101 * @channel: channel specification 102 * @regmap_type: register map layout variant 103 */ 104 105 struct ad5686_chip_info { 106 u16 int_vref_mv; 107 unsigned int num_channels; 108 const struct iio_chan_spec *channels; 109 enum ad5686_regmap_type regmap_type; 110 }; 111 112 /** 113 * struct ad5446_state - driver instance specific data 114 * @spi: spi_device 115 * @chip_info: chip model specific constants, available modes etc 116 * @reg: supply regulator 117 * @vref_mv: actual reference voltage used 118 * @pwr_down_mask: power down mask 119 * @pwr_down_mode: current power down mode 120 * @use_internal_vref: set to true if the internal reference voltage is used 121 * @lock lock to protect the data buffer during regmap ops 122 * @data: spi transfer buffers 123 */ 124 125 struct ad5686_state { 126 struct device *dev; 127 const struct ad5686_chip_info *chip_info; 128 struct regulator *reg; 129 unsigned short vref_mv; 130 unsigned int pwr_down_mask; 131 unsigned int pwr_down_mode; 132 ad5686_write_func write; 133 ad5686_read_func read; 134 bool use_internal_vref; 135 struct mutex lock; 136 137 /* 138 * DMA (thus cache coherency maintenance) requires the 139 * transfer buffers to live in their own cache lines. 140 */ 141 142 union { 143 __be32 d32; 144 __be16 d16; 145 u8 d8[4]; 146 } data[3] ____cacheline_aligned; 147 }; 148 149 150 int ad5686_probe(struct device *dev, 151 enum ad5686_supported_device_ids chip_type, 152 const char *name, ad5686_write_func write, 153 ad5686_read_func read); 154 155 int ad5686_remove(struct device *dev); 156 157 158 #endif /* __DRIVERS_IIO_DAC_AD5686_H__ */ 159