1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * This file is part of AD5686 DAC driver 4 * 5 * Copyright 2018 Analog Devices Inc. 6 */ 7 8 #ifndef __DRIVERS_IIO_DAC_AD5686_H__ 9 #define __DRIVERS_IIO_DAC_AD5686_H__ 10 11 #include <linux/bits.h> 12 #include <linux/mutex.h> 13 #include <linux/types.h> 14 15 #include <linux/iio/iio.h> 16 17 #define AD5310_CMD_MSK GENMASK(15, 12) 18 #define AD5310_DATA_MSK GENMASK(11, 0) 19 20 #define AD5683_DATA_MSK GENMASK(19, 4) 21 22 #define AD5686_CMD_MSK GENMASK(23, 20) 23 #define AD5686_ADDR_MSK GENMASK(19, 16) 24 #define AD5686_DATA_MSK GENMASK(15, 0) 25 26 #define AD5686_ADDR_DAC(chan) (0x1 << (chan)) 27 #define AD5686_ADDR_ALL_DAC 0xF 28 #define AD5686_MAX_CHANNELS 16 29 30 #define AD5686_CMD_NOOP 0x0 31 #define AD5686_CMD_WRITE_INPUT_N 0x1 32 #define AD5686_CMD_UPDATE_DAC_N 0x2 33 #define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3 34 #define AD5686_CMD_POWERDOWN_DAC 0x4 35 #define AD5686_CMD_LDAC_MASK 0x5 36 #define AD5686_CMD_RESET 0x6 37 #define AD5686_CMD_INTERNAL_REFER_SETUP 0x7 38 #define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8 39 #define AD5686_CMD_READBACK_ENABLE 0x9 40 41 #define AD5686_CMD_CONTROL_REG 0x4 42 #define AD5686_CMD_READBACK_ENABLE_V2 0x5 43 44 #define AD5310_DATA_GAIN_MSK BIT(7) 45 #define AD5310_DATA_REF_MSK BIT(8) 46 #define AD5310_DATA_PD_MSK GENMASK(10, 9) 47 48 #define AD5683_DATA_GAIN_MSK BIT(11) /* DB15 */ 49 #define AD5683_DATA_REF_MSK BIT(12) /* DB16 */ 50 #define AD5683_DATA_PD_MSK GENMASK(14, 13) /* DB18:DB17 */ 51 52 #define AD5686_DATA_REF_MSK BIT(0) 53 54 #define AD5686_PD_MSK GENMASK(1, 0) 55 #define AD5686_PD_MODE_1K_TO_GND 0x1 56 #define AD5686_PD_MODE_100K_TO_GND 0x2 57 #define AD5686_PD_MODE_THREE_STATE 0x3 58 59 #define AD5686_PD_MSK_PWR_UP 0x0 60 #define AD5686_PD_MSK_PWR_DOWN 0x3 61 62 enum ad5686_regmap_type { 63 AD5310_REGMAP, 64 AD5683_REGMAP, 65 AD5686_REGMAP, 66 }; 67 68 struct gpio_desc; 69 70 struct ad5686_state; 71 72 /** 73 * struct ad5686_bus_ops - bus specific read/write operations 74 * @read: read a register value at the given address 75 * @write: write a command, address and value to the device 76 * @sync: ensure the completion of the write operation (optional) 77 */ 78 struct ad5686_bus_ops { 79 int (*read)(struct ad5686_state *st, u8 addr); 80 int (*write)(struct ad5686_state *st, u8 cmd, u8 addr, u16 val); 81 int (*sync)(struct ad5686_state *st); 82 }; 83 84 /** 85 * struct ad5686_chip_info - chip specific information 86 * @int_vref_mv: the internal reference voltage 87 * @num_channels: number of channels 88 * @channel: channel specification 89 * @regmap_type: register map layout variant 90 */ 91 struct ad5686_chip_info { 92 u16 int_vref_mv; 93 unsigned int num_channels; 94 const struct iio_chan_spec *channels; 95 enum ad5686_regmap_type regmap_type; 96 }; 97 98 /* single-channel instances */ 99 extern const struct ad5686_chip_info ad5310r_chip_info; 100 extern const struct ad5686_chip_info ad5311r_chip_info; 101 extern const struct ad5686_chip_info ad5681r_chip_info; 102 extern const struct ad5686_chip_info ad5682r_chip_info; 103 extern const struct ad5686_chip_info ad5683_chip_info; 104 extern const struct ad5686_chip_info ad5683r_chip_info; 105 106 /* dual-channel instances */ 107 extern const struct ad5686_chip_info ad5337r_chip_info; 108 extern const struct ad5686_chip_info ad5338r_chip_info; 109 extern const struct ad5686_chip_info ad5687_chip_info; 110 extern const struct ad5686_chip_info ad5687r_chip_info; 111 extern const struct ad5686_chip_info ad5689_chip_info; 112 extern const struct ad5686_chip_info ad5689r_chip_info; 113 114 /* quad-channel instances */ 115 extern const struct ad5686_chip_info ad5317r_chip_info; 116 extern const struct ad5686_chip_info ad5684_chip_info; 117 extern const struct ad5686_chip_info ad5684r_chip_info; 118 extern const struct ad5686_chip_info ad5685r_chip_info; 119 extern const struct ad5686_chip_info ad5686_chip_info; 120 extern const struct ad5686_chip_info ad5686r_chip_info; 121 122 /* 8-channel instances */ 123 extern const struct ad5686_chip_info ad5672r_chip_info; 124 extern const struct ad5686_chip_info ad5676_chip_info; 125 extern const struct ad5686_chip_info ad5676r_chip_info; 126 127 /* 16-channel instances */ 128 extern const struct ad5686_chip_info ad5674_chip_info; 129 extern const struct ad5686_chip_info ad5674r_chip_info; 130 extern const struct ad5686_chip_info ad5679_chip_info; 131 extern const struct ad5686_chip_info ad5679r_chip_info; 132 133 /** 134 * struct ad5686_state - driver instance specific data 135 * @dev: device instance 136 * @chip_info: chip model specific constants, available modes etc 137 * @ops: bus specific operations 138 * @ldac_gpio: LDAC pin GPIO descriptor 139 * @gain_gpio: GAIN pin GPIO descriptor 140 * @pwr_down_mask: power down mask 141 * @pwr_down_mode: current power down mode 142 * @scale_avail: pre-calculated available scale values 143 * @vref_mv: actual reference voltage used 144 * @double_scale: flag to indicate the gain multiplier is applied 145 * @use_internal_vref: set to true if the internal reference voltage is used 146 * @lock: lock to protect access to state fields, which includes 147 * the data buffer during regmap ops 148 * @bus_data: bus specific data 149 * @data: transfer buffers 150 */ 151 struct ad5686_state { 152 struct device *dev; 153 const struct ad5686_chip_info *chip_info; 154 const struct ad5686_bus_ops *ops; 155 struct gpio_desc *ldac_gpio; 156 struct gpio_desc *gain_gpio; 157 unsigned int pwr_down_mask; 158 unsigned int pwr_down_mode; 159 int scale_avail[4]; 160 unsigned short vref_mv; 161 bool double_scale; 162 bool use_internal_vref; 163 struct mutex lock; 164 void *bus_data; 165 166 /* 167 * DMA (thus cache coherency maintenance) may require the 168 * transfer buffers to live in their own cache lines. 169 */ 170 171 union { 172 __be32 d32; 173 __be16 d16; 174 u8 d8[4]; 175 } data[AD5686_MAX_CHANNELS] __aligned(IIO_DMA_MINALIGN); 176 }; 177 178 179 int ad5686_probe(struct device *dev, 180 const struct ad5686_chip_info *chip_info, 181 const char *name, const struct ad5686_bus_ops *ops, 182 void *bus_data); 183 184 static inline int ad5686_write(struct ad5686_state *st, u8 cmd, u8 addr, u16 val) 185 { 186 int ret; 187 188 ret = st->ops->write(st, cmd, addr, val); 189 if (ret) 190 return ret; 191 192 return st->ops->sync ? st->ops->sync(st) : 0; 193 } 194 195 static inline int ad5686_read(struct ad5686_state *st, u8 addr) 196 { 197 return st->ops->read(st, addr); 198 } 199 200 #endif /* __DRIVERS_IIO_DAC_AD5686_H__ */ 201