1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD5686R, AD5685R, AD5684R Digital to analog converters driver 4 * 5 * Copyright 2011 Analog Devices Inc. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/fs.h> 10 #include <linux/device.h> 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/slab.h> 14 #include <linux/sysfs.h> 15 #include <linux/regulator/consumer.h> 16 17 #include <linux/iio/iio.h> 18 #include <linux/iio/sysfs.h> 19 20 #include "ad5686.h" 21 22 static const char * const ad5686_powerdown_modes[] = { 23 "1kohm_to_gnd", 24 "100kohm_to_gnd", 25 "three_state" 26 }; 27 28 static inline unsigned int ad5686_pd_mask_shift(const struct iio_chan_spec *chan) 29 { 30 if (chan->channel == chan->address) 31 return chan->channel * 2; 32 33 /* one-hot encoding is used in dual/quad channel devices */ 34 return __ffs(chan->address) * 2; 35 } 36 37 static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev, 38 const struct iio_chan_spec *chan) 39 { 40 unsigned int shift = ad5686_pd_mask_shift(chan); 41 struct ad5686_state *st = iio_priv(indio_dev); 42 43 guard(mutex)(&st->lock); 44 45 return ((st->pwr_down_mode >> shift) & 0x3U) - 1; 46 } 47 48 static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev, 49 const struct iio_chan_spec *chan, 50 unsigned int mode) 51 { 52 unsigned int shift = ad5686_pd_mask_shift(chan); 53 struct ad5686_state *st = iio_priv(indio_dev); 54 55 guard(mutex)(&st->lock); 56 57 st->pwr_down_mode &= ~(0x3U << shift); 58 st->pwr_down_mode |= (mode + 1) << shift; 59 60 return 0; 61 } 62 63 static const struct iio_enum ad5686_powerdown_mode_enum = { 64 .items = ad5686_powerdown_modes, 65 .num_items = ARRAY_SIZE(ad5686_powerdown_modes), 66 .get = ad5686_get_powerdown_mode, 67 .set = ad5686_set_powerdown_mode, 68 }; 69 70 static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev, 71 uintptr_t private, const struct iio_chan_spec *chan, char *buf) 72 { 73 unsigned int shift = ad5686_pd_mask_shift(chan); 74 struct ad5686_state *st = iio_priv(indio_dev); 75 76 guard(mutex)(&st->lock); 77 78 return sysfs_emit(buf, "%d\n", !!(st->pwr_down_mask & (0x3U << shift))); 79 } 80 81 static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev, 82 uintptr_t private, 83 const struct iio_chan_spec *chan, 84 const char *buf, 85 size_t len) 86 { 87 bool readin; 88 int ret; 89 struct ad5686_state *st = iio_priv(indio_dev); 90 unsigned int val, ref_bit_msk; 91 u8 shift, address = 0; 92 93 ret = kstrtobool(buf, &readin); 94 if (ret) 95 return ret; 96 97 guard(mutex)(&st->lock); 98 99 if (readin) 100 st->pwr_down_mask |= 0x3U << ad5686_pd_mask_shift(chan); 101 else 102 st->pwr_down_mask &= ~(0x3U << ad5686_pd_mask_shift(chan)); 103 104 switch (st->chip_info->regmap_type) { 105 case AD5310_REGMAP: 106 shift = 9; 107 ref_bit_msk = AD5310_REF_BIT_MSK; 108 break; 109 case AD5683_REGMAP: 110 shift = 13; 111 ref_bit_msk = AD5683_REF_BIT_MSK; 112 break; 113 case AD5686_REGMAP: 114 shift = 0; 115 ref_bit_msk = 0; 116 /* AD5674R/AD5679R have 16 channels and 2 powerdown registers */ 117 if (chan->channel > 0x7) 118 address = 0x8; 119 break; 120 case AD5693_REGMAP: 121 shift = 13; 122 ref_bit_msk = AD5693_REF_BIT_MSK; 123 break; 124 default: 125 return -EINVAL; 126 } 127 128 val = ((st->pwr_down_mask & st->pwr_down_mode) << shift); 129 if (!st->use_internal_vref) 130 val |= ref_bit_msk; 131 132 ret = st->write(st, AD5686_CMD_POWERDOWN_DAC, 133 address, val >> (address * 2)); 134 135 return ret ? ret : len; 136 } 137 138 static int ad5686_read_raw(struct iio_dev *indio_dev, 139 struct iio_chan_spec const *chan, 140 int *val, 141 int *val2, 142 long m) 143 { 144 struct ad5686_state *st = iio_priv(indio_dev); 145 int ret; 146 147 switch (m) { 148 case IIO_CHAN_INFO_RAW: 149 mutex_lock(&st->lock); 150 ret = st->read(st, chan->address); 151 mutex_unlock(&st->lock); 152 if (ret < 0) 153 return ret; 154 *val = (ret >> chan->scan_type.shift) & 155 GENMASK(chan->scan_type.realbits - 1, 0); 156 return IIO_VAL_INT; 157 case IIO_CHAN_INFO_SCALE: 158 *val = st->vref_mv; 159 *val2 = chan->scan_type.realbits; 160 return IIO_VAL_FRACTIONAL_LOG2; 161 } 162 return -EINVAL; 163 } 164 165 static int ad5686_write_raw(struct iio_dev *indio_dev, 166 struct iio_chan_spec const *chan, 167 int val, 168 int val2, 169 long mask) 170 { 171 struct ad5686_state *st = iio_priv(indio_dev); 172 int ret; 173 174 switch (mask) { 175 case IIO_CHAN_INFO_RAW: 176 if (val >= (1 << chan->scan_type.realbits) || val < 0) 177 return -EINVAL; 178 179 mutex_lock(&st->lock); 180 ret = st->write(st, 181 AD5686_CMD_WRITE_INPUT_N_UPDATE_N, 182 chan->address, 183 val << chan->scan_type.shift); 184 mutex_unlock(&st->lock); 185 break; 186 default: 187 ret = -EINVAL; 188 } 189 190 return ret; 191 } 192 193 static const struct iio_info ad5686_info = { 194 .read_raw = ad5686_read_raw, 195 .write_raw = ad5686_write_raw, 196 }; 197 198 static const struct iio_chan_spec_ext_info ad5686_ext_info[] = { 199 { 200 .name = "powerdown", 201 .read = ad5686_read_dac_powerdown, 202 .write = ad5686_write_dac_powerdown, 203 .shared = IIO_SEPARATE, 204 }, 205 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5686_powerdown_mode_enum), 206 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5686_powerdown_mode_enum), 207 { } 208 }; 209 210 #define AD5868_CHANNEL(chan, addr, bits, _shift) { \ 211 .type = IIO_VOLTAGE, \ 212 .indexed = 1, \ 213 .output = 1, \ 214 .channel = chan, \ 215 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 216 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\ 217 .address = addr, \ 218 .scan_type = { \ 219 .sign = 'u', \ 220 .realbits = (bits), \ 221 .storagebits = 16, \ 222 .shift = (_shift), \ 223 }, \ 224 .ext_info = ad5686_ext_info, \ 225 } 226 227 #define DECLARE_AD5693_CHANNELS(name, bits, _shift) \ 228 static const struct iio_chan_spec name[] = { \ 229 AD5868_CHANNEL(0, 0, bits, _shift), \ 230 } 231 232 #define DECLARE_AD5338_CHANNELS(name, bits, _shift) \ 233 static const struct iio_chan_spec name[] = { \ 234 AD5868_CHANNEL(0, 1, bits, _shift), \ 235 AD5868_CHANNEL(1, 8, bits, _shift), \ 236 } 237 238 #define DECLARE_AD5686_CHANNELS(name, bits, _shift) \ 239 static const struct iio_chan_spec name[] = { \ 240 AD5868_CHANNEL(0, 1, bits, _shift), \ 241 AD5868_CHANNEL(1, 2, bits, _shift), \ 242 AD5868_CHANNEL(2, 4, bits, _shift), \ 243 AD5868_CHANNEL(3, 8, bits, _shift), \ 244 } 245 246 #define DECLARE_AD5676_CHANNELS(name, bits, _shift) \ 247 static const struct iio_chan_spec name[] = { \ 248 AD5868_CHANNEL(0, 0, bits, _shift), \ 249 AD5868_CHANNEL(1, 1, bits, _shift), \ 250 AD5868_CHANNEL(2, 2, bits, _shift), \ 251 AD5868_CHANNEL(3, 3, bits, _shift), \ 252 AD5868_CHANNEL(4, 4, bits, _shift), \ 253 AD5868_CHANNEL(5, 5, bits, _shift), \ 254 AD5868_CHANNEL(6, 6, bits, _shift), \ 255 AD5868_CHANNEL(7, 7, bits, _shift), \ 256 } 257 258 #define DECLARE_AD5679_CHANNELS(name, bits, _shift) \ 259 static const struct iio_chan_spec name[] = { \ 260 AD5868_CHANNEL(0, 0, bits, _shift), \ 261 AD5868_CHANNEL(1, 1, bits, _shift), \ 262 AD5868_CHANNEL(2, 2, bits, _shift), \ 263 AD5868_CHANNEL(3, 3, bits, _shift), \ 264 AD5868_CHANNEL(4, 4, bits, _shift), \ 265 AD5868_CHANNEL(5, 5, bits, _shift), \ 266 AD5868_CHANNEL(6, 6, bits, _shift), \ 267 AD5868_CHANNEL(7, 7, bits, _shift), \ 268 AD5868_CHANNEL(8, 8, bits, _shift), \ 269 AD5868_CHANNEL(9, 9, bits, _shift), \ 270 AD5868_CHANNEL(10, 10, bits, _shift), \ 271 AD5868_CHANNEL(11, 11, bits, _shift), \ 272 AD5868_CHANNEL(12, 12, bits, _shift), \ 273 AD5868_CHANNEL(13, 13, bits, _shift), \ 274 AD5868_CHANNEL(14, 14, bits, _shift), \ 275 AD5868_CHANNEL(15, 15, bits, _shift), \ 276 } 277 278 DECLARE_AD5693_CHANNELS(ad5310r_channels, 10, 2); 279 DECLARE_AD5693_CHANNELS(ad5311r_channels, 10, 6); 280 DECLARE_AD5338_CHANNELS(ad5337r_channels, 8, 8); 281 DECLARE_AD5338_CHANNELS(ad5338r_channels, 10, 6); 282 DECLARE_AD5676_CHANNELS(ad5672_channels, 12, 4); 283 DECLARE_AD5679_CHANNELS(ad5674r_channels, 12, 4); 284 DECLARE_AD5676_CHANNELS(ad5676_channels, 16, 0); 285 DECLARE_AD5679_CHANNELS(ad5679r_channels, 16, 0); 286 DECLARE_AD5686_CHANNELS(ad5684_channels, 12, 4); 287 DECLARE_AD5686_CHANNELS(ad5685r_channels, 14, 2); 288 DECLARE_AD5686_CHANNELS(ad5686_channels, 16, 0); 289 DECLARE_AD5693_CHANNELS(ad5693_channels, 16, 0); 290 DECLARE_AD5693_CHANNELS(ad5692r_channels, 14, 2); 291 DECLARE_AD5693_CHANNELS(ad5691r_channels, 12, 4); 292 293 static const struct ad5686_chip_info ad5686_chip_info_tbl[] = { 294 [ID_AD5310R] = { 295 .channels = ad5310r_channels, 296 .int_vref_mv = 2500, 297 .num_channels = 1, 298 .regmap_type = AD5310_REGMAP, 299 }, 300 [ID_AD5311R] = { 301 .channels = ad5311r_channels, 302 .int_vref_mv = 2500, 303 .num_channels = 1, 304 .regmap_type = AD5693_REGMAP, 305 }, 306 [ID_AD5337R] = { 307 .channels = ad5337r_channels, 308 .int_vref_mv = 2500, 309 .num_channels = 2, 310 .regmap_type = AD5686_REGMAP, 311 }, 312 [ID_AD5338R] = { 313 .channels = ad5338r_channels, 314 .int_vref_mv = 2500, 315 .num_channels = 2, 316 .regmap_type = AD5686_REGMAP, 317 }, 318 [ID_AD5671R] = { 319 .channels = ad5672_channels, 320 .int_vref_mv = 2500, 321 .num_channels = 8, 322 .regmap_type = AD5686_REGMAP, 323 }, 324 [ID_AD5672R] = { 325 .channels = ad5672_channels, 326 .int_vref_mv = 2500, 327 .num_channels = 8, 328 .regmap_type = AD5686_REGMAP, 329 }, 330 [ID_AD5673R] = { 331 .channels = ad5674r_channels, 332 .int_vref_mv = 2500, 333 .num_channels = 16, 334 .regmap_type = AD5686_REGMAP, 335 }, 336 [ID_AD5674R] = { 337 .channels = ad5674r_channels, 338 .int_vref_mv = 2500, 339 .num_channels = 16, 340 .regmap_type = AD5686_REGMAP, 341 }, 342 [ID_AD5675R] = { 343 .channels = ad5676_channels, 344 .int_vref_mv = 2500, 345 .num_channels = 8, 346 .regmap_type = AD5686_REGMAP, 347 }, 348 [ID_AD5676] = { 349 .channels = ad5676_channels, 350 .num_channels = 8, 351 .regmap_type = AD5686_REGMAP, 352 }, 353 [ID_AD5676R] = { 354 .channels = ad5676_channels, 355 .int_vref_mv = 2500, 356 .num_channels = 8, 357 .regmap_type = AD5686_REGMAP, 358 }, 359 [ID_AD5677R] = { 360 .channels = ad5679r_channels, 361 .int_vref_mv = 2500, 362 .num_channels = 16, 363 .regmap_type = AD5686_REGMAP, 364 }, 365 [ID_AD5679R] = { 366 .channels = ad5679r_channels, 367 .int_vref_mv = 2500, 368 .num_channels = 16, 369 .regmap_type = AD5686_REGMAP, 370 }, 371 [ID_AD5681R] = { 372 .channels = ad5691r_channels, 373 .int_vref_mv = 2500, 374 .num_channels = 1, 375 .regmap_type = AD5683_REGMAP, 376 }, 377 [ID_AD5682R] = { 378 .channels = ad5692r_channels, 379 .int_vref_mv = 2500, 380 .num_channels = 1, 381 .regmap_type = AD5683_REGMAP, 382 }, 383 [ID_AD5683] = { 384 .channels = ad5693_channels, 385 .num_channels = 1, 386 .regmap_type = AD5683_REGMAP, 387 }, 388 [ID_AD5683R] = { 389 .channels = ad5693_channels, 390 .int_vref_mv = 2500, 391 .num_channels = 1, 392 .regmap_type = AD5683_REGMAP, 393 }, 394 [ID_AD5684] = { 395 .channels = ad5684_channels, 396 .num_channels = 4, 397 .regmap_type = AD5686_REGMAP, 398 }, 399 [ID_AD5684R] = { 400 .channels = ad5684_channels, 401 .int_vref_mv = 2500, 402 .num_channels = 4, 403 .regmap_type = AD5686_REGMAP, 404 }, 405 [ID_AD5685R] = { 406 .channels = ad5685r_channels, 407 .int_vref_mv = 2500, 408 .num_channels = 4, 409 .regmap_type = AD5686_REGMAP, 410 }, 411 [ID_AD5686] = { 412 .channels = ad5686_channels, 413 .num_channels = 4, 414 .regmap_type = AD5686_REGMAP, 415 }, 416 [ID_AD5686R] = { 417 .channels = ad5686_channels, 418 .int_vref_mv = 2500, 419 .num_channels = 4, 420 .regmap_type = AD5686_REGMAP, 421 }, 422 [ID_AD5691R] = { 423 .channels = ad5691r_channels, 424 .int_vref_mv = 2500, 425 .num_channels = 1, 426 .regmap_type = AD5693_REGMAP, 427 }, 428 [ID_AD5692R] = { 429 .channels = ad5692r_channels, 430 .int_vref_mv = 2500, 431 .num_channels = 1, 432 .regmap_type = AD5693_REGMAP, 433 }, 434 [ID_AD5693] = { 435 .channels = ad5693_channels, 436 .num_channels = 1, 437 .regmap_type = AD5693_REGMAP, 438 }, 439 [ID_AD5693R] = { 440 .channels = ad5693_channels, 441 .int_vref_mv = 2500, 442 .num_channels = 1, 443 .regmap_type = AD5693_REGMAP, 444 }, 445 [ID_AD5694] = { 446 .channels = ad5684_channels, 447 .num_channels = 4, 448 .regmap_type = AD5686_REGMAP, 449 }, 450 [ID_AD5694R] = { 451 .channels = ad5684_channels, 452 .int_vref_mv = 2500, 453 .num_channels = 4, 454 .regmap_type = AD5686_REGMAP, 455 }, 456 [ID_AD5695R] = { 457 .channels = ad5685r_channels, 458 .int_vref_mv = 2500, 459 .num_channels = 4, 460 .regmap_type = AD5686_REGMAP, 461 }, 462 [ID_AD5696] = { 463 .channels = ad5686_channels, 464 .num_channels = 4, 465 .regmap_type = AD5686_REGMAP, 466 }, 467 [ID_AD5696R] = { 468 .channels = ad5686_channels, 469 .int_vref_mv = 2500, 470 .num_channels = 4, 471 .regmap_type = AD5686_REGMAP, 472 }, 473 }; 474 475 int ad5686_probe(struct device *dev, 476 enum ad5686_supported_device_ids chip_type, 477 const char *name, ad5686_write_func write, 478 ad5686_read_func read) 479 { 480 struct ad5686_state *st; 481 struct iio_dev *indio_dev; 482 unsigned int val, ref_bit_msk, shift; 483 bool has_external_vref; 484 u8 cmd; 485 int ret, i; 486 487 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 488 if (indio_dev == NULL) 489 return -ENOMEM; 490 491 st = iio_priv(indio_dev); 492 493 st->dev = dev; 494 st->write = write; 495 st->read = read; 496 497 st->chip_info = &ad5686_chip_info_tbl[chip_type]; 498 499 ret = devm_regulator_get_enable_read_voltage(dev, "vcc"); 500 if (ret < 0 && ret != -ENODEV) 501 return ret; 502 503 has_external_vref = ret != -ENODEV; 504 st->vref_mv = has_external_vref ? ret / 1000 : st->chip_info->int_vref_mv; 505 506 /* Initialize masks to all ones provided the max shift (last channel) */ 507 shift = ad5686_pd_mask_shift(&st->chip_info->channels[st->chip_info->num_channels - 1]); 508 st->pwr_down_mask = GENMASK(shift + 1, 0); 509 st->pwr_down_mode = GENMASK(shift + 1, 0); 510 511 /* Set all the power down mode for all channels to 1K pulldown */ 512 for (i = 0; i < st->chip_info->num_channels; i++) { 513 shift = ad5686_pd_mask_shift(&st->chip_info->channels[i]); 514 st->pwr_down_mask &= ~(0x3U << shift); /* powered up state */ 515 st->pwr_down_mode &= ~(0x3U << shift); 516 st->pwr_down_mode |= 0x01U << shift; 517 } 518 519 indio_dev->name = name; 520 indio_dev->info = &ad5686_info; 521 indio_dev->modes = INDIO_DIRECT_MODE; 522 indio_dev->channels = st->chip_info->channels; 523 indio_dev->num_channels = st->chip_info->num_channels; 524 525 mutex_init(&st->lock); 526 527 switch (st->chip_info->regmap_type) { 528 case AD5310_REGMAP: 529 cmd = AD5686_CMD_CONTROL_REG; 530 ref_bit_msk = AD5310_REF_BIT_MSK; 531 st->use_internal_vref = !has_external_vref; 532 break; 533 case AD5683_REGMAP: 534 cmd = AD5686_CMD_CONTROL_REG; 535 ref_bit_msk = AD5683_REF_BIT_MSK; 536 st->use_internal_vref = !has_external_vref; 537 break; 538 case AD5686_REGMAP: 539 cmd = AD5686_CMD_INTERNAL_REFER_SETUP; 540 ref_bit_msk = AD5686_REF_BIT_MSK; 541 break; 542 case AD5693_REGMAP: 543 cmd = AD5686_CMD_CONTROL_REG; 544 ref_bit_msk = AD5693_REF_BIT_MSK; 545 st->use_internal_vref = !has_external_vref; 546 break; 547 default: 548 return -EINVAL; 549 } 550 551 val = has_external_vref ? ref_bit_msk : 0; 552 553 ret = st->write(st, cmd, 0, val); 554 if (ret) 555 return ret; 556 557 return devm_iio_device_register(dev, indio_dev); 558 } 559 EXPORT_SYMBOL_NS_GPL(ad5686_probe, "IIO_AD5686"); 560 561 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 562 MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC"); 563 MODULE_LICENSE("GPL v2"); 564