1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Core driver for AD5686 and similar Digital to Analog Converters 4 * 5 * Copyright 2011 Analog Devices Inc. 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bitops.h> 11 #include <linux/cleanup.h> 12 #include <linux/delay.h> 13 #include <linux/dev_printk.h> 14 #include <linux/errno.h> 15 #include <linux/export.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/kstrtox.h> 18 #include <linux/math64.h> 19 #include <linux/module.h> 20 #include <linux/property.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/reset.h> 23 #include <linux/sysfs.h> 24 #include <linux/units.h> 25 #include <linux/wordpart.h> 26 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/iio.h> 29 #include <linux/iio/trigger.h> 30 #include <linux/iio/trigger_consumer.h> 31 #include <linux/iio/triggered_buffer.h> 32 33 #include "ad5686.h" 34 35 static const char * const ad5686_powerdown_modes[] = { 36 "1kohm_to_gnd", 37 "100kohm_to_gnd", 38 "three_state" 39 }; 40 41 static int ad5310_control_sync(struct ad5686_state *st) 42 { 43 unsigned int pd_val = st->pwr_down_mask & st->pwr_down_mode; 44 45 return ad5686_write(st, AD5686_CMD_CONTROL_REG, 0, 46 FIELD_PREP(AD5310_DATA_PD_MSK, pd_val & AD5686_PD_MSK) | 47 FIELD_PREP(AD5310_DATA_REF_MSK, st->use_internal_vref ? 0 : 1) | 48 FIELD_PREP(AD5310_DATA_GAIN_MSK, st->double_scale ? 1 : 0)); 49 } 50 51 static int ad5683_control_sync(struct ad5686_state *st) 52 { 53 unsigned int pd_val = st->pwr_down_mask & st->pwr_down_mode; 54 55 return ad5686_write(st, AD5686_CMD_CONTROL_REG, 0, 56 FIELD_PREP(AD5683_DATA_PD_MSK, pd_val & AD5686_PD_MSK) | 57 FIELD_PREP(AD5683_DATA_REF_MSK, st->use_internal_vref ? 0 : 1) | 58 FIELD_PREP(AD5683_DATA_GAIN_MSK, st->double_scale ? 1 : 0)); 59 } 60 61 static inline unsigned int ad5686_pd_mask_shift(const struct iio_chan_spec *chan) 62 { 63 if (chan->channel == chan->address) 64 return chan->channel * 2; 65 66 /* one-hot encoding is used in dual/quad channel devices */ 67 return __ffs(chan->address) * 2; 68 } 69 70 static inline void ad5686_pd_field_set(const struct iio_chan_spec *chan, 71 unsigned int *pd, unsigned int val) 72 { 73 unsigned int shift = ad5686_pd_mask_shift(chan); 74 75 *pd = (*pd & ~(AD5686_PD_MSK << shift)) | ((val & AD5686_PD_MSK) << shift); 76 } 77 78 static inline unsigned int ad5686_pd_field_get(const struct iio_chan_spec *chan, 79 unsigned int pd) 80 { 81 unsigned int shift = ad5686_pd_mask_shift(chan); 82 83 return (pd >> shift) & AD5686_PD_MSK; 84 } 85 86 static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev, 87 const struct iio_chan_spec *chan) 88 { 89 struct ad5686_state *st = iio_priv(indio_dev); 90 91 guard(mutex)(&st->lock); 92 93 return ad5686_pd_field_get(chan, st->pwr_down_mode) - 1; 94 } 95 96 static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev, 97 const struct iio_chan_spec *chan, 98 unsigned int mode) 99 { 100 struct ad5686_state *st = iio_priv(indio_dev); 101 102 guard(mutex)(&st->lock); 103 ad5686_pd_field_set(chan, &st->pwr_down_mode, mode + 1); 104 105 return 0; 106 } 107 108 static const struct iio_enum ad5686_powerdown_mode_enum = { 109 .items = ad5686_powerdown_modes, 110 .num_items = ARRAY_SIZE(ad5686_powerdown_modes), 111 .get = ad5686_get_powerdown_mode, 112 .set = ad5686_set_powerdown_mode, 113 }; 114 115 static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev, 116 uintptr_t private, const struct iio_chan_spec *chan, char *buf) 117 { 118 struct ad5686_state *st = iio_priv(indio_dev); 119 120 guard(mutex)(&st->lock); 121 122 return sysfs_emit(buf, "%d\n", 123 !!ad5686_pd_field_get(chan, st->pwr_down_mask)); 124 } 125 126 static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev, 127 uintptr_t private, 128 const struct iio_chan_spec *chan, 129 const char *buf, 130 size_t len) 131 { 132 bool readin; 133 int ret; 134 struct ad5686_state *st = iio_priv(indio_dev); 135 unsigned int val; 136 u8 address; 137 138 ret = kstrtobool(buf, &readin); 139 if (ret) 140 return ret; 141 142 guard(mutex)(&st->lock); 143 144 if (readin) 145 ad5686_pd_field_set(chan, &st->pwr_down_mask, AD5686_PD_MSK_PWR_DOWN); 146 else 147 ad5686_pd_field_set(chan, &st->pwr_down_mask, AD5686_PD_MSK_PWR_UP); 148 149 switch (st->chip_info->regmap_type) { 150 case AD5310_REGMAP: 151 ret = ad5310_control_sync(st); 152 if (ret) 153 return ret; 154 break; 155 case AD5683_REGMAP: 156 ret = ad5683_control_sync(st); 157 if (ret) 158 return ret; 159 break; 160 case AD5686_REGMAP: 161 /* AD5674R/AD5679R have 16 channels and 2 powerdown registers */ 162 val = st->pwr_down_mask & st->pwr_down_mode; 163 if (chan->channel > 0x7) { 164 address = 0x8; 165 val = upper_16_bits(val); 166 } else { 167 address = 0x0; 168 val = lower_16_bits(val); 169 } 170 ret = ad5686_write(st, AD5686_CMD_POWERDOWN_DAC, address, val); 171 if (ret) 172 return ret; 173 break; 174 default: 175 return -EINVAL; 176 } 177 178 return len; 179 } 180 181 static int ad5686_read_raw(struct iio_dev *indio_dev, 182 struct iio_chan_spec const *chan, 183 int *val, 184 int *val2, 185 long m) 186 { 187 struct ad5686_state *st = iio_priv(indio_dev); 188 int ret; 189 190 guard(mutex)(&st->lock); 191 192 switch (m) { 193 case IIO_CHAN_INFO_RAW: 194 ret = ad5686_read(st, chan->address); 195 if (ret < 0) 196 return ret; 197 *val = (ret >> chan->scan_type.shift) & 198 GENMASK(chan->scan_type.realbits - 1, 0); 199 return IIO_VAL_INT; 200 case IIO_CHAN_INFO_SCALE: 201 if (st->double_scale) { 202 *val = st->scale_avail[2]; 203 *val2 = st->scale_avail[3]; 204 } else { 205 *val = st->scale_avail[0]; 206 *val2 = st->scale_avail[1]; 207 } 208 return IIO_VAL_INT_PLUS_NANO; 209 } 210 return -EINVAL; 211 } 212 213 static int ad5686_write_raw(struct iio_dev *indio_dev, 214 struct iio_chan_spec const *chan, 215 int val, 216 int val2, 217 long mask) 218 { 219 struct ad5686_state *st = iio_priv(indio_dev); 220 bool double_scale; 221 int ret; 222 223 guard(mutex)(&st->lock); 224 225 switch (mask) { 226 case IIO_CHAN_INFO_RAW: 227 if (val >= (1 << chan->scan_type.realbits) || val < 0) 228 return -EINVAL; 229 230 return ad5686_write(st, AD5686_CMD_WRITE_INPUT_N_UPDATE_N, 231 chan->address, val << chan->scan_type.shift); 232 case IIO_CHAN_INFO_SCALE: 233 if (val == st->scale_avail[0] && val2 == st->scale_avail[1]) 234 double_scale = false; 235 else if (val == st->scale_avail[2] && val2 == st->scale_avail[3]) 236 double_scale = true; 237 else 238 return -EINVAL; 239 240 if (st->double_scale == double_scale) 241 return 0; /* no change */ 242 243 if (st->chip_info->regmap_type == AD5686_REGMAP && !st->gain_gpio) 244 return -EINVAL; /* GAIN pin is board-strapped */ 245 246 st->double_scale = double_scale; 247 switch (st->chip_info->regmap_type) { 248 case AD5310_REGMAP: 249 ret = ad5310_control_sync(st); 250 break; 251 case AD5683_REGMAP: 252 ret = ad5683_control_sync(st); 253 break; 254 case AD5686_REGMAP: 255 ret = gpiod_set_value_cansleep(st->gain_gpio, 256 st->double_scale ? 1 : 0); 257 break; 258 default: 259 ret = -EINVAL; 260 } 261 if (ret) 262 st->double_scale = !double_scale; /* revert on failure */ 263 return ret; 264 default: 265 return -EINVAL; 266 } 267 } 268 269 static int ad5686_write_raw_get_fmt(struct iio_dev *indio_dev, 270 struct iio_chan_spec const *chan, 271 long mask) 272 { 273 switch (mask) { 274 case IIO_CHAN_INFO_RAW: 275 return IIO_VAL_INT; 276 case IIO_CHAN_INFO_SCALE: 277 return IIO_VAL_INT_PLUS_NANO; 278 default: 279 return -EINVAL; 280 } 281 } 282 283 static int ad5686_read_avail(struct iio_dev *indio_dev, 284 struct iio_chan_spec const *chan, 285 const int **vals, int *type, int *length, 286 long mask) 287 { 288 struct ad5686_state *st = iio_priv(indio_dev); 289 290 switch (mask) { 291 case IIO_CHAN_INFO_SCALE: 292 *type = IIO_VAL_INT_PLUS_NANO; 293 294 if (st->chip_info->regmap_type == AD5686_REGMAP && !st->gain_gpio) { 295 /* 296 * GAIN pin is board-strapped, so only the current 297 * scale is available. 298 */ 299 *vals = st->double_scale ? &st->scale_avail[2] : 300 &st->scale_avail[0]; 301 *length = 2; 302 return IIO_AVAIL_LIST; 303 } 304 305 *vals = st->scale_avail; 306 *length = ARRAY_SIZE(st->scale_avail); 307 return IIO_AVAIL_LIST; 308 default: 309 return -EINVAL; 310 } 311 } 312 313 static const struct iio_info ad5686_info = { 314 .read_raw = ad5686_read_raw, 315 .write_raw = ad5686_write_raw, 316 .write_raw_get_fmt = ad5686_write_raw_get_fmt, 317 .read_avail = ad5686_read_avail, 318 }; 319 320 static const struct iio_chan_spec_ext_info ad5686_ext_info[] = { 321 { 322 .name = "powerdown", 323 .read = ad5686_read_dac_powerdown, 324 .write = ad5686_write_dac_powerdown, 325 .shared = IIO_SEPARATE, 326 }, 327 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5686_powerdown_mode_enum), 328 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5686_powerdown_mode_enum), 329 { } 330 }; 331 332 #define AD5868_CHANNEL(chan, addr, bits, _shift) { \ 333 .type = IIO_VOLTAGE, \ 334 .indexed = 1, \ 335 .output = 1, \ 336 .channel = chan, \ 337 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 338 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\ 339 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE),\ 340 .address = addr, \ 341 .scan_index = chan, \ 342 .scan_type = { \ 343 .sign = 'u', \ 344 .realbits = (bits), \ 345 .storagebits = 16, \ 346 .shift = (_shift), \ 347 }, \ 348 .ext_info = ad5686_ext_info, \ 349 } 350 351 #define DECLARE_AD5683_CHANNELS(name, bits, _shift) \ 352 static const struct iio_chan_spec name[] = { \ 353 AD5868_CHANNEL(0, 0, bits, _shift), \ 354 } 355 356 #define DECLARE_AD5338_CHANNELS(name, bits, _shift) \ 357 static const struct iio_chan_spec name[] = { \ 358 AD5868_CHANNEL(0, 1, bits, _shift), \ 359 AD5868_CHANNEL(1, 8, bits, _shift), \ 360 } 361 362 #define DECLARE_AD5686_CHANNELS(name, bits, _shift) \ 363 static const struct iio_chan_spec name[] = { \ 364 AD5868_CHANNEL(0, 1, bits, _shift), \ 365 AD5868_CHANNEL(1, 2, bits, _shift), \ 366 AD5868_CHANNEL(2, 4, bits, _shift), \ 367 AD5868_CHANNEL(3, 8, bits, _shift), \ 368 } 369 370 #define DECLARE_AD5676_CHANNELS(name, bits, _shift) \ 371 static const struct iio_chan_spec name[] = { \ 372 AD5868_CHANNEL(0, 0, bits, _shift), \ 373 AD5868_CHANNEL(1, 1, bits, _shift), \ 374 AD5868_CHANNEL(2, 2, bits, _shift), \ 375 AD5868_CHANNEL(3, 3, bits, _shift), \ 376 AD5868_CHANNEL(4, 4, bits, _shift), \ 377 AD5868_CHANNEL(5, 5, bits, _shift), \ 378 AD5868_CHANNEL(6, 6, bits, _shift), \ 379 AD5868_CHANNEL(7, 7, bits, _shift), \ 380 } 381 382 #define DECLARE_AD5679_CHANNELS(name, bits, _shift) \ 383 static const struct iio_chan_spec name[] = { \ 384 AD5868_CHANNEL(0, 0, bits, _shift), \ 385 AD5868_CHANNEL(1, 1, bits, _shift), \ 386 AD5868_CHANNEL(2, 2, bits, _shift), \ 387 AD5868_CHANNEL(3, 3, bits, _shift), \ 388 AD5868_CHANNEL(4, 4, bits, _shift), \ 389 AD5868_CHANNEL(5, 5, bits, _shift), \ 390 AD5868_CHANNEL(6, 6, bits, _shift), \ 391 AD5868_CHANNEL(7, 7, bits, _shift), \ 392 AD5868_CHANNEL(8, 8, bits, _shift), \ 393 AD5868_CHANNEL(9, 9, bits, _shift), \ 394 AD5868_CHANNEL(10, 10, bits, _shift), \ 395 AD5868_CHANNEL(11, 11, bits, _shift), \ 396 AD5868_CHANNEL(12, 12, bits, _shift), \ 397 AD5868_CHANNEL(13, 13, bits, _shift), \ 398 AD5868_CHANNEL(14, 14, bits, _shift), \ 399 AD5868_CHANNEL(15, 15, bits, _shift), \ 400 } 401 402 /* single-channel */ 403 DECLARE_AD5683_CHANNELS(ad5310r_channels, 10, 2); 404 DECLARE_AD5683_CHANNELS(ad5311r_channels, 10, 6); 405 DECLARE_AD5683_CHANNELS(ad5681r_channels, 12, 4); 406 DECLARE_AD5683_CHANNELS(ad5682r_channels, 14, 2); 407 DECLARE_AD5683_CHANNELS(ad5683r_channels, 16, 0); 408 409 /* dual-channel */ 410 DECLARE_AD5338_CHANNELS(ad5337r_channels, 8, 8); 411 DECLARE_AD5338_CHANNELS(ad5338r_channels, 10, 6); 412 DECLARE_AD5338_CHANNELS(ad5687r_channels, 12, 4); 413 DECLARE_AD5338_CHANNELS(ad5689r_channels, 16, 0); 414 415 /* quad-channel */ 416 DECLARE_AD5686_CHANNELS(ad5317r_channels, 10, 6); 417 DECLARE_AD5686_CHANNELS(ad5684r_channels, 12, 4); 418 DECLARE_AD5686_CHANNELS(ad5685r_channels, 14, 2); 419 DECLARE_AD5686_CHANNELS(ad5686r_channels, 16, 0); 420 421 /* 8-channel */ 422 DECLARE_AD5676_CHANNELS(ad5672r_channels, 12, 4); 423 DECLARE_AD5676_CHANNELS(ad5676r_channels, 16, 0); 424 425 /* 16-channel */ 426 DECLARE_AD5679_CHANNELS(ad5674r_channels, 12, 4); 427 DECLARE_AD5679_CHANNELS(ad5679r_channels, 16, 0); 428 429 const struct ad5686_chip_info ad5310r_chip_info = { 430 .channels = ad5310r_channels, 431 .int_vref_mv = 2500, 432 .num_channels = 1, 433 .regmap_type = AD5310_REGMAP, 434 }; 435 EXPORT_SYMBOL_NS_GPL(ad5310r_chip_info, "IIO_AD5686"); 436 437 const struct ad5686_chip_info ad5311r_chip_info = { 438 .channels = ad5311r_channels, 439 .int_vref_mv = 2500, 440 .num_channels = 1, 441 .regmap_type = AD5683_REGMAP, 442 }; 443 EXPORT_SYMBOL_NS_GPL(ad5311r_chip_info, "IIO_AD5686"); 444 445 const struct ad5686_chip_info ad5681r_chip_info = { 446 .channels = ad5681r_channels, 447 .int_vref_mv = 2500, 448 .num_channels = 1, 449 .regmap_type = AD5683_REGMAP, 450 }; 451 EXPORT_SYMBOL_NS_GPL(ad5681r_chip_info, "IIO_AD5686"); 452 453 const struct ad5686_chip_info ad5682r_chip_info = { 454 .channels = ad5682r_channels, 455 .int_vref_mv = 2500, 456 .num_channels = 1, 457 .regmap_type = AD5683_REGMAP, 458 }; 459 EXPORT_SYMBOL_NS_GPL(ad5682r_chip_info, "IIO_AD5686"); 460 461 const struct ad5686_chip_info ad5683_chip_info = { 462 .channels = ad5683r_channels, 463 .num_channels = 1, 464 .regmap_type = AD5683_REGMAP, 465 }; 466 EXPORT_SYMBOL_NS_GPL(ad5683_chip_info, "IIO_AD5686"); 467 468 const struct ad5686_chip_info ad5683r_chip_info = { 469 .channels = ad5683r_channels, 470 .int_vref_mv = 2500, 471 .num_channels = 1, 472 .regmap_type = AD5683_REGMAP, 473 }; 474 EXPORT_SYMBOL_NS_GPL(ad5683r_chip_info, "IIO_AD5686"); 475 476 const struct ad5686_chip_info ad5337r_chip_info = { 477 .channels = ad5337r_channels, 478 .int_vref_mv = 2500, 479 .num_channels = 2, 480 .regmap_type = AD5686_REGMAP, 481 }; 482 EXPORT_SYMBOL_NS_GPL(ad5337r_chip_info, "IIO_AD5686"); 483 484 const struct ad5686_chip_info ad5338r_chip_info = { 485 .channels = ad5338r_channels, 486 .int_vref_mv = 2500, 487 .num_channels = 2, 488 .regmap_type = AD5686_REGMAP, 489 }; 490 EXPORT_SYMBOL_NS_GPL(ad5338r_chip_info, "IIO_AD5686"); 491 492 const struct ad5686_chip_info ad5687_chip_info = { 493 .channels = ad5687r_channels, 494 .num_channels = 2, 495 .regmap_type = AD5686_REGMAP, 496 }; 497 EXPORT_SYMBOL_NS_GPL(ad5687_chip_info, "IIO_AD5686"); 498 499 const struct ad5686_chip_info ad5687r_chip_info = { 500 .channels = ad5687r_channels, 501 .int_vref_mv = 2500, 502 .num_channels = 2, 503 .regmap_type = AD5686_REGMAP, 504 }; 505 EXPORT_SYMBOL_NS_GPL(ad5687r_chip_info, "IIO_AD5686"); 506 507 const struct ad5686_chip_info ad5689_chip_info = { 508 .channels = ad5689r_channels, 509 .num_channels = 2, 510 .regmap_type = AD5686_REGMAP, 511 }; 512 EXPORT_SYMBOL_NS_GPL(ad5689_chip_info, "IIO_AD5686"); 513 514 const struct ad5686_chip_info ad5689r_chip_info = { 515 .channels = ad5689r_channels, 516 .int_vref_mv = 2500, 517 .num_channels = 2, 518 .regmap_type = AD5686_REGMAP, 519 }; 520 EXPORT_SYMBOL_NS_GPL(ad5689r_chip_info, "IIO_AD5686"); 521 522 const struct ad5686_chip_info ad5317r_chip_info = { 523 .channels = ad5317r_channels, 524 .int_vref_mv = 2500, 525 .num_channels = 4, 526 .regmap_type = AD5686_REGMAP, 527 }; 528 EXPORT_SYMBOL_NS_GPL(ad5317r_chip_info, "IIO_AD5686"); 529 530 const struct ad5686_chip_info ad5684_chip_info = { 531 .channels = ad5684r_channels, 532 .num_channels = 4, 533 .regmap_type = AD5686_REGMAP, 534 }; 535 EXPORT_SYMBOL_NS_GPL(ad5684_chip_info, "IIO_AD5686"); 536 537 const struct ad5686_chip_info ad5684r_chip_info = { 538 .channels = ad5684r_channels, 539 .int_vref_mv = 2500, 540 .num_channels = 4, 541 .regmap_type = AD5686_REGMAP, 542 }; 543 EXPORT_SYMBOL_NS_GPL(ad5684r_chip_info, "IIO_AD5686"); 544 545 const struct ad5686_chip_info ad5685r_chip_info = { 546 .channels = ad5685r_channels, 547 .int_vref_mv = 2500, 548 .num_channels = 4, 549 .regmap_type = AD5686_REGMAP, 550 }; 551 EXPORT_SYMBOL_NS_GPL(ad5685r_chip_info, "IIO_AD5686"); 552 553 const struct ad5686_chip_info ad5686_chip_info = { 554 .channels = ad5686r_channels, 555 .num_channels = 4, 556 .regmap_type = AD5686_REGMAP, 557 }; 558 EXPORT_SYMBOL_NS_GPL(ad5686_chip_info, "IIO_AD5686"); 559 560 const struct ad5686_chip_info ad5686r_chip_info = { 561 .channels = ad5686r_channels, 562 .int_vref_mv = 2500, 563 .num_channels = 4, 564 .regmap_type = AD5686_REGMAP, 565 }; 566 EXPORT_SYMBOL_NS_GPL(ad5686r_chip_info, "IIO_AD5686"); 567 568 const struct ad5686_chip_info ad5672r_chip_info = { 569 .channels = ad5672r_channels, 570 .int_vref_mv = 2500, 571 .num_channels = 8, 572 .regmap_type = AD5686_REGMAP, 573 }; 574 EXPORT_SYMBOL_NS_GPL(ad5672r_chip_info, "IIO_AD5686"); 575 576 const struct ad5686_chip_info ad5676_chip_info = { 577 .channels = ad5676r_channels, 578 .num_channels = 8, 579 .regmap_type = AD5686_REGMAP, 580 }; 581 EXPORT_SYMBOL_NS_GPL(ad5676_chip_info, "IIO_AD5686"); 582 583 const struct ad5686_chip_info ad5676r_chip_info = { 584 .channels = ad5676r_channels, 585 .int_vref_mv = 2500, 586 .num_channels = 8, 587 .regmap_type = AD5686_REGMAP, 588 }; 589 EXPORT_SYMBOL_NS_GPL(ad5676r_chip_info, "IIO_AD5686"); 590 591 const struct ad5686_chip_info ad5674_chip_info = { 592 .channels = ad5674r_channels, 593 .num_channels = 16, 594 .regmap_type = AD5686_REGMAP, 595 }; 596 EXPORT_SYMBOL_NS_GPL(ad5674_chip_info, "IIO_AD5686"); 597 598 const struct ad5686_chip_info ad5674r_chip_info = { 599 .channels = ad5674r_channels, 600 .int_vref_mv = 2500, 601 .num_channels = 16, 602 .regmap_type = AD5686_REGMAP, 603 }; 604 EXPORT_SYMBOL_NS_GPL(ad5674r_chip_info, "IIO_AD5686"); 605 606 const struct ad5686_chip_info ad5679_chip_info = { 607 .channels = ad5679r_channels, 608 .num_channels = 16, 609 .regmap_type = AD5686_REGMAP, 610 }; 611 EXPORT_SYMBOL_NS_GPL(ad5679_chip_info, "IIO_AD5686"); 612 613 const struct ad5686_chip_info ad5679r_chip_info = { 614 .channels = ad5679r_channels, 615 .int_vref_mv = 2500, 616 .num_channels = 16, 617 .regmap_type = AD5686_REGMAP, 618 }; 619 EXPORT_SYMBOL_NS_GPL(ad5679r_chip_info, "IIO_AD5686"); 620 621 static void ad5686_init_scale_avail(struct ad5686_state *st) 622 { 623 int realbits = st->chip_info->channels[0].scan_type.realbits; 624 s64 tmp = 2ULL * st->vref_mv * NANO >> realbits; 625 626 st->scale_avail[2] = div_s64_rem(tmp, NANO, &st->scale_avail[3]); 627 st->scale_avail[0] = div_s64_rem(tmp >> 1, NANO, &st->scale_avail[1]); 628 } 629 630 static void do_ad5686_trigger_handler(struct iio_dev *indio_dev) 631 { 632 struct ad5686_state *st = iio_priv(indio_dev); 633 u16 val[AD5686_MAX_CHANNELS] = { }; 634 unsigned int scan_count, ch, i; 635 bool async_update; 636 u8 cmd; 637 638 if (iio_pop_from_buffer(indio_dev->buffer, val)) 639 return; 640 641 guard(mutex)(&st->lock); 642 643 scan_count = bitmap_weight(indio_dev->active_scan_mask, 644 iio_get_masklength(indio_dev)); 645 async_update = st->ldac_gpio && scan_count > 1; 646 if (async_update) { 647 /* use LDAC to update all channels simultaneously */ 648 cmd = AD5686_CMD_WRITE_INPUT_N; 649 gpiod_set_value_cansleep(st->ldac_gpio, 0); 650 } else { 651 cmd = AD5686_CMD_WRITE_INPUT_N_UPDATE_N; 652 } 653 654 i = 0; 655 iio_for_each_active_channel(indio_dev, ch) { 656 if (st->ops->write(st, cmd, indio_dev->channels[ch].address, val[i++])) 657 break; 658 } 659 660 /* 661 * If sync() is available, it is called here regardless of write 662 * failure to allow bus implementation to reset. In that case, partial 663 * writes are unlikely as the write operations would just queue up 664 * the transfers. 665 */ 666 if (st->ops->sync) 667 st->ops->sync(st); 668 669 if (async_update) 670 gpiod_set_value_cansleep(st->ldac_gpio, 1); 671 } 672 673 static irqreturn_t ad5686_trigger_handler(int irq, void *p) 674 { 675 struct iio_poll_func *pf = p; 676 struct iio_dev *indio_dev = pf->indio_dev; 677 678 do_ad5686_trigger_handler(indio_dev); 679 iio_trigger_notify_done(indio_dev->trig); 680 return IRQ_HANDLED; 681 } 682 683 int ad5686_probe(struct device *dev, 684 const struct ad5686_chip_info *chip_info, 685 const char *name, const struct ad5686_bus_ops *ops, 686 void *bus_data) 687 { 688 struct reset_control *rstc; 689 struct ad5686_state *st; 690 struct iio_dev *indio_dev; 691 int ret, i; 692 693 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 694 if (indio_dev == NULL) 695 return -ENOMEM; 696 697 st = iio_priv(indio_dev); 698 699 st->dev = dev; 700 st->ops = ops; 701 st->bus_data = bus_data; 702 st->chip_info = chip_info; 703 704 rstc = devm_reset_control_get_optional_exclusive(dev, NULL); 705 if (IS_ERR(rstc)) 706 return dev_err_probe(dev, PTR_ERR(rstc), 707 "Failed to get reset control\n"); 708 709 ret = devm_regulator_get_enable(dev, "vdd"); 710 if (ret) 711 return dev_err_probe(dev, ret, "failed to enable vdd supply\n"); 712 713 ret = devm_regulator_get_enable(dev, "vlogic"); 714 if (ret) 715 return dev_err_probe(dev, ret, "failed to enable vlogic supply\n"); 716 717 ret = devm_regulator_get_enable_read_voltage(dev, "vref"); 718 if (ret == -ENODEV) /* vcc-supply is deprecated, but supported still */ 719 ret = devm_regulator_get_enable_read_voltage(dev, "vcc"); 720 if (ret < 0 && ret != -ENODEV) 721 return dev_err_probe(dev, ret, "failed to read vref voltage\n"); 722 723 st->use_internal_vref = ret == -ENODEV; 724 st->vref_mv = st->use_internal_vref ? st->chip_info->int_vref_mv : ret / 1000; 725 if (!st->vref_mv) 726 return dev_err_probe(dev, -EINVAL, 727 "invalid or not provided vref voltage\n"); 728 729 /* 4.5us power-up time: Datasheet Table 4: Timing Characteristics */ 730 fsleep(5); 731 732 /* 1us >> 30ns reset pulse activation time: Datasheet Table 4 */ 733 reset_control_assert(rstc); 734 fsleep(1); 735 reset_control_deassert(rstc); 736 737 st->ldac_gpio = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH); 738 if (IS_ERR(st->ldac_gpio)) 739 return dev_err_probe(dev, PTR_ERR(st->ldac_gpio), 740 "Failed to get LDAC GPIO\n"); 741 742 st->double_scale = device_property_read_bool(dev, "adi,range-double"); 743 st->gain_gpio = devm_gpiod_get_optional(dev, "gain", 744 st->double_scale ? GPIOD_OUT_HIGH : 745 GPIOD_OUT_LOW); 746 if (IS_ERR(st->gain_gpio)) 747 return dev_err_probe(dev, PTR_ERR(st->gain_gpio), 748 "Failed to get GAIN GPIO\n"); 749 750 ad5686_init_scale_avail(st); 751 752 /* Initialize masks to all ones */ 753 st->pwr_down_mask = ~0; 754 st->pwr_down_mode = ~0; 755 756 /* Set all the power down mode for all channels to 1K pulldown */ 757 for (i = 0; i < st->chip_info->num_channels; i++) { 758 ad5686_pd_field_set(&st->chip_info->channels[i], 759 &st->pwr_down_mask, AD5686_PD_MSK_PWR_UP); 760 ad5686_pd_field_set(&st->chip_info->channels[i], 761 &st->pwr_down_mode, AD5686_PD_MODE_1K_TO_GND); 762 } 763 764 indio_dev->name = name; 765 indio_dev->info = &ad5686_info; 766 indio_dev->modes = INDIO_DIRECT_MODE; 767 indio_dev->channels = st->chip_info->channels; 768 indio_dev->num_channels = st->chip_info->num_channels; 769 770 ret = devm_mutex_init(dev, &st->lock); 771 if (ret) 772 return ret; 773 774 switch (st->chip_info->regmap_type) { 775 case AD5310_REGMAP: 776 ret = ad5310_control_sync(st); 777 if (ret) 778 return ret; 779 break; 780 case AD5683_REGMAP: 781 ret = ad5683_control_sync(st); 782 if (ret) 783 return ret; 784 break; 785 case AD5686_REGMAP: 786 ret = ad5686_write(st, AD5686_CMD_INTERNAL_REFER_SETUP, 0, 787 st->use_internal_vref ? 0 : AD5686_DATA_REF_MSK); 788 if (ret) 789 return ret; 790 break; 791 default: 792 return -EINVAL; 793 } 794 795 ret = devm_iio_triggered_buffer_setup_ext(dev, indio_dev, NULL, 796 &ad5686_trigger_handler, 797 IIO_BUFFER_DIRECTION_OUT, 798 NULL, NULL); 799 if (ret) 800 return ret; 801 802 return devm_iio_device_register(dev, indio_dev); 803 } 804 EXPORT_SYMBOL_NS_GPL(ad5686_probe, "IIO_AD5686"); 805 806 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 807 MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC"); 808 MODULE_LICENSE("GPL v2"); 809