1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD5686R, AD5685R, AD5684R Digital to analog converters driver 4 * 5 * Copyright 2011 Analog Devices Inc. 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bitops.h> 11 #include <linux/delay.h> 12 #include <linux/dev_printk.h> 13 #include <linux/errno.h> 14 #include <linux/export.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/kstrtox.h> 17 #include <linux/module.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/sysfs.h> 21 #include <linux/wordpart.h> 22 23 #include <linux/iio/iio.h> 24 25 #include "ad5686.h" 26 27 static const char * const ad5686_powerdown_modes[] = { 28 "1kohm_to_gnd", 29 "100kohm_to_gnd", 30 "three_state" 31 }; 32 33 static int ad5310_control_sync(struct ad5686_state *st) 34 { 35 unsigned int pd_val = st->pwr_down_mask & st->pwr_down_mode; 36 37 return ad5686_write(st, AD5686_CMD_CONTROL_REG, 0, 38 FIELD_PREP(AD5310_PD_MSK, pd_val & AD5686_PD_MSK) | 39 FIELD_PREP(AD5310_REF_BIT_MSK, st->use_internal_vref ? 0 : 1)); 40 } 41 42 static int ad5683_control_sync(struct ad5686_state *st) 43 { 44 unsigned int pd_val = st->pwr_down_mask & st->pwr_down_mode; 45 46 return ad5686_write(st, AD5686_CMD_CONTROL_REG, 0, 47 FIELD_PREP(AD5683_PD_MSK, pd_val & AD5686_PD_MSK) | 48 FIELD_PREP(AD5683_REF_BIT_MSK, st->use_internal_vref ? 0 : 1)); 49 } 50 51 static inline unsigned int ad5686_pd_mask_shift(const struct iio_chan_spec *chan) 52 { 53 if (chan->channel == chan->address) 54 return chan->channel * 2; 55 56 /* one-hot encoding is used in dual/quad channel devices */ 57 return __ffs(chan->address) * 2; 58 } 59 60 static inline void ad5686_pd_field_set(const struct iio_chan_spec *chan, 61 unsigned int *pd, unsigned int val) 62 { 63 unsigned int shift = ad5686_pd_mask_shift(chan); 64 65 *pd = (*pd & ~(AD5686_PD_MSK << shift)) | ((val & AD5686_PD_MSK) << shift); 66 } 67 68 static inline unsigned int ad5686_pd_field_get(const struct iio_chan_spec *chan, 69 unsigned int pd) 70 { 71 unsigned int shift = ad5686_pd_mask_shift(chan); 72 73 return (pd >> shift) & AD5686_PD_MSK; 74 } 75 76 static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev, 77 const struct iio_chan_spec *chan) 78 { 79 struct ad5686_state *st = iio_priv(indio_dev); 80 81 guard(mutex)(&st->lock); 82 83 return ad5686_pd_field_get(chan, st->pwr_down_mode) - 1; 84 } 85 86 static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev, 87 const struct iio_chan_spec *chan, 88 unsigned int mode) 89 { 90 struct ad5686_state *st = iio_priv(indio_dev); 91 92 guard(mutex)(&st->lock); 93 ad5686_pd_field_set(chan, &st->pwr_down_mode, mode + 1); 94 95 return 0; 96 } 97 98 static const struct iio_enum ad5686_powerdown_mode_enum = { 99 .items = ad5686_powerdown_modes, 100 .num_items = ARRAY_SIZE(ad5686_powerdown_modes), 101 .get = ad5686_get_powerdown_mode, 102 .set = ad5686_set_powerdown_mode, 103 }; 104 105 static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev, 106 uintptr_t private, const struct iio_chan_spec *chan, char *buf) 107 { 108 struct ad5686_state *st = iio_priv(indio_dev); 109 110 guard(mutex)(&st->lock); 111 112 return sysfs_emit(buf, "%d\n", 113 !!ad5686_pd_field_get(chan, st->pwr_down_mask)); 114 } 115 116 static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev, 117 uintptr_t private, 118 const struct iio_chan_spec *chan, 119 const char *buf, 120 size_t len) 121 { 122 bool readin; 123 int ret; 124 struct ad5686_state *st = iio_priv(indio_dev); 125 unsigned int val; 126 u8 address; 127 128 ret = kstrtobool(buf, &readin); 129 if (ret) 130 return ret; 131 132 guard(mutex)(&st->lock); 133 134 if (readin) 135 ad5686_pd_field_set(chan, &st->pwr_down_mask, AD5686_PD_MSK_PWR_DOWN); 136 else 137 ad5686_pd_field_set(chan, &st->pwr_down_mask, AD5686_PD_MSK_PWR_UP); 138 139 switch (st->chip_info->regmap_type) { 140 case AD5310_REGMAP: 141 ret = ad5310_control_sync(st); 142 if (ret) 143 return ret; 144 break; 145 case AD5683_REGMAP: 146 ret = ad5683_control_sync(st); 147 if (ret) 148 return ret; 149 break; 150 case AD5686_REGMAP: 151 /* AD5674R/AD5679R have 16 channels and 2 powerdown registers */ 152 val = st->pwr_down_mask & st->pwr_down_mode; 153 if (chan->channel > 0x7) { 154 address = 0x8; 155 val = upper_16_bits(val); 156 } else { 157 address = 0x0; 158 val = lower_16_bits(val); 159 } 160 ret = ad5686_write(st, AD5686_CMD_POWERDOWN_DAC, address, val); 161 if (ret) 162 return ret; 163 break; 164 default: 165 return -EINVAL; 166 } 167 168 return len; 169 } 170 171 static int ad5686_read_raw(struct iio_dev *indio_dev, 172 struct iio_chan_spec const *chan, 173 int *val, 174 int *val2, 175 long m) 176 { 177 struct ad5686_state *st = iio_priv(indio_dev); 178 int ret; 179 180 switch (m) { 181 case IIO_CHAN_INFO_RAW: 182 mutex_lock(&st->lock); 183 ret = ad5686_read(st, chan->address); 184 mutex_unlock(&st->lock); 185 if (ret < 0) 186 return ret; 187 *val = (ret >> chan->scan_type.shift) & 188 GENMASK(chan->scan_type.realbits - 1, 0); 189 return IIO_VAL_INT; 190 case IIO_CHAN_INFO_SCALE: 191 *val = st->vref_mv; 192 *val2 = chan->scan_type.realbits; 193 return IIO_VAL_FRACTIONAL_LOG2; 194 } 195 return -EINVAL; 196 } 197 198 static int ad5686_write_raw(struct iio_dev *indio_dev, 199 struct iio_chan_spec const *chan, 200 int val, 201 int val2, 202 long mask) 203 { 204 struct ad5686_state *st = iio_priv(indio_dev); 205 int ret; 206 207 switch (mask) { 208 case IIO_CHAN_INFO_RAW: 209 if (val >= (1 << chan->scan_type.realbits) || val < 0) 210 return -EINVAL; 211 212 mutex_lock(&st->lock); 213 ret = ad5686_write(st, AD5686_CMD_WRITE_INPUT_N_UPDATE_N, 214 chan->address, val << chan->scan_type.shift); 215 mutex_unlock(&st->lock); 216 break; 217 default: 218 ret = -EINVAL; 219 } 220 221 return ret; 222 } 223 224 static const struct iio_info ad5686_info = { 225 .read_raw = ad5686_read_raw, 226 .write_raw = ad5686_write_raw, 227 }; 228 229 static const struct iio_chan_spec_ext_info ad5686_ext_info[] = { 230 { 231 .name = "powerdown", 232 .read = ad5686_read_dac_powerdown, 233 .write = ad5686_write_dac_powerdown, 234 .shared = IIO_SEPARATE, 235 }, 236 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5686_powerdown_mode_enum), 237 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5686_powerdown_mode_enum), 238 { } 239 }; 240 241 #define AD5868_CHANNEL(chan, addr, bits, _shift) { \ 242 .type = IIO_VOLTAGE, \ 243 .indexed = 1, \ 244 .output = 1, \ 245 .channel = chan, \ 246 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 247 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\ 248 .address = addr, \ 249 .scan_type = { \ 250 .sign = 'u', \ 251 .realbits = (bits), \ 252 .storagebits = 16, \ 253 .shift = (_shift), \ 254 }, \ 255 .ext_info = ad5686_ext_info, \ 256 } 257 258 #define DECLARE_AD5683_CHANNELS(name, bits, _shift) \ 259 static const struct iio_chan_spec name[] = { \ 260 AD5868_CHANNEL(0, 0, bits, _shift), \ 261 } 262 263 #define DECLARE_AD5338_CHANNELS(name, bits, _shift) \ 264 static const struct iio_chan_spec name[] = { \ 265 AD5868_CHANNEL(0, 1, bits, _shift), \ 266 AD5868_CHANNEL(1, 8, bits, _shift), \ 267 } 268 269 #define DECLARE_AD5686_CHANNELS(name, bits, _shift) \ 270 static const struct iio_chan_spec name[] = { \ 271 AD5868_CHANNEL(0, 1, bits, _shift), \ 272 AD5868_CHANNEL(1, 2, bits, _shift), \ 273 AD5868_CHANNEL(2, 4, bits, _shift), \ 274 AD5868_CHANNEL(3, 8, bits, _shift), \ 275 } 276 277 #define DECLARE_AD5676_CHANNELS(name, bits, _shift) \ 278 static const struct iio_chan_spec name[] = { \ 279 AD5868_CHANNEL(0, 0, bits, _shift), \ 280 AD5868_CHANNEL(1, 1, bits, _shift), \ 281 AD5868_CHANNEL(2, 2, bits, _shift), \ 282 AD5868_CHANNEL(3, 3, bits, _shift), \ 283 AD5868_CHANNEL(4, 4, bits, _shift), \ 284 AD5868_CHANNEL(5, 5, bits, _shift), \ 285 AD5868_CHANNEL(6, 6, bits, _shift), \ 286 AD5868_CHANNEL(7, 7, bits, _shift), \ 287 } 288 289 #define DECLARE_AD5679_CHANNELS(name, bits, _shift) \ 290 static const struct iio_chan_spec name[] = { \ 291 AD5868_CHANNEL(0, 0, bits, _shift), \ 292 AD5868_CHANNEL(1, 1, bits, _shift), \ 293 AD5868_CHANNEL(2, 2, bits, _shift), \ 294 AD5868_CHANNEL(3, 3, bits, _shift), \ 295 AD5868_CHANNEL(4, 4, bits, _shift), \ 296 AD5868_CHANNEL(5, 5, bits, _shift), \ 297 AD5868_CHANNEL(6, 6, bits, _shift), \ 298 AD5868_CHANNEL(7, 7, bits, _shift), \ 299 AD5868_CHANNEL(8, 8, bits, _shift), \ 300 AD5868_CHANNEL(9, 9, bits, _shift), \ 301 AD5868_CHANNEL(10, 10, bits, _shift), \ 302 AD5868_CHANNEL(11, 11, bits, _shift), \ 303 AD5868_CHANNEL(12, 12, bits, _shift), \ 304 AD5868_CHANNEL(13, 13, bits, _shift), \ 305 AD5868_CHANNEL(14, 14, bits, _shift), \ 306 AD5868_CHANNEL(15, 15, bits, _shift), \ 307 } 308 309 /* single-channel */ 310 DECLARE_AD5683_CHANNELS(ad5310r_channels, 10, 2); 311 DECLARE_AD5683_CHANNELS(ad5311r_channels, 10, 6); 312 DECLARE_AD5683_CHANNELS(ad5681r_channels, 12, 4); 313 DECLARE_AD5683_CHANNELS(ad5682r_channels, 14, 2); 314 DECLARE_AD5683_CHANNELS(ad5683r_channels, 16, 0); 315 316 /* dual-channel */ 317 DECLARE_AD5338_CHANNELS(ad5337r_channels, 8, 8); 318 DECLARE_AD5338_CHANNELS(ad5338r_channels, 10, 6); 319 320 /* quad-channel */ 321 DECLARE_AD5686_CHANNELS(ad5684r_channels, 12, 4); 322 DECLARE_AD5686_CHANNELS(ad5685r_channels, 14, 2); 323 DECLARE_AD5686_CHANNELS(ad5686r_channels, 16, 0); 324 325 /* 8-channel */ 326 DECLARE_AD5676_CHANNELS(ad5672r_channels, 12, 4); 327 DECLARE_AD5676_CHANNELS(ad5676r_channels, 16, 0); 328 329 /* 16-channel */ 330 DECLARE_AD5679_CHANNELS(ad5674r_channels, 12, 4); 331 DECLARE_AD5679_CHANNELS(ad5679r_channels, 16, 0); 332 333 const struct ad5686_chip_info ad5310r_chip_info = { 334 .channels = ad5310r_channels, 335 .int_vref_mv = 2500, 336 .num_channels = 1, 337 .regmap_type = AD5310_REGMAP, 338 }; 339 EXPORT_SYMBOL_NS_GPL(ad5310r_chip_info, "IIO_AD5686"); 340 341 const struct ad5686_chip_info ad5311r_chip_info = { 342 .channels = ad5311r_channels, 343 .int_vref_mv = 2500, 344 .num_channels = 1, 345 .regmap_type = AD5683_REGMAP, 346 }; 347 EXPORT_SYMBOL_NS_GPL(ad5311r_chip_info, "IIO_AD5686"); 348 349 const struct ad5686_chip_info ad5681r_chip_info = { 350 .channels = ad5681r_channels, 351 .int_vref_mv = 2500, 352 .num_channels = 1, 353 .regmap_type = AD5683_REGMAP, 354 }; 355 EXPORT_SYMBOL_NS_GPL(ad5681r_chip_info, "IIO_AD5686"); 356 357 const struct ad5686_chip_info ad5682r_chip_info = { 358 .channels = ad5682r_channels, 359 .int_vref_mv = 2500, 360 .num_channels = 1, 361 .regmap_type = AD5683_REGMAP, 362 }; 363 EXPORT_SYMBOL_NS_GPL(ad5682r_chip_info, "IIO_AD5686"); 364 365 const struct ad5686_chip_info ad5683_chip_info = { 366 .channels = ad5683r_channels, 367 .num_channels = 1, 368 .regmap_type = AD5683_REGMAP, 369 }; 370 EXPORT_SYMBOL_NS_GPL(ad5683_chip_info, "IIO_AD5686"); 371 372 const struct ad5686_chip_info ad5683r_chip_info = { 373 .channels = ad5683r_channels, 374 .int_vref_mv = 2500, 375 .num_channels = 1, 376 .regmap_type = AD5683_REGMAP, 377 }; 378 EXPORT_SYMBOL_NS_GPL(ad5683r_chip_info, "IIO_AD5686"); 379 380 const struct ad5686_chip_info ad5337r_chip_info = { 381 .channels = ad5337r_channels, 382 .int_vref_mv = 2500, 383 .num_channels = 2, 384 .regmap_type = AD5686_REGMAP, 385 }; 386 EXPORT_SYMBOL_NS_GPL(ad5337r_chip_info, "IIO_AD5686"); 387 388 const struct ad5686_chip_info ad5338r_chip_info = { 389 .channels = ad5338r_channels, 390 .int_vref_mv = 2500, 391 .num_channels = 2, 392 .regmap_type = AD5686_REGMAP, 393 }; 394 EXPORT_SYMBOL_NS_GPL(ad5338r_chip_info, "IIO_AD5686"); 395 396 const struct ad5686_chip_info ad5684_chip_info = { 397 .channels = ad5684r_channels, 398 .num_channels = 4, 399 .regmap_type = AD5686_REGMAP, 400 }; 401 EXPORT_SYMBOL_NS_GPL(ad5684_chip_info, "IIO_AD5686"); 402 403 const struct ad5686_chip_info ad5684r_chip_info = { 404 .channels = ad5684r_channels, 405 .int_vref_mv = 2500, 406 .num_channels = 4, 407 .regmap_type = AD5686_REGMAP, 408 }; 409 EXPORT_SYMBOL_NS_GPL(ad5684r_chip_info, "IIO_AD5686"); 410 411 const struct ad5686_chip_info ad5685r_chip_info = { 412 .channels = ad5685r_channels, 413 .int_vref_mv = 2500, 414 .num_channels = 4, 415 .regmap_type = AD5686_REGMAP, 416 }; 417 EXPORT_SYMBOL_NS_GPL(ad5685r_chip_info, "IIO_AD5686"); 418 419 const struct ad5686_chip_info ad5686_chip_info = { 420 .channels = ad5686r_channels, 421 .num_channels = 4, 422 .regmap_type = AD5686_REGMAP, 423 }; 424 EXPORT_SYMBOL_NS_GPL(ad5686_chip_info, "IIO_AD5686"); 425 426 const struct ad5686_chip_info ad5686r_chip_info = { 427 .channels = ad5686r_channels, 428 .int_vref_mv = 2500, 429 .num_channels = 4, 430 .regmap_type = AD5686_REGMAP, 431 }; 432 EXPORT_SYMBOL_NS_GPL(ad5686r_chip_info, "IIO_AD5686"); 433 434 const struct ad5686_chip_info ad5672r_chip_info = { 435 .channels = ad5672r_channels, 436 .int_vref_mv = 2500, 437 .num_channels = 8, 438 .regmap_type = AD5686_REGMAP, 439 }; 440 EXPORT_SYMBOL_NS_GPL(ad5672r_chip_info, "IIO_AD5686"); 441 442 const struct ad5686_chip_info ad5676_chip_info = { 443 .channels = ad5676r_channels, 444 .num_channels = 8, 445 .regmap_type = AD5686_REGMAP, 446 }; 447 EXPORT_SYMBOL_NS_GPL(ad5676_chip_info, "IIO_AD5686"); 448 449 const struct ad5686_chip_info ad5676r_chip_info = { 450 .channels = ad5676r_channels, 451 .int_vref_mv = 2500, 452 .num_channels = 8, 453 .regmap_type = AD5686_REGMAP, 454 }; 455 EXPORT_SYMBOL_NS_GPL(ad5676r_chip_info, "IIO_AD5686"); 456 457 const struct ad5686_chip_info ad5674r_chip_info = { 458 .channels = ad5674r_channels, 459 .int_vref_mv = 2500, 460 .num_channels = 16, 461 .regmap_type = AD5686_REGMAP, 462 }; 463 EXPORT_SYMBOL_NS_GPL(ad5674r_chip_info, "IIO_AD5686"); 464 465 const struct ad5686_chip_info ad5679r_chip_info = { 466 .channels = ad5679r_channels, 467 .int_vref_mv = 2500, 468 .num_channels = 16, 469 .regmap_type = AD5686_REGMAP, 470 }; 471 EXPORT_SYMBOL_NS_GPL(ad5679r_chip_info, "IIO_AD5686"); 472 473 int ad5686_probe(struct device *dev, 474 const struct ad5686_chip_info *chip_info, 475 const char *name, const struct ad5686_bus_ops *ops) 476 { 477 struct reset_control *rstc; 478 struct ad5686_state *st; 479 struct iio_dev *indio_dev; 480 int ret, i; 481 482 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 483 if (indio_dev == NULL) 484 return -ENOMEM; 485 486 st = iio_priv(indio_dev); 487 488 st->dev = dev; 489 st->ops = ops; 490 st->chip_info = chip_info; 491 492 rstc = devm_reset_control_get_optional_exclusive(dev, NULL); 493 if (IS_ERR(rstc)) 494 return dev_err_probe(dev, PTR_ERR(rstc), 495 "Failed to get reset control\n"); 496 497 ret = devm_regulator_get_enable(dev, "vdd"); 498 if (ret) 499 return dev_err_probe(dev, ret, "failed to enable vdd supply\n"); 500 501 ret = devm_regulator_get_enable(dev, "vlogic"); 502 if (ret) 503 return dev_err_probe(dev, ret, "failed to enable vlogic supply\n"); 504 505 ret = devm_regulator_get_enable_read_voltage(dev, "vref"); 506 if (ret == -ENODEV) /* vcc-supply is deprecated, but supported still */ 507 ret = devm_regulator_get_enable_read_voltage(dev, "vcc"); 508 if (ret < 0 && ret != -ENODEV) 509 return dev_err_probe(dev, ret, "failed to read vref voltage\n"); 510 511 st->use_internal_vref = ret == -ENODEV; 512 st->vref_mv = st->use_internal_vref ? st->chip_info->int_vref_mv : ret / 1000; 513 if (!st->vref_mv) 514 return dev_err_probe(dev, -EINVAL, 515 "invalid or not provided vref voltage\n"); 516 517 /* 4.5us power-up time: Datasheet Table 4: Timing Characteristics */ 518 fsleep(5); 519 520 /* 1us >> 30ns reset pulse activation time: Datasheet Table 4 */ 521 reset_control_assert(rstc); 522 fsleep(1); 523 reset_control_deassert(rstc); 524 525 st->ldac_gpio = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH); 526 if (IS_ERR(st->ldac_gpio)) 527 return dev_err_probe(dev, PTR_ERR(st->ldac_gpio), 528 "Failed to get LDAC GPIO\n"); 529 530 /* Initialize masks to all ones */ 531 st->pwr_down_mask = ~0; 532 st->pwr_down_mode = ~0; 533 534 /* Set all the power down mode for all channels to 1K pulldown */ 535 for (i = 0; i < st->chip_info->num_channels; i++) { 536 ad5686_pd_field_set(&st->chip_info->channels[i], 537 &st->pwr_down_mask, AD5686_PD_MSK_PWR_UP); 538 ad5686_pd_field_set(&st->chip_info->channels[i], 539 &st->pwr_down_mode, AD5686_PD_MODE_1K_TO_GND); 540 } 541 542 indio_dev->name = name; 543 indio_dev->info = &ad5686_info; 544 indio_dev->modes = INDIO_DIRECT_MODE; 545 indio_dev->channels = st->chip_info->channels; 546 indio_dev->num_channels = st->chip_info->num_channels; 547 548 ret = devm_mutex_init(dev, &st->lock); 549 if (ret) 550 return ret; 551 552 switch (st->chip_info->regmap_type) { 553 case AD5310_REGMAP: 554 ret = ad5310_control_sync(st); 555 if (ret) 556 return ret; 557 break; 558 case AD5683_REGMAP: 559 ret = ad5683_control_sync(st); 560 if (ret) 561 return ret; 562 break; 563 case AD5686_REGMAP: 564 ret = ad5686_write(st, AD5686_CMD_INTERNAL_REFER_SETUP, 0, 565 st->use_internal_vref ? 0 : AD5686_REF_BIT_MSK); 566 if (ret) 567 return ret; 568 break; 569 default: 570 return -EINVAL; 571 } 572 573 return devm_iio_device_register(dev, indio_dev); 574 } 575 EXPORT_SYMBOL_NS_GPL(ad5686_probe, "IIO_AD5686"); 576 577 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 578 MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC"); 579 MODULE_LICENSE("GPL v2"); 580