1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD3552R 4 * Digital to Analog converter driver 5 * 6 * Copyright 2021 Analog Devices Inc. 7 */ 8 #include <linux/unaligned.h> 9 #include <linux/bitfield.h> 10 #include <linux/device.h> 11 #include <linux/iio/triggered_buffer.h> 12 #include <linux/iio/trigger_consumer.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/spi/spi.h> 16 17 #include "ad3552r.h" 18 19 struct ad3552r_desc { 20 const struct ad3552r_model_data *model_data; 21 /* Used to look the spi bus for atomic operations where needed */ 22 struct mutex lock; 23 struct gpio_desc *gpio_reset; 24 struct gpio_desc *gpio_ldac; 25 struct spi_device *spi; 26 struct ad3552r_ch_data ch_data[AD3552R_MAX_CH]; 27 struct iio_chan_spec channels[AD3552R_MAX_CH + 1]; 28 unsigned long enabled_ch; 29 unsigned int num_ch; 30 }; 31 32 static u8 _ad3552r_reg_len(u8 addr) 33 { 34 switch (addr) { 35 case AD3552R_REG_ADDR_HW_LDAC_16B: 36 case AD3552R_REG_ADDR_CH_SELECT_16B: 37 case AD3552R_REG_ADDR_SW_LDAC_16B: 38 case AD3552R_REG_ADDR_HW_LDAC_24B: 39 case AD3552R_REG_ADDR_CH_SELECT_24B: 40 case AD3552R_REG_ADDR_SW_LDAC_24B: 41 return 1; 42 default: 43 break; 44 } 45 46 if (addr > AD3552R_REG_ADDR_HW_LDAC_24B) 47 return 3; 48 if (addr > AD3552R_REG_ADDR_HW_LDAC_16B) 49 return 2; 50 51 return 1; 52 } 53 54 /* SPI transfer to device */ 55 static int ad3552r_transfer(struct ad3552r_desc *dac, u8 addr, u32 len, 56 u8 *data, bool is_read) 57 { 58 /* Maximum transfer: Addr (1B) + 2 * (Data Reg (3B)) + SW LDAC(1B) */ 59 u8 buf[8]; 60 61 buf[0] = addr & AD3552R_ADDR_MASK; 62 buf[0] |= is_read ? AD3552R_READ_BIT : 0; 63 if (is_read) 64 return spi_write_then_read(dac->spi, buf, 1, data, len); 65 66 memcpy(buf + 1, data, len); 67 return spi_write_then_read(dac->spi, buf, len + 1, NULL, 0); 68 } 69 70 static int ad3552r_write_reg(struct ad3552r_desc *dac, u8 addr, u16 val) 71 { 72 u8 reg_len; 73 u8 buf[AD3552R_MAX_REG_SIZE] = { 0 }; 74 75 reg_len = _ad3552r_reg_len(addr); 76 if (reg_len == 2) 77 /* Only DAC register are 2 bytes wide */ 78 val &= AD3552R_MASK_DAC_12B; 79 if (reg_len == 1) 80 buf[0] = val & 0xFF; 81 else 82 /* reg_len can be 2 or 3, but 3rd bytes needs to be set to 0 */ 83 put_unaligned_be16(val, buf); 84 85 return ad3552r_transfer(dac, addr, reg_len, buf, false); 86 } 87 88 static int ad3552r_read_reg(struct ad3552r_desc *dac, u8 addr, u16 *val) 89 { 90 int err; 91 u8 reg_len, buf[AD3552R_MAX_REG_SIZE] = { 0 }; 92 93 reg_len = _ad3552r_reg_len(addr); 94 err = ad3552r_transfer(dac, addr, reg_len, buf, true); 95 if (err) 96 return err; 97 98 if (reg_len == 1) 99 *val = buf[0]; 100 else 101 /* reg_len can be 2 or 3, but only first 2 bytes are relevant */ 102 *val = get_unaligned_be16(buf); 103 104 return 0; 105 } 106 107 /* Update field of a register, shift val if needed */ 108 static int ad3552r_update_reg_field(struct ad3552r_desc *dac, u8 addr, u16 mask, 109 u16 val) 110 { 111 int ret; 112 u16 reg; 113 114 ret = ad3552r_read_reg(dac, addr, ®); 115 if (ret < 0) 116 return ret; 117 118 reg &= ~mask; 119 reg |= val; 120 121 return ad3552r_write_reg(dac, addr, reg); 122 } 123 124 #define AD3552R_CH_DAC(_idx) ((struct iio_chan_spec) { \ 125 .type = IIO_VOLTAGE, \ 126 .output = true, \ 127 .indexed = true, \ 128 .channel = _idx, \ 129 .scan_index = _idx, \ 130 .scan_type = { \ 131 .sign = 'u', \ 132 .realbits = 16, \ 133 .storagebits = 16, \ 134 .endianness = IIO_BE, \ 135 }, \ 136 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 137 BIT(IIO_CHAN_INFO_SCALE) | \ 138 BIT(IIO_CHAN_INFO_ENABLE) | \ 139 BIT(IIO_CHAN_INFO_OFFSET), \ 140 }) 141 142 static int ad3552r_read_raw(struct iio_dev *indio_dev, 143 struct iio_chan_spec const *chan, 144 int *val, 145 int *val2, 146 long mask) 147 { 148 struct ad3552r_desc *dac = iio_priv(indio_dev); 149 u16 tmp_val; 150 int err; 151 u8 ch = chan->channel; 152 153 switch (mask) { 154 case IIO_CHAN_INFO_RAW: 155 mutex_lock(&dac->lock); 156 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_CH_DAC_24B(ch), 157 &tmp_val); 158 mutex_unlock(&dac->lock); 159 if (err < 0) 160 return err; 161 *val = tmp_val; 162 return IIO_VAL_INT; 163 case IIO_CHAN_INFO_ENABLE: 164 mutex_lock(&dac->lock); 165 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG, 166 &tmp_val); 167 mutex_unlock(&dac->lock); 168 if (err < 0) 169 return err; 170 *val = !((tmp_val & AD3552R_MASK_CH_DAC_POWERDOWN(ch)) >> 171 __ffs(AD3552R_MASK_CH_DAC_POWERDOWN(ch))); 172 return IIO_VAL_INT; 173 case IIO_CHAN_INFO_SCALE: 174 *val = dac->ch_data[ch].scale_int; 175 *val2 = dac->ch_data[ch].scale_dec; 176 return IIO_VAL_INT_PLUS_MICRO; 177 case IIO_CHAN_INFO_OFFSET: 178 *val = dac->ch_data[ch].offset_int; 179 *val2 = dac->ch_data[ch].offset_dec; 180 return IIO_VAL_INT_PLUS_MICRO; 181 default: 182 return -EINVAL; 183 } 184 } 185 186 static int ad3552r_write_raw(struct iio_dev *indio_dev, 187 struct iio_chan_spec const *chan, 188 int val, 189 int val2, 190 long mask) 191 { 192 struct ad3552r_desc *dac = iio_priv(indio_dev); 193 int err; 194 195 mutex_lock(&dac->lock); 196 switch (mask) { 197 case IIO_CHAN_INFO_RAW: 198 err = ad3552r_write_reg(dac, 199 AD3552R_REG_ADDR_CH_DAC_24B(chan->channel), 200 val); 201 break; 202 case IIO_CHAN_INFO_ENABLE: 203 if (chan->channel == 0) 204 val = FIELD_PREP(AD3552R_MASK_CH_DAC_POWERDOWN(0), !val); 205 else 206 val = FIELD_PREP(AD3552R_MASK_CH_DAC_POWERDOWN(1), !val); 207 208 err = ad3552r_update_reg_field(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG, 209 AD3552R_MASK_CH_DAC_POWERDOWN(chan->channel), 210 val); 211 break; 212 default: 213 err = -EINVAL; 214 break; 215 } 216 mutex_unlock(&dac->lock); 217 218 return err; 219 } 220 221 static const struct iio_info ad3552r_iio_info = { 222 .read_raw = ad3552r_read_raw, 223 .write_raw = ad3552r_write_raw 224 }; 225 226 static int32_t ad3552r_trigger_hw_ldac(struct gpio_desc *ldac) 227 { 228 gpiod_set_value_cansleep(ldac, 0); 229 usleep_range(AD3552R_LDAC_PULSE_US, AD3552R_LDAC_PULSE_US + 10); 230 gpiod_set_value_cansleep(ldac, 1); 231 232 return 0; 233 } 234 235 static int ad3552r_write_all_channels(struct ad3552r_desc *dac, u8 *data) 236 { 237 int err, len; 238 u8 addr, buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE + 1]; 239 240 addr = AD3552R_REG_ADDR_CH_INPUT_24B(1); 241 /* CH1 */ 242 memcpy(buff, data + 2, 2); 243 buff[2] = 0; 244 /* CH0 */ 245 memcpy(buff + 3, data, 2); 246 buff[5] = 0; 247 len = 6; 248 if (!dac->gpio_ldac) { 249 /* Software LDAC */ 250 buff[6] = AD3552R_MASK_ALL_CH; 251 ++len; 252 } 253 err = ad3552r_transfer(dac, addr, len, buff, false); 254 if (err) 255 return err; 256 257 if (dac->gpio_ldac) 258 return ad3552r_trigger_hw_ldac(dac->gpio_ldac); 259 260 return 0; 261 } 262 263 static int ad3552r_write_codes(struct ad3552r_desc *dac, u32 mask, u8 *data) 264 { 265 int err; 266 u8 addr, buff[AD3552R_MAX_REG_SIZE]; 267 268 if (mask == AD3552R_MASK_ALL_CH) { 269 if (memcmp(data, data + 2, 2) != 0) 270 return ad3552r_write_all_channels(dac, data); 271 272 addr = AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B; 273 } else { 274 addr = AD3552R_REG_ADDR_CH_INPUT_24B(__ffs(mask)); 275 } 276 277 memcpy(buff, data, 2); 278 buff[2] = 0; 279 err = ad3552r_transfer(dac, addr, 3, data, false); 280 if (err) 281 return err; 282 283 if (dac->gpio_ldac) 284 return ad3552r_trigger_hw_ldac(dac->gpio_ldac); 285 286 return ad3552r_write_reg(dac, AD3552R_REG_ADDR_SW_LDAC_24B, mask); 287 } 288 289 static irqreturn_t ad3552r_trigger_handler(int irq, void *p) 290 { 291 struct iio_poll_func *pf = p; 292 struct iio_dev *indio_dev = pf->indio_dev; 293 struct iio_buffer *buf = indio_dev->buffer; 294 struct ad3552r_desc *dac = iio_priv(indio_dev); 295 /* Maximum size of a scan */ 296 u8 buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE]; 297 int err; 298 299 memset(buff, 0, sizeof(buff)); 300 err = iio_pop_from_buffer(buf, buff); 301 if (err) 302 goto end; 303 304 mutex_lock(&dac->lock); 305 ad3552r_write_codes(dac, *indio_dev->active_scan_mask, buff); 306 mutex_unlock(&dac->lock); 307 end: 308 iio_trigger_notify_done(indio_dev->trig); 309 310 return IRQ_HANDLED; 311 } 312 313 static int ad3552r_check_scratch_pad(struct ad3552r_desc *dac) 314 { 315 const u16 val1 = AD3552R_SCRATCH_PAD_TEST_VAL1; 316 const u16 val2 = AD3552R_SCRATCH_PAD_TEST_VAL2; 317 u16 val; 318 int err; 319 320 err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val1); 321 if (err < 0) 322 return err; 323 324 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val); 325 if (err < 0) 326 return err; 327 328 if (val1 != val) 329 return -ENODEV; 330 331 err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val2); 332 if (err < 0) 333 return err; 334 335 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val); 336 if (err < 0) 337 return err; 338 339 if (val2 != val) 340 return -ENODEV; 341 342 return 0; 343 } 344 345 struct reg_addr_pool { 346 struct ad3552r_desc *dac; 347 u8 addr; 348 }; 349 350 static int ad3552r_read_reg_wrapper(struct reg_addr_pool *addr) 351 { 352 int err; 353 u16 val; 354 355 err = ad3552r_read_reg(addr->dac, addr->addr, &val); 356 if (err) 357 return err; 358 359 return val; 360 } 361 362 static int ad3552r_reset(struct ad3552r_desc *dac) 363 { 364 struct reg_addr_pool addr; 365 int ret; 366 int val; 367 368 dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset", 369 GPIOD_OUT_LOW); 370 if (IS_ERR(dac->gpio_reset)) 371 return dev_err_probe(&dac->spi->dev, PTR_ERR(dac->gpio_reset), 372 "Error while getting gpio reset"); 373 374 if (dac->gpio_reset) { 375 /* Perform hardware reset */ 376 usleep_range(10, 20); 377 gpiod_set_value_cansleep(dac->gpio_reset, 1); 378 } else { 379 /* Perform software reset if no GPIO provided */ 380 ret = ad3552r_update_reg_field(dac, 381 AD3552R_REG_ADDR_INTERFACE_CONFIG_A, 382 AD3552R_MASK_SOFTWARE_RESET, 383 AD3552R_MASK_SOFTWARE_RESET); 384 if (ret < 0) 385 return ret; 386 387 } 388 389 addr.dac = dac; 390 addr.addr = AD3552R_REG_ADDR_INTERFACE_CONFIG_B; 391 ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val, 392 val == AD3552R_DEFAULT_CONFIG_B_VALUE || 393 val < 0, 394 5000, 50000); 395 if (val < 0) 396 ret = val; 397 if (ret) { 398 dev_err(&dac->spi->dev, "Error while resetting"); 399 return ret; 400 } 401 402 ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val, 403 !(val & AD3552R_MASK_INTERFACE_NOT_READY) || 404 val < 0, 405 5000, 50000); 406 if (val < 0) 407 ret = val; 408 if (ret) { 409 dev_err(&dac->spi->dev, "Error while resetting"); 410 return ret; 411 } 412 413 /* Clear reset error flag, see ad3552r manual, rev B table 38. */ 414 ret = ad3552r_write_reg(dac, AD3552R_REG_ADDR_ERR_STATUS, 415 AD3552R_MASK_RESET_STATUS); 416 if (ret) 417 return ret; 418 419 return ad3552r_update_reg_field(dac, 420 AD3552R_REG_ADDR_INTERFACE_CONFIG_A, 421 AD3552R_MASK_ADDR_ASCENSION, 422 FIELD_PREP(AD3552R_MASK_ADDR_ASCENSION, val)); 423 } 424 425 static int ad3552r_configure_custom_gain(struct ad3552r_desc *dac, 426 struct fwnode_handle *child, 427 u32 ch) 428 { 429 struct device *dev = &dac->spi->dev; 430 int err; 431 u8 addr; 432 u16 reg; 433 434 err = ad3552r_get_custom_gain(dev, child, 435 &dac->ch_data[ch].p, 436 &dac->ch_data[ch].n, 437 &dac->ch_data[ch].rfb, 438 &dac->ch_data[ch].gain_offset); 439 if (err) 440 return err; 441 442 dac->ch_data[ch].range_override = 1; 443 444 addr = AD3552R_REG_ADDR_CH_GAIN(ch); 445 err = ad3552r_write_reg(dac, addr, 446 abs((s32)dac->ch_data[ch].gain_offset) & 447 AD3552R_MASK_CH_OFFSET_BITS_0_7); 448 if (err) 449 return dev_err_probe(dev, err, "Error writing register\n"); 450 451 reg = ad3552r_calc_custom_gain(dac->ch_data[ch].p, dac->ch_data[ch].n, 452 dac->ch_data[ch].gain_offset); 453 454 err = ad3552r_write_reg(dac, addr, reg); 455 if (err) 456 return dev_err_probe(dev, err, "Error writing register\n"); 457 458 return 0; 459 } 460 461 static int ad3552r_configure_device(struct ad3552r_desc *dac) 462 { 463 struct device *dev = &dac->spi->dev; 464 int err, cnt = 0; 465 u32 val, ch; 466 467 dac->gpio_ldac = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH); 468 if (IS_ERR(dac->gpio_ldac)) 469 return dev_err_probe(dev, PTR_ERR(dac->gpio_ldac), 470 "Error getting gpio ldac"); 471 472 err = ad3552r_get_ref_voltage(dev, &val); 473 if (err < 0) 474 return err; 475 476 err = ad3552r_update_reg_field(dac, 477 AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, 478 AD3552R_MASK_REFERENCE_VOLTAGE_SEL, 479 FIELD_PREP(AD3552R_MASK_REFERENCE_VOLTAGE_SEL, val)); 480 if (err) 481 return err; 482 483 err = ad3552r_get_drive_strength(dev, &val); 484 if (!err) { 485 err = ad3552r_update_reg_field(dac, 486 AD3552R_REG_ADDR_INTERFACE_CONFIG_D, 487 AD3552R_MASK_SDO_DRIVE_STRENGTH, 488 FIELD_PREP(AD3552R_MASK_SDO_DRIVE_STRENGTH, val)); 489 if (err) 490 return err; 491 } 492 493 dac->num_ch = device_get_child_node_count(dev); 494 if (!dac->num_ch) { 495 dev_err(dev, "No channels defined\n"); 496 return -ENODEV; 497 } 498 499 device_for_each_child_node_scoped(dev, child) { 500 err = fwnode_property_read_u32(child, "reg", &ch); 501 if (err) 502 return dev_err_probe(dev, err, 503 "mandatory reg property missing\n"); 504 if (ch >= dac->model_data->num_hw_channels) 505 return dev_err_probe(dev, -EINVAL, 506 "reg must be less than %d\n", 507 dac->model_data->num_hw_channels); 508 509 err = ad3552r_get_output_range(dev, dac->model_data, 510 child, &val); 511 if (err && err != -ENOENT) 512 return err; 513 514 if (!err) { 515 if (ch == 0) 516 val = FIELD_PREP(AD3552R_MASK_CH_OUTPUT_RANGE_SEL(0), val); 517 else 518 val = FIELD_PREP(AD3552R_MASK_CH_OUTPUT_RANGE_SEL(1), val); 519 520 err = ad3552r_update_reg_field(dac, 521 AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE, 522 AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch), 523 val); 524 if (err) 525 return err; 526 527 dac->ch_data[ch].range = val; 528 } else if (dac->model_data->requires_output_range) { 529 return dev_err_probe(dev, -EINVAL, 530 "adi,output-range-microvolt is required for %s\n", 531 dac->model_data->model_name); 532 } else { 533 err = ad3552r_configure_custom_gain(dac, child, ch); 534 if (err) 535 return err; 536 } 537 538 ad3552r_calc_gain_and_offset(&dac->ch_data[ch], dac->model_data); 539 dac->enabled_ch |= BIT(ch); 540 541 if (ch == 0) 542 val = FIELD_PREP(AD3552R_MASK_CH(0), 1); 543 else 544 val = FIELD_PREP(AD3552R_MASK_CH(1), 1); 545 546 err = ad3552r_update_reg_field(dac, 547 AD3552R_REG_ADDR_CH_SELECT_16B, 548 AD3552R_MASK_CH(ch), val); 549 if (err < 0) 550 return err; 551 552 dac->channels[cnt] = AD3552R_CH_DAC(ch); 553 ++cnt; 554 555 } 556 557 /* Disable unused channels */ 558 for_each_clear_bit(ch, &dac->enabled_ch, 559 dac->model_data->num_hw_channels) { 560 if (ch == 0) 561 val = FIELD_PREP(AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(0), 1); 562 else 563 val = FIELD_PREP(AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(1), 1); 564 565 err = ad3552r_update_reg_field(dac, 566 AD3552R_REG_ADDR_POWERDOWN_CONFIG, 567 AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch), 568 val); 569 if (err) 570 return err; 571 } 572 573 dac->num_ch = cnt; 574 575 return 0; 576 } 577 578 static int ad3552r_init(struct ad3552r_desc *dac) 579 { 580 int err; 581 u16 val, id; 582 583 err = ad3552r_reset(dac); 584 if (err) { 585 dev_err(&dac->spi->dev, "Reset failed\n"); 586 return err; 587 } 588 589 err = ad3552r_check_scratch_pad(dac); 590 if (err) { 591 dev_err(&dac->spi->dev, "Scratch pad test failed\n"); 592 return err; 593 } 594 595 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_L, &val); 596 if (err) { 597 dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_L\n"); 598 return err; 599 } 600 601 id = val; 602 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_H, &val); 603 if (err) { 604 dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_H\n"); 605 return err; 606 } 607 608 id |= val << 8; 609 if (id != dac->model_data->chip_id) { 610 dev_err(&dac->spi->dev, "Product id not matching\n"); 611 return -ENODEV; 612 } 613 614 return ad3552r_configure_device(dac); 615 } 616 617 static int ad3552r_probe(struct spi_device *spi) 618 { 619 struct ad3552r_desc *dac; 620 struct iio_dev *indio_dev; 621 int err; 622 623 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*dac)); 624 if (!indio_dev) 625 return -ENOMEM; 626 627 dac = iio_priv(indio_dev); 628 dac->spi = spi; 629 dac->model_data = spi_get_device_match_data(spi); 630 if (!dac->model_data) 631 return -EINVAL; 632 633 mutex_init(&dac->lock); 634 635 err = ad3552r_init(dac); 636 if (err) 637 return err; 638 639 /* Config triggered buffer device */ 640 indio_dev->name = dac->model_data->model_name; 641 indio_dev->dev.parent = &spi->dev; 642 indio_dev->info = &ad3552r_iio_info; 643 indio_dev->num_channels = dac->num_ch; 644 indio_dev->channels = dac->channels; 645 indio_dev->modes = INDIO_DIRECT_MODE; 646 647 err = devm_iio_triggered_buffer_setup_ext(&indio_dev->dev, indio_dev, NULL, 648 &ad3552r_trigger_handler, 649 IIO_BUFFER_DIRECTION_OUT, 650 NULL, 651 NULL); 652 if (err) 653 return err; 654 655 return devm_iio_device_register(&spi->dev, indio_dev); 656 } 657 658 static const struct spi_device_id ad3552r_id[] = { 659 { 660 .name = "ad3541r", 661 .driver_data = (kernel_ulong_t)&ad3541r_model_data 662 }, 663 { 664 .name = "ad3542r", 665 .driver_data = (kernel_ulong_t)&ad3542r_model_data 666 }, 667 { 668 .name = "ad3551r", 669 .driver_data = (kernel_ulong_t)&ad3551r_model_data 670 }, 671 { 672 .name = "ad3552r", 673 .driver_data = (kernel_ulong_t)&ad3552r_model_data 674 }, 675 { } 676 }; 677 MODULE_DEVICE_TABLE(spi, ad3552r_id); 678 679 static const struct of_device_id ad3552r_of_match[] = { 680 { .compatible = "adi,ad3541r", .data = &ad3541r_model_data }, 681 { .compatible = "adi,ad3542r", .data = &ad3542r_model_data }, 682 { .compatible = "adi,ad3551r", .data = &ad3551r_model_data }, 683 { .compatible = "adi,ad3552r", .data = &ad3552r_model_data }, 684 { } 685 }; 686 MODULE_DEVICE_TABLE(of, ad3552r_of_match); 687 688 static struct spi_driver ad3552r_driver = { 689 .driver = { 690 .name = "ad3552r", 691 .of_match_table = ad3552r_of_match, 692 }, 693 .probe = ad3552r_probe, 694 .id_table = ad3552r_id 695 }; 696 module_spi_driver(ad3552r_driver); 697 698 MODULE_AUTHOR("Mihail Chindris <mihail.chindris@analog.com>"); 699 MODULE_DESCRIPTION("Analog Device AD3552R DAC"); 700 MODULE_LICENSE("GPL v2"); 701 MODULE_IMPORT_NS("IIO_AD3552R"); 702