1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices AD3552R
4 * Digital to Analog converter driver
5 *
6 * Copyright 2021 Analog Devices Inc.
7 */
8 #include <linux/unaligned.h>
9 #include <linux/bitfield.h>
10 #include <linux/device.h>
11 #include <linux/iio/triggered_buffer.h>
12 #include <linux/iio/trigger_consumer.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/spi/spi.h>
16
17 #include "ad3552r.h"
18
19 struct ad3552r_desc {
20 const struct ad3552r_model_data *model_data;
21 /* Used to look the spi bus for atomic operations where needed */
22 struct mutex lock;
23 struct gpio_desc *gpio_reset;
24 struct gpio_desc *gpio_ldac;
25 struct spi_device *spi;
26 struct ad3552r_ch_data ch_data[AD3552R_MAX_CH];
27 struct iio_chan_spec channels[AD3552R_MAX_CH + 1];
28 unsigned long enabled_ch;
29 unsigned int num_ch;
30 };
31
_ad3552r_reg_len(u8 addr)32 static u8 _ad3552r_reg_len(u8 addr)
33 {
34 switch (addr) {
35 case AD3552R_REG_ADDR_HW_LDAC_16B:
36 case AD3552R_REG_ADDR_CH_SELECT_16B:
37 case AD3552R_REG_ADDR_SW_LDAC_16B:
38 case AD3552R_REG_ADDR_HW_LDAC_24B:
39 case AD3552R_REG_ADDR_CH_SELECT_24B:
40 case AD3552R_REG_ADDR_SW_LDAC_24B:
41 return 1;
42 default:
43 break;
44 }
45
46 if (addr > AD3552R_REG_ADDR_HW_LDAC_24B)
47 return 3;
48 if (addr > AD3552R_REG_ADDR_HW_LDAC_16B)
49 return 2;
50
51 return 1;
52 }
53
54 /* SPI transfer to device */
ad3552r_transfer(struct ad3552r_desc * dac,u8 addr,u32 len,u8 * data,bool is_read)55 static int ad3552r_transfer(struct ad3552r_desc *dac, u8 addr, u32 len,
56 u8 *data, bool is_read)
57 {
58 /* Maximum transfer: Addr (1B) + 2 * (Data Reg (3B)) + SW LDAC(1B) */
59 u8 buf[8];
60
61 buf[0] = addr & AD3552R_ADDR_MASK;
62 buf[0] |= is_read ? AD3552R_READ_BIT : 0;
63 if (is_read)
64 return spi_write_then_read(dac->spi, buf, 1, data, len);
65
66 memcpy(buf + 1, data, len);
67 return spi_write_then_read(dac->spi, buf, len + 1, NULL, 0);
68 }
69
ad3552r_write_reg(struct ad3552r_desc * dac,u8 addr,u16 val)70 static int ad3552r_write_reg(struct ad3552r_desc *dac, u8 addr, u16 val)
71 {
72 u8 reg_len;
73 u8 buf[AD3552R_MAX_REG_SIZE] = { 0 };
74
75 reg_len = _ad3552r_reg_len(addr);
76 if (reg_len == 2)
77 /* Only DAC register are 2 bytes wide */
78 val &= AD3552R_MASK_DAC_12B;
79 if (reg_len == 1)
80 buf[0] = val & 0xFF;
81 else
82 /* reg_len can be 2 or 3, but 3rd bytes needs to be set to 0 */
83 put_unaligned_be16(val, buf);
84
85 return ad3552r_transfer(dac, addr, reg_len, buf, false);
86 }
87
ad3552r_read_reg(struct ad3552r_desc * dac,u8 addr,u16 * val)88 static int ad3552r_read_reg(struct ad3552r_desc *dac, u8 addr, u16 *val)
89 {
90 int err;
91 u8 reg_len, buf[AD3552R_MAX_REG_SIZE] = { 0 };
92
93 reg_len = _ad3552r_reg_len(addr);
94 err = ad3552r_transfer(dac, addr, reg_len, buf, true);
95 if (err)
96 return err;
97
98 if (reg_len == 1)
99 *val = buf[0];
100 else
101 /* reg_len can be 2 or 3, but only first 2 bytes are relevant */
102 *val = get_unaligned_be16(buf);
103
104 return 0;
105 }
106
107 /* Update field of a register, shift val if needed */
ad3552r_update_reg_field(struct ad3552r_desc * dac,u8 addr,u16 mask,u16 val)108 static int ad3552r_update_reg_field(struct ad3552r_desc *dac, u8 addr, u16 mask,
109 u16 val)
110 {
111 int ret;
112 u16 reg;
113
114 ret = ad3552r_read_reg(dac, addr, ®);
115 if (ret < 0)
116 return ret;
117
118 reg &= ~mask;
119 reg |= val;
120
121 return ad3552r_write_reg(dac, addr, reg);
122 }
123
124 #define AD3552R_CH_DAC(_idx) ((struct iio_chan_spec) { \
125 .type = IIO_VOLTAGE, \
126 .output = true, \
127 .indexed = true, \
128 .channel = _idx, \
129 .scan_index = _idx, \
130 .scan_type = { \
131 .sign = 'u', \
132 .realbits = 16, \
133 .storagebits = 16, \
134 .endianness = IIO_BE, \
135 }, \
136 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
137 BIT(IIO_CHAN_INFO_SCALE) | \
138 BIT(IIO_CHAN_INFO_ENABLE) | \
139 BIT(IIO_CHAN_INFO_OFFSET), \
140 })
141
ad3552r_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)142 static int ad3552r_read_raw(struct iio_dev *indio_dev,
143 struct iio_chan_spec const *chan,
144 int *val,
145 int *val2,
146 long mask)
147 {
148 struct ad3552r_desc *dac = iio_priv(indio_dev);
149 u16 tmp_val;
150 int err;
151 u8 ch = chan->channel;
152
153 switch (mask) {
154 case IIO_CHAN_INFO_RAW:
155 mutex_lock(&dac->lock);
156 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_CH_DAC_24B(ch),
157 &tmp_val);
158 mutex_unlock(&dac->lock);
159 if (err < 0)
160 return err;
161 *val = tmp_val;
162 return IIO_VAL_INT;
163 case IIO_CHAN_INFO_ENABLE:
164 mutex_lock(&dac->lock);
165 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG,
166 &tmp_val);
167 mutex_unlock(&dac->lock);
168 if (err < 0)
169 return err;
170 *val = !((tmp_val & AD3552R_MASK_CH_DAC_POWERDOWN(ch)) >>
171 __ffs(AD3552R_MASK_CH_DAC_POWERDOWN(ch)));
172 return IIO_VAL_INT;
173 case IIO_CHAN_INFO_SCALE:
174 *val = dac->ch_data[ch].scale_int;
175 *val2 = dac->ch_data[ch].scale_dec;
176 return IIO_VAL_INT_PLUS_MICRO;
177 case IIO_CHAN_INFO_OFFSET:
178 *val = dac->ch_data[ch].offset_int;
179 *val2 = dac->ch_data[ch].offset_dec;
180 return IIO_VAL_INT_PLUS_MICRO;
181 default:
182 return -EINVAL;
183 }
184 }
185
ad3552r_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)186 static int ad3552r_write_raw(struct iio_dev *indio_dev,
187 struct iio_chan_spec const *chan,
188 int val,
189 int val2,
190 long mask)
191 {
192 struct ad3552r_desc *dac = iio_priv(indio_dev);
193 int err;
194
195 mutex_lock(&dac->lock);
196 switch (mask) {
197 case IIO_CHAN_INFO_RAW:
198 err = ad3552r_write_reg(dac,
199 AD3552R_REG_ADDR_CH_DAC_24B(chan->channel),
200 val);
201 break;
202 case IIO_CHAN_INFO_ENABLE:
203 if (chan->channel == 0)
204 val = FIELD_PREP(AD3552R_MASK_CH_DAC_POWERDOWN(0), !val);
205 else
206 val = FIELD_PREP(AD3552R_MASK_CH_DAC_POWERDOWN(1), !val);
207
208 err = ad3552r_update_reg_field(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG,
209 AD3552R_MASK_CH_DAC_POWERDOWN(chan->channel),
210 val);
211 break;
212 default:
213 err = -EINVAL;
214 break;
215 }
216 mutex_unlock(&dac->lock);
217
218 return err;
219 }
220
221 static const struct iio_info ad3552r_iio_info = {
222 .read_raw = ad3552r_read_raw,
223 .write_raw = ad3552r_write_raw
224 };
225
ad3552r_trigger_hw_ldac(struct gpio_desc * ldac)226 static int32_t ad3552r_trigger_hw_ldac(struct gpio_desc *ldac)
227 {
228 gpiod_set_value_cansleep(ldac, 0);
229 usleep_range(AD3552R_LDAC_PULSE_US, AD3552R_LDAC_PULSE_US + 10);
230 gpiod_set_value_cansleep(ldac, 1);
231
232 return 0;
233 }
234
ad3552r_write_all_channels(struct ad3552r_desc * dac,u8 * data)235 static int ad3552r_write_all_channels(struct ad3552r_desc *dac, u8 *data)
236 {
237 int err, len;
238 u8 addr, buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE + 1];
239
240 addr = AD3552R_REG_ADDR_CH_INPUT_24B(1);
241 /* CH1 */
242 memcpy(buff, data + 2, 2);
243 buff[2] = 0;
244 /* CH0 */
245 memcpy(buff + 3, data, 2);
246 buff[5] = 0;
247 len = 6;
248 if (!dac->gpio_ldac) {
249 /* Software LDAC */
250 buff[6] = AD3552R_MASK_ALL_CH;
251 ++len;
252 }
253 err = ad3552r_transfer(dac, addr, len, buff, false);
254 if (err)
255 return err;
256
257 if (dac->gpio_ldac)
258 return ad3552r_trigger_hw_ldac(dac->gpio_ldac);
259
260 return 0;
261 }
262
ad3552r_write_codes(struct ad3552r_desc * dac,u32 mask,u8 * data)263 static int ad3552r_write_codes(struct ad3552r_desc *dac, u32 mask, u8 *data)
264 {
265 int err;
266 u8 addr, buff[AD3552R_MAX_REG_SIZE];
267
268 if (mask == AD3552R_MASK_ALL_CH) {
269 if (memcmp(data, data + 2, 2) != 0)
270 return ad3552r_write_all_channels(dac, data);
271
272 addr = AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B;
273 } else {
274 addr = AD3552R_REG_ADDR_CH_INPUT_24B(__ffs(mask));
275 }
276
277 memcpy(buff, data, 2);
278 buff[2] = 0;
279 err = ad3552r_transfer(dac, addr, 3, data, false);
280 if (err)
281 return err;
282
283 if (dac->gpio_ldac)
284 return ad3552r_trigger_hw_ldac(dac->gpio_ldac);
285
286 return ad3552r_write_reg(dac, AD3552R_REG_ADDR_SW_LDAC_24B, mask);
287 }
288
ad3552r_trigger_handler(int irq,void * p)289 static irqreturn_t ad3552r_trigger_handler(int irq, void *p)
290 {
291 struct iio_poll_func *pf = p;
292 struct iio_dev *indio_dev = pf->indio_dev;
293 struct iio_buffer *buf = indio_dev->buffer;
294 struct ad3552r_desc *dac = iio_priv(indio_dev);
295 /* Maximum size of a scan */
296 u8 buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE];
297 int err;
298
299 memset(buff, 0, sizeof(buff));
300 err = iio_pop_from_buffer(buf, buff);
301 if (err)
302 goto end;
303
304 mutex_lock(&dac->lock);
305 ad3552r_write_codes(dac, *indio_dev->active_scan_mask, buff);
306 mutex_unlock(&dac->lock);
307 end:
308 iio_trigger_notify_done(indio_dev->trig);
309
310 return IRQ_HANDLED;
311 }
312
ad3552r_check_scratch_pad(struct ad3552r_desc * dac)313 static int ad3552r_check_scratch_pad(struct ad3552r_desc *dac)
314 {
315 const u16 val1 = AD3552R_SCRATCH_PAD_TEST_VAL1;
316 const u16 val2 = AD3552R_SCRATCH_PAD_TEST_VAL2;
317 u16 val;
318 int err;
319
320 err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val1);
321 if (err < 0)
322 return err;
323
324 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);
325 if (err < 0)
326 return err;
327
328 if (val1 != val)
329 return -ENODEV;
330
331 err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val2);
332 if (err < 0)
333 return err;
334
335 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);
336 if (err < 0)
337 return err;
338
339 if (val2 != val)
340 return -ENODEV;
341
342 return 0;
343 }
344
345 struct reg_addr_pool {
346 struct ad3552r_desc *dac;
347 u8 addr;
348 };
349
ad3552r_read_reg_wrapper(struct reg_addr_pool * addr)350 static int ad3552r_read_reg_wrapper(struct reg_addr_pool *addr)
351 {
352 int err;
353 u16 val;
354
355 err = ad3552r_read_reg(addr->dac, addr->addr, &val);
356 if (err)
357 return err;
358
359 return val;
360 }
361
ad3552r_reset(struct ad3552r_desc * dac)362 static int ad3552r_reset(struct ad3552r_desc *dac)
363 {
364 struct reg_addr_pool addr;
365 int ret;
366 int val;
367
368 dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset",
369 GPIOD_OUT_LOW);
370 if (IS_ERR(dac->gpio_reset))
371 return dev_err_probe(&dac->spi->dev, PTR_ERR(dac->gpio_reset),
372 "Error while getting gpio reset");
373
374 if (dac->gpio_reset) {
375 /* Perform hardware reset */
376 usleep_range(10, 20);
377 gpiod_set_value_cansleep(dac->gpio_reset, 1);
378 } else {
379 /* Perform software reset if no GPIO provided */
380 ret = ad3552r_update_reg_field(dac,
381 AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
382 AD3552R_MASK_SOFTWARE_RESET,
383 AD3552R_MASK_SOFTWARE_RESET);
384 if (ret < 0)
385 return ret;
386
387 }
388
389 addr.dac = dac;
390 addr.addr = AD3552R_REG_ADDR_INTERFACE_CONFIG_B;
391 ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
392 val == AD3552R_DEFAULT_CONFIG_B_VALUE ||
393 val < 0,
394 5000, 50000);
395 if (val < 0)
396 ret = val;
397 if (ret) {
398 dev_err(&dac->spi->dev, "Error while resetting");
399 return ret;
400 }
401
402 ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
403 !(val & AD3552R_MASK_INTERFACE_NOT_READY) ||
404 val < 0,
405 5000, 50000);
406 if (val < 0)
407 ret = val;
408 if (ret) {
409 dev_err(&dac->spi->dev, "Error while resetting");
410 return ret;
411 }
412
413 return ad3552r_update_reg_field(dac,
414 AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
415 AD3552R_MASK_ADDR_ASCENSION,
416 FIELD_PREP(AD3552R_MASK_ADDR_ASCENSION, val));
417 }
418
ad3552r_configure_custom_gain(struct ad3552r_desc * dac,struct fwnode_handle * child,u32 ch)419 static int ad3552r_configure_custom_gain(struct ad3552r_desc *dac,
420 struct fwnode_handle *child,
421 u32 ch)
422 {
423 struct device *dev = &dac->spi->dev;
424 int err;
425 u8 addr;
426 u16 reg;
427
428 err = ad3552r_get_custom_gain(dev, child,
429 &dac->ch_data[ch].p,
430 &dac->ch_data[ch].n,
431 &dac->ch_data[ch].rfb,
432 &dac->ch_data[ch].gain_offset);
433 if (err)
434 return err;
435
436 dac->ch_data[ch].range_override = 1;
437
438 addr = AD3552R_REG_ADDR_CH_GAIN(ch);
439 err = ad3552r_write_reg(dac, addr,
440 abs((s32)dac->ch_data[ch].gain_offset) &
441 AD3552R_MASK_CH_OFFSET_BITS_0_7);
442 if (err)
443 return dev_err_probe(dev, err, "Error writing register\n");
444
445 reg = ad3552r_calc_custom_gain(dac->ch_data[ch].p, dac->ch_data[ch].n,
446 dac->ch_data[ch].gain_offset);
447
448 err = ad3552r_write_reg(dac, addr, reg);
449 if (err)
450 return dev_err_probe(dev, err, "Error writing register\n");
451
452 return 0;
453 }
454
ad3552r_configure_device(struct ad3552r_desc * dac)455 static int ad3552r_configure_device(struct ad3552r_desc *dac)
456 {
457 struct device *dev = &dac->spi->dev;
458 int err, cnt = 0;
459 u32 val, ch;
460
461 dac->gpio_ldac = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH);
462 if (IS_ERR(dac->gpio_ldac))
463 return dev_err_probe(dev, PTR_ERR(dac->gpio_ldac),
464 "Error getting gpio ldac");
465
466 err = ad3552r_get_ref_voltage(dev, &val);
467 if (err < 0)
468 return err;
469
470 err = ad3552r_update_reg_field(dac,
471 AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
472 AD3552R_MASK_REFERENCE_VOLTAGE_SEL,
473 FIELD_PREP(AD3552R_MASK_REFERENCE_VOLTAGE_SEL, val));
474 if (err)
475 return err;
476
477 err = ad3552r_get_drive_strength(dev, &val);
478 if (!err) {
479 err = ad3552r_update_reg_field(dac,
480 AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
481 AD3552R_MASK_SDO_DRIVE_STRENGTH,
482 FIELD_PREP(AD3552R_MASK_SDO_DRIVE_STRENGTH, val));
483 if (err)
484 return err;
485 }
486
487 dac->num_ch = device_get_child_node_count(dev);
488 if (!dac->num_ch) {
489 dev_err(dev, "No channels defined\n");
490 return -ENODEV;
491 }
492
493 device_for_each_child_node_scoped(dev, child) {
494 err = fwnode_property_read_u32(child, "reg", &ch);
495 if (err)
496 return dev_err_probe(dev, err,
497 "mandatory reg property missing\n");
498 if (ch >= dac->model_data->num_hw_channels)
499 return dev_err_probe(dev, -EINVAL,
500 "reg must be less than %d\n",
501 dac->model_data->num_hw_channels);
502
503 err = ad3552r_get_output_range(dev, dac->model_data,
504 child, &val);
505 if (err && err != -ENOENT)
506 return err;
507
508 if (!err) {
509 if (ch == 0)
510 val = FIELD_PREP(AD3552R_MASK_CH_OUTPUT_RANGE_SEL(0), val);
511 else
512 val = FIELD_PREP(AD3552R_MASK_CH_OUTPUT_RANGE_SEL(1), val);
513
514 err = ad3552r_update_reg_field(dac,
515 AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,
516 AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch),
517 val);
518 if (err)
519 return err;
520
521 dac->ch_data[ch].range = val;
522 } else if (dac->model_data->requires_output_range) {
523 return dev_err_probe(dev, -EINVAL,
524 "adi,output-range-microvolt is required for %s\n",
525 dac->model_data->model_name);
526 } else {
527 err = ad3552r_configure_custom_gain(dac, child, ch);
528 if (err)
529 return err;
530 }
531
532 ad3552r_calc_gain_and_offset(&dac->ch_data[ch], dac->model_data);
533 dac->enabled_ch |= BIT(ch);
534
535 if (ch == 0)
536 val = FIELD_PREP(AD3552R_MASK_CH(0), 1);
537 else
538 val = FIELD_PREP(AD3552R_MASK_CH(1), 1);
539
540 err = ad3552r_update_reg_field(dac,
541 AD3552R_REG_ADDR_CH_SELECT_16B,
542 AD3552R_MASK_CH(ch), val);
543 if (err < 0)
544 return err;
545
546 dac->channels[cnt] = AD3552R_CH_DAC(ch);
547 ++cnt;
548
549 }
550
551 /* Disable unused channels */
552 for_each_clear_bit(ch, &dac->enabled_ch,
553 dac->model_data->num_hw_channels) {
554 if (ch == 0)
555 val = FIELD_PREP(AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(0), 1);
556 else
557 val = FIELD_PREP(AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(1), 1);
558
559 err = ad3552r_update_reg_field(dac,
560 AD3552R_REG_ADDR_POWERDOWN_CONFIG,
561 AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch),
562 val);
563 if (err)
564 return err;
565 }
566
567 dac->num_ch = cnt;
568
569 return 0;
570 }
571
ad3552r_init(struct ad3552r_desc * dac)572 static int ad3552r_init(struct ad3552r_desc *dac)
573 {
574 int err;
575 u16 val, id;
576
577 err = ad3552r_reset(dac);
578 if (err) {
579 dev_err(&dac->spi->dev, "Reset failed\n");
580 return err;
581 }
582
583 err = ad3552r_check_scratch_pad(dac);
584 if (err) {
585 dev_err(&dac->spi->dev, "Scratch pad test failed\n");
586 return err;
587 }
588
589 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_L, &val);
590 if (err) {
591 dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_L\n");
592 return err;
593 }
594
595 id = val;
596 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_H, &val);
597 if (err) {
598 dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_H\n");
599 return err;
600 }
601
602 id |= val << 8;
603 if (id != dac->model_data->chip_id) {
604 dev_err(&dac->spi->dev, "Product id not matching\n");
605 return -ENODEV;
606 }
607
608 return ad3552r_configure_device(dac);
609 }
610
ad3552r_probe(struct spi_device * spi)611 static int ad3552r_probe(struct spi_device *spi)
612 {
613 struct ad3552r_desc *dac;
614 struct iio_dev *indio_dev;
615 int err;
616
617 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*dac));
618 if (!indio_dev)
619 return -ENOMEM;
620
621 dac = iio_priv(indio_dev);
622 dac->spi = spi;
623 dac->model_data = spi_get_device_match_data(spi);
624 if (!dac->model_data)
625 return -EINVAL;
626
627 mutex_init(&dac->lock);
628
629 err = ad3552r_init(dac);
630 if (err)
631 return err;
632
633 /* Config triggered buffer device */
634 indio_dev->name = dac->model_data->model_name;
635 indio_dev->dev.parent = &spi->dev;
636 indio_dev->info = &ad3552r_iio_info;
637 indio_dev->num_channels = dac->num_ch;
638 indio_dev->channels = dac->channels;
639 indio_dev->modes = INDIO_DIRECT_MODE;
640
641 err = devm_iio_triggered_buffer_setup_ext(&indio_dev->dev, indio_dev, NULL,
642 &ad3552r_trigger_handler,
643 IIO_BUFFER_DIRECTION_OUT,
644 NULL,
645 NULL);
646 if (err)
647 return err;
648
649 return devm_iio_device_register(&spi->dev, indio_dev);
650 }
651
652 static const struct ad3552r_model_data ad3541r_model_data = {
653 .model_name = "ad3541r",
654 .chip_id = AD3541R_ID,
655 .num_hw_channels = 1,
656 .ranges_table = ad3542r_ch_ranges,
657 .num_ranges = ARRAY_SIZE(ad3542r_ch_ranges),
658 .requires_output_range = true,
659 };
660
661 static const struct ad3552r_model_data ad3542r_model_data = {
662 .model_name = "ad3542r",
663 .chip_id = AD3542R_ID,
664 .num_hw_channels = 2,
665 .ranges_table = ad3542r_ch_ranges,
666 .num_ranges = ARRAY_SIZE(ad3542r_ch_ranges),
667 .requires_output_range = true,
668 };
669
670 static const struct ad3552r_model_data ad3551r_model_data = {
671 .model_name = "ad3551r",
672 .chip_id = AD3551R_ID,
673 .num_hw_channels = 1,
674 .ranges_table = ad3552r_ch_ranges,
675 .num_ranges = ARRAY_SIZE(ad3552r_ch_ranges),
676 .requires_output_range = false,
677 };
678
679 static const struct ad3552r_model_data ad3552r_model_data = {
680 .model_name = "ad3552r",
681 .chip_id = AD3552R_ID,
682 .num_hw_channels = 2,
683 .ranges_table = ad3552r_ch_ranges,
684 .num_ranges = ARRAY_SIZE(ad3552r_ch_ranges),
685 .requires_output_range = false,
686 };
687
688 static const struct spi_device_id ad3552r_id[] = {
689 {
690 .name = "ad3541r",
691 .driver_data = (kernel_ulong_t)&ad3541r_model_data
692 },
693 {
694 .name = "ad3542r",
695 .driver_data = (kernel_ulong_t)&ad3542r_model_data
696 },
697 {
698 .name = "ad3551r",
699 .driver_data = (kernel_ulong_t)&ad3551r_model_data
700 },
701 {
702 .name = "ad3552r",
703 .driver_data = (kernel_ulong_t)&ad3552r_model_data
704 },
705 { }
706 };
707 MODULE_DEVICE_TABLE(spi, ad3552r_id);
708
709 static const struct of_device_id ad3552r_of_match[] = {
710 { .compatible = "adi,ad3541r", .data = &ad3541r_model_data },
711 { .compatible = "adi,ad3542r", .data = &ad3542r_model_data },
712 { .compatible = "adi,ad3551r", .data = &ad3551r_model_data },
713 { .compatible = "adi,ad3552r", .data = &ad3552r_model_data },
714 { }
715 };
716 MODULE_DEVICE_TABLE(of, ad3552r_of_match);
717
718 static struct spi_driver ad3552r_driver = {
719 .driver = {
720 .name = "ad3552r",
721 .of_match_table = ad3552r_of_match,
722 },
723 .probe = ad3552r_probe,
724 .id_table = ad3552r_id
725 };
726 module_spi_driver(ad3552r_driver);
727
728 MODULE_AUTHOR("Mihail Chindris <mihail.chindris@analog.com>");
729 MODULE_DESCRIPTION("Analog Device AD3552R DAC");
730 MODULE_LICENSE("GPL v2");
731 MODULE_IMPORT_NS("IIO_AD3552R");
732