1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD3552R 4 * Digital to Analog converter driver, High Speed version 5 * 6 * Copyright 2024 Analog Devices Inc. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/iio/backend.h> 13 #include <linux/iio/buffer.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/units.h> 18 19 #include "ad3552r.h" 20 #include "ad3552r-hs.h" 21 22 struct ad3552r_hs_state { 23 const struct ad3552r_model_data *model_data; 24 struct gpio_desc *reset_gpio; 25 struct device *dev; 26 struct iio_backend *back; 27 bool single_channel; 28 struct ad3552r_ch_data ch_data[AD3552R_MAX_CH]; 29 struct ad3552r_hs_platform_data *data; 30 }; 31 32 static int ad3552r_qspi_update_reg_bits(struct ad3552r_hs_state *st, 33 u32 reg, u32 mask, u32 val, 34 size_t xfer_size) 35 { 36 u32 rval; 37 int ret; 38 39 ret = st->data->bus_reg_read(st->back, reg, &rval, xfer_size); 40 if (ret) 41 return ret; 42 43 rval = (rval & ~mask) | val; 44 45 return st->data->bus_reg_write(st->back, reg, rval, xfer_size); 46 } 47 48 static int ad3552r_hs_read_raw(struct iio_dev *indio_dev, 49 struct iio_chan_spec const *chan, 50 int *val, int *val2, long mask) 51 { 52 struct ad3552r_hs_state *st = iio_priv(indio_dev); 53 int ret; 54 int ch = chan->channel; 55 56 switch (mask) { 57 case IIO_CHAN_INFO_SAMP_FREQ: 58 /* 59 * Using 4 lanes (QSPI), then using 2 as DDR mode is 60 * considered always on (considering buffering mode always). 61 */ 62 *val = DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz * 63 4 * 2, chan->scan_type.realbits); 64 65 return IIO_VAL_INT; 66 67 case IIO_CHAN_INFO_RAW: 68 ret = st->data->bus_reg_read(st->back, 69 AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), 70 val, 2); 71 if (ret) 72 return ret; 73 74 return IIO_VAL_INT; 75 case IIO_CHAN_INFO_SCALE: 76 *val = st->ch_data[ch].scale_int; 77 *val2 = st->ch_data[ch].scale_dec; 78 return IIO_VAL_INT_PLUS_MICRO; 79 case IIO_CHAN_INFO_OFFSET: 80 *val = st->ch_data[ch].offset_int; 81 *val2 = st->ch_data[ch].offset_dec; 82 return IIO_VAL_INT_PLUS_MICRO; 83 default: 84 return -EINVAL; 85 } 86 } 87 88 static int ad3552r_hs_write_raw(struct iio_dev *indio_dev, 89 struct iio_chan_spec const *chan, 90 int val, int val2, long mask) 91 { 92 struct ad3552r_hs_state *st = iio_priv(indio_dev); 93 94 switch (mask) { 95 case IIO_CHAN_INFO_RAW: 96 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 97 return st->data->bus_reg_write(st->back, 98 AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), 99 val, 2); 100 } 101 unreachable(); 102 default: 103 return -EINVAL; 104 } 105 } 106 107 static int ad3552r_hs_buffer_postenable(struct iio_dev *indio_dev) 108 { 109 struct ad3552r_hs_state *st = iio_priv(indio_dev); 110 struct iio_backend_data_fmt fmt = { 111 .type = IIO_BACKEND_DATA_UNSIGNED 112 }; 113 int loop_len, val, ret; 114 115 switch (*indio_dev->active_scan_mask) { 116 case AD3552R_CH0_ACTIVE: 117 st->single_channel = true; 118 loop_len = 2; 119 val = AD3552R_REG_ADDR_CH_DAC_16B(0); 120 break; 121 case AD3552R_CH1_ACTIVE: 122 st->single_channel = true; 123 loop_len = 2; 124 val = AD3552R_REG_ADDR_CH_DAC_16B(1); 125 break; 126 case AD3552R_CH0_ACTIVE | AD3552R_CH1_ACTIVE: 127 st->single_channel = false; 128 loop_len = 4; 129 val = AD3552R_REG_ADDR_CH_DAC_16B(1); 130 break; 131 default: 132 return -EINVAL; 133 } 134 135 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_STREAM_MODE, 136 loop_len, 1); 137 if (ret) 138 return ret; 139 140 /* Inform DAC chip to switch into DDR mode */ 141 ret = ad3552r_qspi_update_reg_bits(st, 142 AD3552R_REG_ADDR_INTERFACE_CONFIG_D, 143 AD3552R_MASK_SPI_CONFIG_DDR, 144 AD3552R_MASK_SPI_CONFIG_DDR, 1); 145 if (ret) 146 return ret; 147 148 /* Inform DAC IP to go for DDR mode from now on */ 149 ret = iio_backend_ddr_enable(st->back); 150 if (ret) { 151 dev_err(st->dev, "could not set DDR mode, not streaming"); 152 goto exit_err; 153 } 154 155 ret = iio_backend_data_transfer_addr(st->back, val); 156 if (ret) 157 goto exit_err; 158 159 ret = iio_backend_data_format_set(st->back, 0, &fmt); 160 if (ret) 161 goto exit_err; 162 163 ret = iio_backend_data_stream_enable(st->back); 164 if (ret) 165 goto exit_err; 166 167 return 0; 168 169 exit_err: 170 ad3552r_qspi_update_reg_bits(st, 171 AD3552R_REG_ADDR_INTERFACE_CONFIG_D, 172 AD3552R_MASK_SPI_CONFIG_DDR, 173 0, 1); 174 175 iio_backend_ddr_disable(st->back); 176 177 return ret; 178 } 179 180 static int ad3552r_hs_buffer_predisable(struct iio_dev *indio_dev) 181 { 182 struct ad3552r_hs_state *st = iio_priv(indio_dev); 183 int ret; 184 185 ret = iio_backend_data_stream_disable(st->back); 186 if (ret) 187 return ret; 188 189 /* Inform DAC to set in SDR mode */ 190 ret = ad3552r_qspi_update_reg_bits(st, 191 AD3552R_REG_ADDR_INTERFACE_CONFIG_D, 192 AD3552R_MASK_SPI_CONFIG_DDR, 193 0, 1); 194 if (ret) 195 return ret; 196 197 ret = iio_backend_ddr_disable(st->back); 198 if (ret) 199 return ret; 200 201 return 0; 202 } 203 204 static inline int ad3552r_hs_set_output_range(struct ad3552r_hs_state *st, 205 int ch, unsigned int mode) 206 { 207 int val; 208 209 if (ch == 0) 210 val = FIELD_PREP(AD3552R_MASK_CH0_RANGE, mode); 211 else 212 val = FIELD_PREP(AD3552R_MASK_CH1_RANGE, mode); 213 214 return ad3552r_qspi_update_reg_bits(st, 215 AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE, 216 AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch), 217 val, 1); 218 } 219 220 static int ad3552r_hs_reset(struct ad3552r_hs_state *st) 221 { 222 int ret; 223 224 st->reset_gpio = devm_gpiod_get_optional(st->dev, 225 "reset", GPIOD_OUT_HIGH); 226 if (IS_ERR(st->reset_gpio)) 227 return PTR_ERR(st->reset_gpio); 228 229 if (st->reset_gpio) { 230 fsleep(10); 231 gpiod_set_value_cansleep(st->reset_gpio, 0); 232 } else { 233 ret = ad3552r_qspi_update_reg_bits(st, 234 AD3552R_REG_ADDR_INTERFACE_CONFIG_A, 235 AD3552R_MASK_SOFTWARE_RESET, 236 AD3552R_MASK_SOFTWARE_RESET, 1); 237 if (ret) 238 return ret; 239 } 240 msleep(100); 241 242 return 0; 243 } 244 245 static int ad3552r_hs_scratch_pad_test(struct ad3552r_hs_state *st) 246 { 247 int ret, val; 248 249 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, 250 AD3552R_SCRATCH_PAD_TEST_VAL1, 1); 251 if (ret) 252 return ret; 253 254 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, 255 &val, 1); 256 if (ret) 257 return ret; 258 259 if (val != AD3552R_SCRATCH_PAD_TEST_VAL1) 260 return dev_err_probe(st->dev, -EIO, 261 "SCRATCH_PAD_TEST mismatch. Expected 0x%x, Read 0x%x\n", 262 AD3552R_SCRATCH_PAD_TEST_VAL1, val); 263 264 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, 265 AD3552R_SCRATCH_PAD_TEST_VAL2, 1); 266 if (ret) 267 return ret; 268 269 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, 270 &val, 1); 271 if (ret) 272 return ret; 273 274 if (val != AD3552R_SCRATCH_PAD_TEST_VAL2) 275 return dev_err_probe(st->dev, -EIO, 276 "SCRATCH_PAD_TEST mismatch. Expected 0x%x, Read 0x%x\n", 277 AD3552R_SCRATCH_PAD_TEST_VAL2, val); 278 279 return 0; 280 } 281 282 static int ad3552r_hs_setup_custom_gain(struct ad3552r_hs_state *st, 283 int ch, u16 gain, u16 offset) 284 { 285 int ret; 286 287 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_OFFSET(ch), 288 offset, 1); 289 if (ret) 290 return ret; 291 292 return st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_GAIN(ch), 293 gain, 1); 294 } 295 296 static int ad3552r_hs_setup(struct ad3552r_hs_state *st) 297 { 298 u16 id; 299 u16 gain = 0, offset = 0; 300 u32 ch, val, range; 301 int ret; 302 303 ret = ad3552r_hs_reset(st); 304 if (ret) 305 return ret; 306 307 ret = iio_backend_ddr_disable(st->back); 308 if (ret) 309 return ret; 310 311 ret = ad3552r_hs_scratch_pad_test(st); 312 if (ret) 313 return ret; 314 315 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_PRODUCT_ID_L, 316 &val, 1); 317 if (ret) 318 return ret; 319 320 id = val; 321 322 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_PRODUCT_ID_H, 323 &val, 1); 324 if (ret) 325 return ret; 326 327 id |= val << 8; 328 if (id != st->model_data->chip_id) 329 dev_info(st->dev, "Chip ID error. Expected 0x%x, Read 0x%x\n", 330 AD3552R_ID, id); 331 332 ret = st->data->bus_reg_write(st->back, 333 AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, 334 0, 1); 335 if (ret) 336 return ret; 337 338 ret = st->data->bus_reg_write(st->back, 339 AD3552R_REG_ADDR_TRANSFER_REGISTER, 340 FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE, 341 AD3552R_QUAD_SPI) | 342 AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); 343 if (ret) 344 return ret; 345 346 ret = iio_backend_data_source_set(st->back, 0, IIO_BACKEND_EXTERNAL); 347 if (ret) 348 return ret; 349 350 ret = iio_backend_data_source_set(st->back, 1, IIO_BACKEND_EXTERNAL); 351 if (ret) 352 return ret; 353 354 ret = ad3552r_get_ref_voltage(st->dev, &val); 355 if (ret < 0) 356 return ret; 357 358 val = ret; 359 360 ret = ad3552r_qspi_update_reg_bits(st, 361 AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, 362 AD3552R_MASK_REFERENCE_VOLTAGE_SEL, 363 val, 1); 364 if (ret) 365 return ret; 366 367 ret = ad3552r_get_drive_strength(st->dev, &val); 368 if (!ret) { 369 ret = ad3552r_qspi_update_reg_bits(st, 370 AD3552R_REG_ADDR_INTERFACE_CONFIG_D, 371 AD3552R_MASK_SDO_DRIVE_STRENGTH, 372 val, 1); 373 if (ret) 374 return ret; 375 } 376 377 device_for_each_child_node_scoped(st->dev, child) { 378 ret = fwnode_property_read_u32(child, "reg", &ch); 379 if (ret) 380 return dev_err_probe(st->dev, ret, 381 "reg property missing\n"); 382 383 ret = ad3552r_get_output_range(st->dev, st->model_data, child, 384 &range); 385 if (ret && ret != -ENOENT) 386 return ret; 387 if (ret == -ENOENT) { 388 ret = ad3552r_get_custom_gain(st->dev, child, 389 &st->ch_data[ch].p, 390 &st->ch_data[ch].n, 391 &st->ch_data[ch].rfb, 392 &st->ch_data[ch].gain_offset); 393 if (ret) 394 return ret; 395 396 gain = ad3552r_calc_custom_gain(st->ch_data[ch].p, 397 st->ch_data[ch].n, 398 st->ch_data[ch].gain_offset); 399 offset = abs(st->ch_data[ch].gain_offset); 400 401 st->ch_data[ch].range_override = 1; 402 403 ret = ad3552r_hs_setup_custom_gain(st, ch, gain, 404 offset); 405 if (ret) 406 return ret; 407 } else { 408 st->ch_data[ch].range = range; 409 410 ret = ad3552r_hs_set_output_range(st, ch, range); 411 if (ret) 412 return ret; 413 } 414 415 ad3552r_calc_gain_and_offset(&st->ch_data[ch], st->model_data); 416 } 417 418 return 0; 419 } 420 421 static const struct iio_buffer_setup_ops ad3552r_hs_buffer_setup_ops = { 422 .postenable = ad3552r_hs_buffer_postenable, 423 .predisable = ad3552r_hs_buffer_predisable, 424 }; 425 426 #define AD3552R_CHANNEL(ch) { \ 427 .type = IIO_VOLTAGE, \ 428 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 429 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 430 BIT(IIO_CHAN_INFO_SCALE) | \ 431 BIT(IIO_CHAN_INFO_OFFSET), \ 432 .output = 1, \ 433 .indexed = 1, \ 434 .channel = (ch), \ 435 .scan_index = (ch), \ 436 .scan_type = { \ 437 .sign = 'u', \ 438 .realbits = 16, \ 439 .storagebits = 16, \ 440 .endianness = IIO_BE, \ 441 } \ 442 } 443 444 static const struct iio_chan_spec ad3552r_hs_channels[] = { 445 AD3552R_CHANNEL(0), 446 AD3552R_CHANNEL(1), 447 }; 448 449 static const struct iio_info ad3552r_hs_info = { 450 .read_raw = &ad3552r_hs_read_raw, 451 .write_raw = &ad3552r_hs_write_raw, 452 }; 453 454 static int ad3552r_hs_probe(struct platform_device *pdev) 455 { 456 struct ad3552r_hs_state *st; 457 struct iio_dev *indio_dev; 458 int ret; 459 460 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 461 if (!indio_dev) 462 return -ENOMEM; 463 464 st = iio_priv(indio_dev); 465 st->dev = &pdev->dev; 466 467 st->data = dev_get_platdata(st->dev); 468 if (!st->data) 469 return dev_err_probe(st->dev, -ENODEV, "No platform data !"); 470 471 st->back = devm_iio_backend_get(&pdev->dev, NULL); 472 if (IS_ERR(st->back)) 473 return PTR_ERR(st->back); 474 475 ret = devm_iio_backend_enable(&pdev->dev, st->back); 476 if (ret) 477 return ret; 478 479 st->model_data = device_get_match_data(&pdev->dev); 480 if (!st->model_data) 481 return -ENODEV; 482 483 indio_dev->name = "ad3552r"; 484 indio_dev->modes = INDIO_DIRECT_MODE; 485 indio_dev->setup_ops = &ad3552r_hs_buffer_setup_ops; 486 indio_dev->channels = ad3552r_hs_channels; 487 indio_dev->num_channels = ARRAY_SIZE(ad3552r_hs_channels); 488 indio_dev->info = &ad3552r_hs_info; 489 490 ret = devm_iio_backend_request_buffer(&pdev->dev, st->back, indio_dev); 491 if (ret) 492 return ret; 493 494 ret = ad3552r_hs_setup(st); 495 if (ret) 496 return ret; 497 498 return devm_iio_device_register(&pdev->dev, indio_dev); 499 } 500 501 static const struct ad3552r_model_data ad3552r_model_data = { 502 .model_name = "ad3552r", 503 .chip_id = AD3552R_ID, 504 .num_hw_channels = 2, 505 .ranges_table = ad3552r_ch_ranges, 506 .num_ranges = ARRAY_SIZE(ad3552r_ch_ranges), 507 }; 508 509 static const struct of_device_id ad3552r_hs_of_id[] = { 510 { .compatible = "adi,ad3552r", .data = &ad3552r_model_data }, 511 { } 512 }; 513 MODULE_DEVICE_TABLE(of, ad3552r_hs_of_id); 514 515 static struct platform_driver ad3552r_hs_driver = { 516 .driver = { 517 .name = "ad3552r-hs", 518 .of_match_table = ad3552r_hs_of_id, 519 }, 520 .probe = ad3552r_hs_probe, 521 }; 522 module_platform_driver(ad3552r_hs_driver); 523 524 MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>"); 525 MODULE_AUTHOR("Angelo Dureghello <adueghello@baylibre.com>"); 526 MODULE_DESCRIPTION("AD3552R Driver - High Speed version"); 527 MODULE_LICENSE("GPL"); 528 MODULE_IMPORT_NS("IIO_BACKEND"); 529 MODULE_IMPORT_NS("IIO_AD3552R"); 530