1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD3552R 4 * Digital to Analog converter driver, High Speed version 5 * 6 * Copyright 2024 Analog Devices Inc. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/debugfs.h> 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/iio/backend.h> 14 #include <linux/iio/buffer.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/units.h> 18 19 #include "ad3552r.h" 20 #include "ad3552r-hs.h" 21 22 /* 23 * Important notes for register map access: 24 * ======================================== 25 * 26 * Register address space is divided in 2 regions, primary (config) and 27 * secondary (DAC). Primary region can only be accessed in simple SPI mode, 28 * with exception for ad355x models where setting QSPI pin high allows QSPI 29 * access to both the regions. 30 * 31 * Due to the fact that ad3541/2r do not implement QSPI, for proper device 32 * detection, HDL keeps "QSPI" pin level low at boot (see ad3552r manual, rev B 33 * table 7, pin 31, digital input). For this reason, actually the working mode 34 * between SPI, DSPI and QSPI must be set via software, configuring the target 35 * DAC appropriately, together with the backend API to configure the bus mode 36 * accordingly. 37 * 38 * Also, important to note that none of the three modes allow to read in DDR. 39 * 40 * In non-buffering operations, mode is set to simple SPI SDR for all primary 41 * and secondary region r/w accesses, to avoid to switch the mode each time DAC 42 * register is accessed (raw accesses, r/w), and to be able to dump registers 43 * content (possible as non DDR only). 44 * In buffering mode, driver sets best possible mode, D/QSPI and DDR. 45 */ 46 47 struct ad3552r_hs_state { 48 const struct ad3552r_model_data *model_data; 49 struct gpio_desc *reset_gpio; 50 struct device *dev; 51 struct iio_backend *back; 52 bool single_channel; 53 struct ad3552r_ch_data ch_data[AD3552R_MAX_CH]; 54 struct ad3552r_hs_platform_data *data; 55 /* INTERFACE_CONFIG_D register cache, in DDR we cannot read values. */ 56 u32 config_d; 57 /* Protects backend I/O operations from concurrent accesses. */ 58 struct mutex lock; 59 }; 60 61 enum ad3552r_sources { 62 AD3552R_SRC_NORMAL, 63 AD3552R_SRC_RAMP_16BIT, 64 }; 65 66 static const char * const dbgfs_attr_source[] = { 67 [AD3552R_SRC_NORMAL] = "normal", 68 [AD3552R_SRC_RAMP_16BIT] = "ramp-16bit", 69 }; 70 71 static int ad3552r_hs_reg_read(struct ad3552r_hs_state *st, u32 reg, u32 *val, 72 size_t xfer_size) 73 { 74 /* No chip in the family supports DDR read. Informing of this. */ 75 WARN_ON_ONCE(st->config_d & AD3552R_MASK_SPI_CONFIG_DDR); 76 77 return st->data->bus_reg_read(st->back, reg, val, xfer_size); 78 } 79 80 static int ad3552r_hs_set_data_source(struct ad3552r_hs_state *st, 81 enum iio_backend_data_source type) 82 { 83 int i, ret; 84 85 for (i = 0; i < st->model_data->num_hw_channels; ++i) { 86 ret = iio_backend_data_source_set(st->back, i, type); 87 if (ret) 88 return ret; 89 } 90 91 return 0; 92 } 93 94 static int ad3552r_hs_update_reg_bits(struct ad3552r_hs_state *st, u32 reg, 95 u32 mask, u32 val, size_t xfer_size) 96 { 97 u32 rval; 98 int ret; 99 100 ret = ad3552r_hs_reg_read(st, reg, &rval, xfer_size); 101 if (ret) 102 return ret; 103 104 rval = (rval & ~mask) | val; 105 106 return st->data->bus_reg_write(st->back, reg, rval, xfer_size); 107 } 108 109 static int ad3552r_hs_read_raw(struct iio_dev *indio_dev, 110 struct iio_chan_spec const *chan, 111 int *val, int *val2, long mask) 112 { 113 struct ad3552r_hs_state *st = iio_priv(indio_dev); 114 int ret; 115 int ch = chan->channel; 116 117 switch (mask) { 118 case IIO_CHAN_INFO_SAMP_FREQ: 119 /* 120 * Using a "num_spi_data_lanes" variable since ad3541/2 have 121 * only DSPI interface, while ad355x is QSPI. Then using 2 as 122 * DDR mode is considered always on (considering buffering 123 * mode always). 124 */ 125 *val = DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz * 126 st->model_data->num_spi_data_lanes * 2, 127 chan->scan_type.realbits); 128 129 return IIO_VAL_INT; 130 131 case IIO_CHAN_INFO_RAW: 132 /* For RAW accesses, stay always in simple-spi. */ 133 ret = ad3552r_hs_reg_read(st, 134 AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), 135 val, 2); 136 if (ret) 137 return ret; 138 139 return IIO_VAL_INT; 140 case IIO_CHAN_INFO_SCALE: 141 *val = st->ch_data[ch].scale_int; 142 *val2 = st->ch_data[ch].scale_dec; 143 return IIO_VAL_INT_PLUS_MICRO; 144 case IIO_CHAN_INFO_OFFSET: 145 *val = st->ch_data[ch].offset_int; 146 *val2 = st->ch_data[ch].offset_dec; 147 return IIO_VAL_INT_PLUS_MICRO; 148 default: 149 return -EINVAL; 150 } 151 } 152 153 static int ad3552r_hs_write_raw(struct iio_dev *indio_dev, 154 struct iio_chan_spec const *chan, 155 int val, int val2, long mask) 156 { 157 struct ad3552r_hs_state *st = iio_priv(indio_dev); 158 int ret; 159 160 switch (mask) { 161 case IIO_CHAN_INFO_RAW: 162 if (!iio_device_claim_direct(indio_dev)) 163 return -EBUSY; 164 /* For RAW accesses, stay always in simple-spi. */ 165 ret = st->data->bus_reg_write(st->back, 166 AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), 167 val, 2); 168 169 iio_device_release_direct(indio_dev); 170 return ret; 171 default: 172 return -EINVAL; 173 } 174 } 175 176 static int ad3552r_hs_set_bus_io_mode_hs(struct ad3552r_hs_state *st) 177 { 178 int bus_mode; 179 180 if (st->model_data->num_spi_data_lanes == 4) 181 bus_mode = AD3552R_IO_MODE_QSPI; 182 else 183 bus_mode = AD3552R_IO_MODE_DSPI; 184 185 return st->data->bus_set_io_mode(st->back, bus_mode); 186 } 187 188 static int ad3552r_hs_set_target_io_mode_hs(struct ad3552r_hs_state *st) 189 { 190 u32 mode_target; 191 192 /* 193 * Best access for secondary reg area, QSPI where possible, 194 * else as DSPI. 195 */ 196 if (st->model_data->num_spi_data_lanes == 4) 197 mode_target = AD3552R_QUAD_SPI; 198 else 199 mode_target = AD3552R_DUAL_SPI; 200 201 /* 202 * Better to not use update here, since generally it is already 203 * set as DDR mode, and it's not possible to read in DDR mode. 204 */ 205 return st->data->bus_reg_write(st->back, 206 AD3552R_REG_ADDR_TRANSFER_REGISTER, 207 FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE, 208 mode_target) | 209 AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); 210 } 211 212 static int ad3552r_hs_buffer_postenable(struct iio_dev *indio_dev) 213 { 214 struct ad3552r_hs_state *st = iio_priv(indio_dev); 215 struct iio_backend_data_fmt fmt = { 216 .type = IIO_BACKEND_DATA_UNSIGNED 217 }; 218 int loop_len, val, ret; 219 220 switch (*indio_dev->active_scan_mask) { 221 case AD3552R_CH0_ACTIVE: 222 st->single_channel = true; 223 loop_len = 2; 224 val = AD3552R_REG_ADDR_CH_DAC_16B(0); 225 break; 226 case AD3552R_CH1_ACTIVE: 227 st->single_channel = true; 228 loop_len = 2; 229 val = AD3552R_REG_ADDR_CH_DAC_16B(1); 230 break; 231 case AD3552R_CH0_ACTIVE | AD3552R_CH1_ACTIVE: 232 st->single_channel = false; 233 loop_len = 4; 234 val = AD3552R_REG_ADDR_CH_DAC_16B(1); 235 break; 236 default: 237 return -EINVAL; 238 } 239 240 /* 241 * With ad3541/2r support, QSPI pin is held low at reset from HDL, 242 * streaming start sequence must respect strictly the order below. 243 */ 244 245 /* Primary region access, set streaming mode (now in SPI + SDR). */ 246 ret = ad3552r_hs_update_reg_bits(st, 247 AD3552R_REG_ADDR_INTERFACE_CONFIG_B, 248 AD3552R_MASK_SINGLE_INST, 0, 1); 249 if (ret) 250 return ret; 251 252 /* 253 * Set target loop len, keeping the value: streaming writes at address 254 * 0x2c or 0x2a, in descending loop (2 or 4 bytes), keeping loop len 255 * value so that it's not cleared hereafter when _CS is deasserted. 256 */ 257 ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER, 258 AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 259 AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 260 1); 261 if (ret) 262 goto exit_err_streaming; 263 264 ret = st->data->bus_reg_write(st->back, 265 AD3552R_REG_ADDR_STREAM_MODE, 266 loop_len, 1); 267 if (ret) 268 goto exit_err_streaming; 269 270 st->config_d |= AD3552R_MASK_SPI_CONFIG_DDR; 271 ret = st->data->bus_reg_write(st->back, 272 AD3552R_REG_ADDR_INTERFACE_CONFIG_D, 273 st->config_d, 1); 274 if (ret) 275 goto exit_err_streaming; 276 277 ret = iio_backend_ddr_enable(st->back); 278 if (ret) 279 goto exit_err_ddr_mode_target; 280 281 /* 282 * From here onward mode is DDR, so reading any register is not possible 283 * anymore, including calling "ad3552r_hs_update_reg_bits" function. 284 */ 285 286 /* Set target to best high speed mode (D or QSPI). */ 287 ret = ad3552r_hs_set_target_io_mode_hs(st); 288 if (ret) 289 goto exit_err_ddr_mode; 290 291 /* Set bus to best high speed mode (D or QSPI). */ 292 ret = ad3552r_hs_set_bus_io_mode_hs(st); 293 if (ret) 294 goto exit_err_bus_mode_target; 295 296 /* 297 * Backend setup must be done now only, or related register values will 298 * be disrupted by previous bus accesses. 299 */ 300 ret = iio_backend_data_transfer_addr(st->back, val); 301 if (ret) 302 goto exit_err_bus_mode_target; 303 304 ret = iio_backend_data_format_set(st->back, 0, &fmt); 305 if (ret) 306 goto exit_err_bus_mode_target; 307 308 ret = iio_backend_data_stream_enable(st->back); 309 if (ret) 310 goto exit_err_bus_mode_target; 311 312 return 0; 313 314 exit_err_bus_mode_target: 315 /* Back to simple SPI, not using update to avoid read. */ 316 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_TRANSFER_REGISTER, 317 FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE, 318 AD3552R_SPI) | 319 AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); 320 321 /* 322 * Back bus to simple SPI, this must be executed together with above 323 * target mode unwind, and can be done only after it. 324 */ 325 st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI); 326 327 exit_err_ddr_mode: 328 iio_backend_ddr_disable(st->back); 329 330 exit_err_ddr_mode_target: 331 /* 332 * Back to SDR. In DDR we cannot read, whatever the mode is, so not 333 * using update. 334 */ 335 st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR; 336 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D, 337 st->config_d, 1); 338 339 exit_err_streaming: 340 /* Back to single instruction mode, disabling loop. */ 341 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_B, 342 AD3552R_MASK_SINGLE_INST | 343 AD3552R_MASK_SHORT_INSTRUCTION, 1); 344 345 return ret; 346 } 347 348 static int ad3552r_hs_buffer_predisable(struct iio_dev *indio_dev) 349 { 350 struct ad3552r_hs_state *st = iio_priv(indio_dev); 351 int ret; 352 353 ret = iio_backend_data_stream_disable(st->back); 354 if (ret) 355 return ret; 356 357 /* 358 * Set us to simple SPI, even if still in ddr, so to be able to write 359 * in primary region. 360 */ 361 ret = st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI); 362 if (ret) 363 return ret; 364 365 /* 366 * Back to SDR (in DDR we cannot read, whatever the mode is, so not 367 * using update). 368 */ 369 st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR; 370 ret = st->data->bus_reg_write(st->back, 371 AD3552R_REG_ADDR_INTERFACE_CONFIG_D, 372 st->config_d, 1); 373 if (ret) 374 return ret; 375 376 ret = iio_backend_ddr_disable(st->back); 377 if (ret) 378 return ret; 379 380 /* 381 * Back to simple SPI for secondary region too now, so to be able to 382 * dump/read registers there too if needed. 383 */ 384 ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER, 385 AD3552R_MASK_MULTI_IO_MODE, 386 AD3552R_SPI, 1); 387 if (ret) 388 return ret; 389 390 /* Back to single instruction mode, disabling loop. */ 391 ret = ad3552r_hs_update_reg_bits(st, 392 AD3552R_REG_ADDR_INTERFACE_CONFIG_B, 393 AD3552R_MASK_SINGLE_INST, 394 AD3552R_MASK_SINGLE_INST, 1); 395 if (ret) 396 return ret; 397 398 return 0; 399 } 400 401 static inline int ad3552r_hs_set_output_range(struct ad3552r_hs_state *st, 402 int ch, unsigned int mode) 403 { 404 int val; 405 406 if (ch == 0) 407 val = FIELD_PREP(AD3552R_MASK_CH0_RANGE, mode); 408 else 409 val = FIELD_PREP(AD3552R_MASK_CH1_RANGE, mode); 410 411 return ad3552r_hs_update_reg_bits(st, 412 AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE, 413 AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch), 414 val, 1); 415 } 416 417 static int ad3552r_hs_reset(struct ad3552r_hs_state *st) 418 { 419 int ret; 420 421 st->reset_gpio = devm_gpiod_get_optional(st->dev, 422 "reset", GPIOD_OUT_HIGH); 423 if (IS_ERR(st->reset_gpio)) 424 return PTR_ERR(st->reset_gpio); 425 426 if (st->reset_gpio) { 427 fsleep(10); 428 gpiod_set_value_cansleep(st->reset_gpio, 0); 429 } else { 430 ret = ad3552r_hs_update_reg_bits(st, 431 AD3552R_REG_ADDR_INTERFACE_CONFIG_A, 432 AD3552R_MASK_SOFTWARE_RESET, 433 AD3552R_MASK_SOFTWARE_RESET, 1); 434 if (ret) 435 return ret; 436 } 437 msleep(100); 438 439 return 0; 440 } 441 442 static int ad3552r_hs_scratch_pad_test(struct ad3552r_hs_state *st) 443 { 444 int ret, val; 445 446 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, 447 AD3552R_SCRATCH_PAD_TEST_VAL1, 1); 448 if (ret) 449 return ret; 450 451 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, 452 &val, 1); 453 if (ret) 454 return ret; 455 456 if (val != AD3552R_SCRATCH_PAD_TEST_VAL1) 457 return dev_err_probe(st->dev, -EIO, 458 "SCRATCH_PAD_TEST mismatch. Expected 0x%x, Read 0x%x\n", 459 AD3552R_SCRATCH_PAD_TEST_VAL1, val); 460 461 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, 462 AD3552R_SCRATCH_PAD_TEST_VAL2, 1); 463 if (ret) 464 return ret; 465 466 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, 467 &val, 1); 468 if (ret) 469 return ret; 470 471 if (val != AD3552R_SCRATCH_PAD_TEST_VAL2) 472 return dev_err_probe(st->dev, -EIO, 473 "SCRATCH_PAD_TEST mismatch. Expected 0x%x, Read 0x%x\n", 474 AD3552R_SCRATCH_PAD_TEST_VAL2, val); 475 476 return 0; 477 } 478 479 static int ad3552r_hs_setup_custom_gain(struct ad3552r_hs_state *st, 480 int ch, u16 gain, u16 offset) 481 { 482 int ret; 483 484 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_OFFSET(ch), 485 offset, 1); 486 if (ret) 487 return ret; 488 489 return st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_GAIN(ch), 490 gain, 1); 491 } 492 493 static int ad3552r_hs_reg_access(struct iio_dev *indio_dev, unsigned int reg, 494 unsigned int writeval, unsigned int *readval) 495 { 496 struct ad3552r_hs_state *st = iio_priv(indio_dev); 497 498 if (reg > st->model_data->max_reg_addr) 499 return -EINVAL; 500 501 /* 502 * There are 8, 16 or 24 bit registers, but HDL supports only reading 8 503 * or 16 bit data, not 24. So, also to avoid to check any proper read 504 * alignment, supporting only 8-bit readings here. 505 */ 506 if (readval) 507 return ad3552r_hs_reg_read(st, reg, readval, 1); 508 509 return st->data->bus_reg_write(st->back, reg, writeval, 1); 510 } 511 512 static ssize_t ad3552r_hs_show_data_source(struct file *f, char __user *userbuf, 513 size_t count, loff_t *ppos) 514 { 515 struct ad3552r_hs_state *st = file_inode(f)->i_private; 516 enum iio_backend_data_source type; 517 int idx, ret; 518 519 guard(mutex)(&st->lock); 520 521 ret = iio_backend_data_source_get(st->back, 0, &type); 522 if (ret) 523 return ret; 524 525 switch (type) { 526 case IIO_BACKEND_INTERNAL_RAMP_16BIT: 527 idx = AD3552R_SRC_RAMP_16BIT; 528 break; 529 case IIO_BACKEND_EXTERNAL: 530 idx = AD3552R_SRC_NORMAL; 531 break; 532 default: 533 return -EINVAL; 534 } 535 536 return simple_read_from_buffer(userbuf, count, ppos, 537 dbgfs_attr_source[idx], 538 strlen(dbgfs_attr_source[idx])); 539 } 540 541 static ssize_t ad3552r_hs_write_data_source(struct file *f, 542 const char __user *userbuf, 543 size_t count, loff_t *ppos) 544 { 545 struct ad3552r_hs_state *st = file_inode(f)->i_private; 546 char buf[64]; 547 int ret, source; 548 549 guard(mutex)(&st->lock); 550 551 if (*ppos != 0 || count >= sizeof(buf)) 552 return -ENOSPC; 553 554 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, userbuf, 555 count); 556 if (ret < 0) 557 return ret; 558 559 buf[ret] = '\0'; 560 561 ret = match_string(dbgfs_attr_source, ARRAY_SIZE(dbgfs_attr_source), 562 buf); 563 if (ret < 0) 564 return ret; 565 566 switch (ret) { 567 case AD3552R_SRC_RAMP_16BIT: 568 source = IIO_BACKEND_INTERNAL_RAMP_16BIT; 569 break; 570 case AD3552R_SRC_NORMAL: 571 source = IIO_BACKEND_EXTERNAL; 572 break; 573 default: 574 return -EINVAL; 575 } 576 577 ret = ad3552r_hs_set_data_source(st, source); 578 if (ret) 579 return ret; 580 581 return count; 582 } 583 584 static ssize_t ad3552r_hs_show_data_source_avail(struct file *f, 585 char __user *userbuf, 586 size_t count, loff_t *ppos) 587 { 588 ssize_t len = 0; 589 char buf[128]; 590 int i; 591 592 for (i = 0; i < ARRAY_SIZE(dbgfs_attr_source); i++) { 593 len += scnprintf(buf + len, sizeof(buf) - len, "%s ", 594 dbgfs_attr_source[i]); 595 } 596 buf[len - 1] = '\n'; 597 598 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 599 } 600 601 static const struct file_operations ad3552r_hs_data_source_fops = { 602 .owner = THIS_MODULE, 603 .write = ad3552r_hs_write_data_source, 604 .read = ad3552r_hs_show_data_source, 605 }; 606 607 static const struct file_operations ad3552r_hs_data_source_avail_fops = { 608 .owner = THIS_MODULE, 609 .read = ad3552r_hs_show_data_source_avail, 610 }; 611 612 static int ad3552r_hs_setup(struct ad3552r_hs_state *st) 613 { 614 u16 id; 615 u16 gain = 0, offset = 0; 616 u32 ch, val, range; 617 int ret; 618 619 ret = ad3552r_hs_reset(st); 620 if (ret) 621 return ret; 622 623 /* HDL starts with DDR enabled, disabling it. */ 624 ret = iio_backend_ddr_disable(st->back); 625 if (ret) 626 return ret; 627 628 ret = st->data->bus_reg_write(st->back, 629 AD3552R_REG_ADDR_INTERFACE_CONFIG_B, 630 AD3552R_MASK_SINGLE_INST | 631 AD3552R_MASK_SHORT_INSTRUCTION, 1); 632 if (ret) 633 return ret; 634 635 ret = ad3552r_hs_scratch_pad_test(st); 636 if (ret) 637 return ret; 638 639 /* 640 * Caching config_d, needed to restore it after streaming, 641 * and also, to detect possible DDR read, that's not allowed. 642 */ 643 ret = st->data->bus_reg_read(st->back, 644 AD3552R_REG_ADDR_INTERFACE_CONFIG_D, 645 &st->config_d, 1); 646 if (ret) 647 return ret; 648 649 ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_L, &val, 1); 650 if (ret) 651 return ret; 652 653 id = val; 654 655 ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_H, &val, 1); 656 if (ret) 657 return ret; 658 659 id |= val << 8; 660 if (id != st->model_data->chip_id) 661 dev_warn(st->dev, 662 "chip ID mismatch, detected 0x%x but expected 0x%x\n", 663 id, st->model_data->chip_id); 664 665 dev_dbg(st->dev, "chip id %s detected", st->model_data->model_name); 666 667 /* Clear reset error flag, see ad3552r manual, rev B table 38. */ 668 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS, 669 AD3552R_MASK_RESET_STATUS, 1); 670 if (ret) 671 return ret; 672 673 ret = st->data->bus_reg_write(st->back, 674 AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, 675 0, 1); 676 if (ret) 677 return ret; 678 679 ret = ad3552r_hs_set_data_source(st, IIO_BACKEND_EXTERNAL); 680 if (ret) 681 return ret; 682 683 ret = ad3552r_get_ref_voltage(st->dev, &val); 684 if (ret < 0) 685 return ret; 686 687 val = ret; 688 689 ret = ad3552r_hs_update_reg_bits(st, 690 AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, 691 AD3552R_MASK_REFERENCE_VOLTAGE_SEL, 692 val, 1); 693 if (ret) 694 return ret; 695 696 ret = ad3552r_get_drive_strength(st->dev, &val); 697 if (!ret) { 698 st->config_d |= 699 FIELD_PREP(AD3552R_MASK_SDO_DRIVE_STRENGTH, val); 700 701 ret = st->data->bus_reg_write(st->back, 702 AD3552R_REG_ADDR_INTERFACE_CONFIG_D, 703 st->config_d, 1); 704 if (ret) 705 return ret; 706 } 707 708 device_for_each_child_node_scoped(st->dev, child) { 709 ret = fwnode_property_read_u32(child, "reg", &ch); 710 if (ret) 711 return dev_err_probe(st->dev, ret, 712 "reg property missing\n"); 713 714 ret = ad3552r_get_output_range(st->dev, st->model_data, child, 715 &range); 716 if (ret && ret != -ENOENT) 717 return ret; 718 if (ret == -ENOENT) { 719 ret = ad3552r_get_custom_gain(st->dev, child, 720 &st->ch_data[ch].p, 721 &st->ch_data[ch].n, 722 &st->ch_data[ch].rfb, 723 &st->ch_data[ch].gain_offset); 724 if (ret) 725 return ret; 726 727 gain = ad3552r_calc_custom_gain(st->ch_data[ch].p, 728 st->ch_data[ch].n, 729 st->ch_data[ch].gain_offset); 730 offset = abs(st->ch_data[ch].gain_offset); 731 732 st->ch_data[ch].range_override = 1; 733 734 ret = ad3552r_hs_setup_custom_gain(st, ch, gain, 735 offset); 736 if (ret) 737 return ret; 738 } else { 739 st->ch_data[ch].range = range; 740 741 ret = ad3552r_hs_set_output_range(st, ch, range); 742 if (ret) 743 return ret; 744 } 745 746 ad3552r_calc_gain_and_offset(&st->ch_data[ch], st->model_data); 747 } 748 749 return 0; 750 } 751 752 static const struct iio_buffer_setup_ops ad3552r_hs_buffer_setup_ops = { 753 .postenable = ad3552r_hs_buffer_postenable, 754 .predisable = ad3552r_hs_buffer_predisable, 755 }; 756 757 #define AD3552R_CHANNEL(ch) { \ 758 .type = IIO_VOLTAGE, \ 759 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 760 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 761 BIT(IIO_CHAN_INFO_SCALE) | \ 762 BIT(IIO_CHAN_INFO_OFFSET), \ 763 .output = 1, \ 764 .indexed = 1, \ 765 .channel = (ch), \ 766 .scan_index = (ch), \ 767 .scan_type = { \ 768 .sign = 'u', \ 769 .realbits = 16, \ 770 .storagebits = 16, \ 771 .endianness = IIO_BE, \ 772 } \ 773 } 774 775 static const struct iio_chan_spec ad3552r_hs_channels[] = { 776 AD3552R_CHANNEL(0), 777 AD3552R_CHANNEL(1), 778 }; 779 780 static const struct iio_info ad3552r_hs_info = { 781 .read_raw = &ad3552r_hs_read_raw, 782 .write_raw = &ad3552r_hs_write_raw, 783 .debugfs_reg_access = &ad3552r_hs_reg_access, 784 }; 785 786 static void ad3552r_hs_debugfs_init(struct iio_dev *indio_dev) 787 { 788 struct ad3552r_hs_state *st = iio_priv(indio_dev); 789 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 790 791 if (!IS_ENABLED(CONFIG_DEBUG_FS)) 792 return; 793 794 d = iio_get_debugfs_dentry(indio_dev); 795 if (!d) { 796 dev_warn(st->dev, "can't set debugfs in driver dir\n"); 797 return; 798 } 799 800 debugfs_create_file("data_source", 0600, d, st, 801 &ad3552r_hs_data_source_fops); 802 debugfs_create_file("data_source_available", 0600, d, st, 803 &ad3552r_hs_data_source_avail_fops); 804 } 805 806 static int ad3552r_hs_probe(struct platform_device *pdev) 807 { 808 struct ad3552r_hs_state *st; 809 struct iio_dev *indio_dev; 810 int ret; 811 812 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 813 if (!indio_dev) 814 return -ENOMEM; 815 816 st = iio_priv(indio_dev); 817 st->dev = &pdev->dev; 818 819 st->data = dev_get_platdata(st->dev); 820 if (!st->data) 821 return dev_err_probe(st->dev, -ENODEV, "No platform data !"); 822 823 st->back = devm_iio_backend_get(&pdev->dev, NULL); 824 if (IS_ERR(st->back)) 825 return PTR_ERR(st->back); 826 827 ret = devm_iio_backend_enable(&pdev->dev, st->back); 828 if (ret) 829 return ret; 830 831 st->model_data = device_get_match_data(&pdev->dev); 832 if (!st->model_data) 833 return -ENODEV; 834 835 indio_dev->name = "ad3552r"; 836 indio_dev->modes = INDIO_DIRECT_MODE; 837 indio_dev->setup_ops = &ad3552r_hs_buffer_setup_ops; 838 indio_dev->channels = ad3552r_hs_channels; 839 indio_dev->num_channels = ARRAY_SIZE(ad3552r_hs_channels); 840 indio_dev->info = &ad3552r_hs_info; 841 842 ret = devm_iio_backend_request_buffer(&pdev->dev, st->back, indio_dev); 843 if (ret) 844 return ret; 845 846 ret = ad3552r_hs_setup(st); 847 if (ret) 848 return ret; 849 850 ret = devm_iio_device_register(&pdev->dev, indio_dev); 851 if (ret) 852 return ret; 853 854 ret = devm_mutex_init(&pdev->dev, &st->lock); 855 if (ret) 856 return ret; 857 858 ad3552r_hs_debugfs_init(indio_dev); 859 860 return ret; 861 } 862 863 static const struct of_device_id ad3552r_hs_of_id[] = { 864 { .compatible = "adi,ad3541r", .data = &ad3541r_model_data }, 865 { .compatible = "adi,ad3542r", .data = &ad3542r_model_data }, 866 { .compatible = "adi,ad3551r", .data = &ad3551r_model_data }, 867 { .compatible = "adi,ad3552r", .data = &ad3552r_model_data }, 868 { } 869 }; 870 MODULE_DEVICE_TABLE(of, ad3552r_hs_of_id); 871 872 static struct platform_driver ad3552r_hs_driver = { 873 .driver = { 874 .name = "ad3552r-hs", 875 .of_match_table = ad3552r_hs_of_id, 876 }, 877 .probe = ad3552r_hs_probe, 878 }; 879 module_platform_driver(ad3552r_hs_driver); 880 881 MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>"); 882 MODULE_AUTHOR("Angelo Dureghello <adueghello@baylibre.com>"); 883 MODULE_DESCRIPTION("AD3552R Driver - High Speed version"); 884 MODULE_LICENSE("GPL"); 885 MODULE_IMPORT_NS("IIO_BACKEND"); 886 MODULE_IMPORT_NS("IIO_AD3552R"); 887