1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD3530R/AD3530 8-channel, 16-bit Voltage Output DAC Driver 4 * AD3531R/AD3531 4-channel, 16-bit Voltage Output DAC Driver 5 * 6 * Copyright 2025 Analog Devices Inc. 7 */ 8 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/cleanup.h> 13 #include <linux/delay.h> 14 #include <linux/dev_printk.h> 15 #include <linux/err.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/iio/iio.h> 18 #include <linux/kstrtox.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/property.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/spi/spi.h> 26 #include <linux/sysfs.h> 27 #include <linux/types.h> 28 #include <linux/units.h> 29 30 #define AD3530R_INTERFACE_CONFIG_A 0x00 31 #define AD3530R_OUTPUT_OPERATING_MODE_0 0x20 32 #define AD3530R_OUTPUT_OPERATING_MODE_1 0x21 33 #define AD3530R_OUTPUT_CONTROL_0 0x2A 34 #define AD3530R_REFERENCE_CONTROL_0 0x3C 35 #define AD3530R_SW_LDAC_TRIG_A 0xE5 36 #define AD3530R_INPUT_CH 0xEB 37 #define AD3530R_MAX_REG_ADDR 0xF9 38 39 #define AD3531R_SW_LDAC_TRIG_A 0xDD 40 #define AD3531R_INPUT_CH 0xE3 41 42 #define AD3530R_SLD_TRIG_A BIT(7) 43 #define AD3530R_OUTPUT_CONTROL_RANGE BIT(2) 44 #define AD3530R_REFERENCE_CONTROL_SEL BIT(0) 45 #define AD3530R_REG_VAL_MASK GENMASK(15, 0) 46 #define AD3530R_OP_MODE_CHAN_MSK(chan) (GENMASK(1, 0) << 2 * (chan)) 47 48 #define AD3530R_SW_RESET (BIT(7) | BIT(0)) 49 #define AD3530R_INTERNAL_VREF_mV 2500 50 #define AD3530R_LDAC_PULSE_US 100 51 52 #define AD3530R_DAC_MAX_VAL GENMASK(15, 0) 53 #define AD3530R_MAX_CHANNELS 8 54 #define AD3531R_MAX_CHANNELS 4 55 56 /* Non-constant mask variant of FIELD_PREP() */ 57 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 58 59 enum ad3530r_mode { 60 AD3530R_NORMAL_OP, 61 AD3530R_POWERDOWN_1K, 62 AD3530R_POWERDOWN_7K7, 63 AD3530R_POWERDOWN_32K, 64 }; 65 66 struct ad3530r_chan { 67 enum ad3530r_mode powerdown_mode; 68 bool powerdown; 69 }; 70 71 struct ad3530r_chip_info { 72 const char *name; 73 const struct iio_chan_spec *channels; 74 int (*input_ch_reg)(unsigned int channel); 75 unsigned int num_channels; 76 unsigned int sw_ldac_trig_reg; 77 bool internal_ref_support; 78 }; 79 80 struct ad3530r_state { 81 struct regmap *regmap; 82 /* lock to protect against multiple access to the device and shared data */ 83 struct mutex lock; 84 struct ad3530r_chan chan[AD3530R_MAX_CHANNELS]; 85 const struct ad3530r_chip_info *chip_info; 86 struct gpio_desc *ldac_gpio; 87 int vref_mV; 88 /* 89 * DMA (thus cache coherency maintenance) may require the transfer 90 * buffers to live in their own cache lines. 91 */ 92 __be16 buf __aligned(IIO_DMA_MINALIGN); 93 }; 94 95 static int ad3530r_input_ch_reg(unsigned int channel) 96 { 97 return 2 * channel + AD3530R_INPUT_CH; 98 } 99 100 static int ad3531r_input_ch_reg(unsigned int channel) 101 { 102 return 2 * channel + AD3531R_INPUT_CH; 103 } 104 105 static const char * const ad3530r_powerdown_modes[] = { 106 "1kohm_to_gnd", 107 "7.7kohm_to_gnd", 108 "32kohm_to_gnd", 109 }; 110 111 static int ad3530r_get_powerdown_mode(struct iio_dev *indio_dev, 112 const struct iio_chan_spec *chan) 113 { 114 struct ad3530r_state *st = iio_priv(indio_dev); 115 116 guard(mutex)(&st->lock); 117 return st->chan[chan->channel].powerdown_mode - 1; 118 } 119 120 static int ad3530r_set_powerdown_mode(struct iio_dev *indio_dev, 121 const struct iio_chan_spec *chan, 122 unsigned int mode) 123 { 124 struct ad3530r_state *st = iio_priv(indio_dev); 125 126 guard(mutex)(&st->lock); 127 st->chan[chan->channel].powerdown_mode = mode + 1; 128 129 return 0; 130 } 131 132 static const struct iio_enum ad3530r_powerdown_mode_enum = { 133 .items = ad3530r_powerdown_modes, 134 .num_items = ARRAY_SIZE(ad3530r_powerdown_modes), 135 .get = ad3530r_get_powerdown_mode, 136 .set = ad3530r_set_powerdown_mode, 137 }; 138 139 static ssize_t ad3530r_get_dac_powerdown(struct iio_dev *indio_dev, 140 uintptr_t private, 141 const struct iio_chan_spec *chan, 142 char *buf) 143 { 144 struct ad3530r_state *st = iio_priv(indio_dev); 145 146 guard(mutex)(&st->lock); 147 return sysfs_emit(buf, "%d\n", st->chan[chan->channel].powerdown); 148 } 149 150 static ssize_t ad3530r_set_dac_powerdown(struct iio_dev *indio_dev, 151 uintptr_t private, 152 const struct iio_chan_spec *chan, 153 const char *buf, size_t len) 154 { 155 struct ad3530r_state *st = iio_priv(indio_dev); 156 int ret; 157 unsigned int reg, pdmode, mask, val; 158 bool powerdown; 159 160 ret = kstrtobool(buf, &powerdown); 161 if (ret) 162 return ret; 163 164 guard(mutex)(&st->lock); 165 reg = chan->channel < AD3531R_MAX_CHANNELS ? 166 AD3530R_OUTPUT_OPERATING_MODE_0 : 167 AD3530R_OUTPUT_OPERATING_MODE_1; 168 pdmode = powerdown ? st->chan[chan->channel].powerdown_mode : 0; 169 mask = chan->channel < AD3531R_MAX_CHANNELS ? 170 AD3530R_OP_MODE_CHAN_MSK(chan->channel) : 171 AD3530R_OP_MODE_CHAN_MSK(chan->channel - 4); 172 val = field_prep(mask, pdmode); 173 174 ret = regmap_update_bits(st->regmap, reg, mask, val); 175 if (ret) 176 return ret; 177 178 st->chan[chan->channel].powerdown = powerdown; 179 180 return len; 181 } 182 183 static int ad3530r_trigger_hw_ldac(struct gpio_desc *ldac_gpio) 184 { 185 gpiod_set_value_cansleep(ldac_gpio, 1); 186 fsleep(AD3530R_LDAC_PULSE_US); 187 gpiod_set_value_cansleep(ldac_gpio, 0); 188 189 return 0; 190 } 191 192 static int ad3530r_dac_write(struct ad3530r_state *st, unsigned int chan, 193 unsigned int val) 194 { 195 int ret; 196 197 guard(mutex)(&st->lock); 198 st->buf = cpu_to_be16(val); 199 200 ret = regmap_bulk_write(st->regmap, st->chip_info->input_ch_reg(chan), 201 &st->buf, sizeof(st->buf)); 202 if (ret) 203 return ret; 204 205 if (st->ldac_gpio) 206 return ad3530r_trigger_hw_ldac(st->ldac_gpio); 207 208 return regmap_set_bits(st->regmap, st->chip_info->sw_ldac_trig_reg, 209 AD3530R_SLD_TRIG_A); 210 } 211 212 static int ad3530r_read_raw(struct iio_dev *indio_dev, 213 struct iio_chan_spec const *chan, 214 int *val, int *val2, long info) 215 { 216 struct ad3530r_state *st = iio_priv(indio_dev); 217 int ret; 218 219 guard(mutex)(&st->lock); 220 switch (info) { 221 case IIO_CHAN_INFO_RAW: 222 ret = regmap_bulk_read(st->regmap, 223 st->chip_info->input_ch_reg(chan->channel), 224 &st->buf, sizeof(st->buf)); 225 if (ret) 226 return ret; 227 228 *val = FIELD_GET(AD3530R_REG_VAL_MASK, be16_to_cpu(st->buf)); 229 230 return IIO_VAL_INT; 231 case IIO_CHAN_INFO_SCALE: 232 *val = st->vref_mV; 233 *val2 = 16; 234 235 return IIO_VAL_FRACTIONAL_LOG2; 236 default: 237 return -EINVAL; 238 } 239 } 240 241 static int ad3530r_write_raw(struct iio_dev *indio_dev, 242 struct iio_chan_spec const *chan, 243 int val, int val2, long info) 244 { 245 struct ad3530r_state *st = iio_priv(indio_dev); 246 247 switch (info) { 248 case IIO_CHAN_INFO_RAW: 249 if (val < 0 || val > AD3530R_DAC_MAX_VAL) 250 return -EINVAL; 251 252 return ad3530r_dac_write(st, chan->channel, val); 253 default: 254 return -EINVAL; 255 } 256 } 257 258 static int ad3530r_reg_access(struct iio_dev *indio_dev, unsigned int reg, 259 unsigned int writeval, unsigned int *readval) 260 { 261 struct ad3530r_state *st = iio_priv(indio_dev); 262 263 if (readval) 264 return regmap_read(st->regmap, reg, readval); 265 266 return regmap_write(st->regmap, reg, writeval); 267 } 268 269 static const struct iio_chan_spec_ext_info ad3530r_ext_info[] = { 270 { 271 .name = "powerdown", 272 .shared = IIO_SEPARATE, 273 .read = ad3530r_get_dac_powerdown, 274 .write = ad3530r_set_dac_powerdown, 275 }, 276 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad3530r_powerdown_mode_enum), 277 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, 278 &ad3530r_powerdown_mode_enum), 279 { } 280 }; 281 282 #define AD3530R_CHAN(_chan) \ 283 { \ 284 .type = IIO_VOLTAGE, \ 285 .indexed = 1, \ 286 .channel = _chan, \ 287 .output = 1, \ 288 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 289 BIT(IIO_CHAN_INFO_SCALE), \ 290 .ext_info = ad3530r_ext_info, \ 291 } 292 293 static const struct iio_chan_spec ad3530r_channels[] = { 294 AD3530R_CHAN(0), 295 AD3530R_CHAN(1), 296 AD3530R_CHAN(2), 297 AD3530R_CHAN(3), 298 AD3530R_CHAN(4), 299 AD3530R_CHAN(5), 300 AD3530R_CHAN(6), 301 AD3530R_CHAN(7), 302 }; 303 304 static const struct iio_chan_spec ad3531r_channels[] = { 305 AD3530R_CHAN(0), 306 AD3530R_CHAN(1), 307 AD3530R_CHAN(2), 308 AD3530R_CHAN(3), 309 }; 310 311 static const struct ad3530r_chip_info ad3530_chip = { 312 .name = "ad3530", 313 .channels = ad3530r_channels, 314 .num_channels = ARRAY_SIZE(ad3530r_channels), 315 .sw_ldac_trig_reg = AD3530R_SW_LDAC_TRIG_A, 316 .input_ch_reg = ad3530r_input_ch_reg, 317 .internal_ref_support = false, 318 }; 319 320 static const struct ad3530r_chip_info ad3530r_chip = { 321 .name = "ad3530r", 322 .channels = ad3530r_channels, 323 .num_channels = ARRAY_SIZE(ad3530r_channels), 324 .sw_ldac_trig_reg = AD3530R_SW_LDAC_TRIG_A, 325 .input_ch_reg = ad3530r_input_ch_reg, 326 .internal_ref_support = true, 327 }; 328 329 static const struct ad3530r_chip_info ad3531_chip = { 330 .name = "ad3531", 331 .channels = ad3531r_channels, 332 .num_channels = ARRAY_SIZE(ad3531r_channels), 333 .sw_ldac_trig_reg = AD3531R_SW_LDAC_TRIG_A, 334 .input_ch_reg = ad3531r_input_ch_reg, 335 .internal_ref_support = false, 336 }; 337 338 static const struct ad3530r_chip_info ad3531r_chip = { 339 .name = "ad3531r", 340 .channels = ad3531r_channels, 341 .num_channels = ARRAY_SIZE(ad3531r_channels), 342 .sw_ldac_trig_reg = AD3531R_SW_LDAC_TRIG_A, 343 .input_ch_reg = ad3531r_input_ch_reg, 344 .internal_ref_support = true, 345 }; 346 347 static int ad3530r_setup(struct ad3530r_state *st, int external_vref_uV) 348 { 349 struct device *dev = regmap_get_device(st->regmap); 350 struct gpio_desc *reset_gpio; 351 int i, ret; 352 u8 range_multiplier, val; 353 354 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 355 if (IS_ERR(reset_gpio)) 356 return dev_err_probe(dev, PTR_ERR(reset_gpio), 357 "Failed to get reset GPIO\n"); 358 359 if (reset_gpio) { 360 /* Perform hardware reset */ 361 fsleep(1 * USEC_PER_MSEC); 362 gpiod_set_value_cansleep(reset_gpio, 0); 363 } else { 364 /* Perform software reset */ 365 ret = regmap_update_bits(st->regmap, AD3530R_INTERFACE_CONFIG_A, 366 AD3530R_SW_RESET, AD3530R_SW_RESET); 367 if (ret) 368 return ret; 369 } 370 371 fsleep(10 * USEC_PER_MSEC); 372 373 range_multiplier = 1; 374 if (device_property_read_bool(dev, "adi,range-double")) { 375 ret = regmap_set_bits(st->regmap, AD3530R_OUTPUT_CONTROL_0, 376 AD3530R_OUTPUT_CONTROL_RANGE); 377 if (ret) 378 return ret; 379 380 range_multiplier = 2; 381 } 382 383 if (external_vref_uV) { 384 st->vref_mV = range_multiplier * external_vref_uV / MILLI; 385 } else { 386 ret = regmap_set_bits(st->regmap, AD3530R_REFERENCE_CONTROL_0, 387 AD3530R_REFERENCE_CONTROL_SEL); 388 if (ret) 389 return ret; 390 391 st->vref_mV = range_multiplier * AD3530R_INTERNAL_VREF_mV; 392 } 393 394 /* Set normal operating mode for all channels */ 395 val = FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(0), AD3530R_NORMAL_OP) | 396 FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(1), AD3530R_NORMAL_OP) | 397 FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(2), AD3530R_NORMAL_OP) | 398 FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(3), AD3530R_NORMAL_OP); 399 400 ret = regmap_write(st->regmap, AD3530R_OUTPUT_OPERATING_MODE_0, val); 401 if (ret) 402 return ret; 403 404 if (st->chip_info->num_channels > 4) { 405 ret = regmap_write(st->regmap, AD3530R_OUTPUT_OPERATING_MODE_1, 406 val); 407 if (ret) 408 return ret; 409 } 410 411 for (i = 0; i < st->chip_info->num_channels; i++) 412 st->chan[i].powerdown_mode = AD3530R_POWERDOWN_32K; 413 414 st->ldac_gpio = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_LOW); 415 if (IS_ERR(st->ldac_gpio)) 416 return dev_err_probe(dev, PTR_ERR(st->ldac_gpio), 417 "Failed to get ldac GPIO\n"); 418 419 return 0; 420 } 421 422 static const struct regmap_config ad3530r_regmap_config = { 423 .reg_bits = 16, 424 .val_bits = 8, 425 .max_register = AD3530R_MAX_REG_ADDR, 426 }; 427 428 static const struct iio_info ad3530r_info = { 429 .read_raw = ad3530r_read_raw, 430 .write_raw = ad3530r_write_raw, 431 .debugfs_reg_access = ad3530r_reg_access, 432 }; 433 434 static int ad3530r_probe(struct spi_device *spi) 435 { 436 static const char * const regulators[] = { "vdd", "iovdd" }; 437 struct device *dev = &spi->dev; 438 struct iio_dev *indio_dev; 439 struct ad3530r_state *st; 440 int ret, external_vref_uV; 441 442 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 443 if (!indio_dev) 444 return -ENOMEM; 445 446 st = iio_priv(indio_dev); 447 448 st->regmap = devm_regmap_init_spi(spi, &ad3530r_regmap_config); 449 if (IS_ERR(st->regmap)) 450 return dev_err_probe(dev, PTR_ERR(st->regmap), 451 "Failed to init regmap"); 452 453 ret = devm_mutex_init(dev, &st->lock); 454 if (ret) 455 return ret; 456 457 st->chip_info = spi_get_device_match_data(spi); 458 if (!st->chip_info) 459 return -ENODEV; 460 461 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators), 462 regulators); 463 if (ret) 464 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 465 466 external_vref_uV = devm_regulator_get_enable_read_voltage(dev, "ref"); 467 if (external_vref_uV < 0 && external_vref_uV != -ENODEV) 468 return external_vref_uV; 469 470 if (external_vref_uV == -ENODEV) 471 external_vref_uV = 0; 472 473 if (!st->chip_info->internal_ref_support && external_vref_uV == 0) 474 return -ENODEV; 475 476 ret = ad3530r_setup(st, external_vref_uV); 477 if (ret) 478 return ret; 479 480 indio_dev->name = st->chip_info->name; 481 indio_dev->info = &ad3530r_info; 482 indio_dev->modes = INDIO_DIRECT_MODE; 483 indio_dev->channels = st->chip_info->channels; 484 indio_dev->num_channels = st->chip_info->num_channels; 485 486 return devm_iio_device_register(&spi->dev, indio_dev); 487 } 488 489 static const struct spi_device_id ad3530r_id[] = { 490 { "ad3530", (kernel_ulong_t)&ad3530_chip }, 491 { "ad3530r", (kernel_ulong_t)&ad3530r_chip }, 492 { "ad3531", (kernel_ulong_t)&ad3531_chip }, 493 { "ad3531r", (kernel_ulong_t)&ad3531r_chip }, 494 { } 495 }; 496 MODULE_DEVICE_TABLE(spi, ad3530r_id); 497 498 static const struct of_device_id ad3530r_of_match[] = { 499 { .compatible = "adi,ad3530", .data = &ad3530_chip }, 500 { .compatible = "adi,ad3530r", .data = &ad3530r_chip }, 501 { .compatible = "adi,ad3531", .data = &ad3531_chip }, 502 { .compatible = "adi,ad3531r", .data = &ad3531r_chip }, 503 { } 504 }; 505 MODULE_DEVICE_TABLE(of, ad3530r_of_match); 506 507 static struct spi_driver ad3530r_driver = { 508 .driver = { 509 .name = "ad3530r", 510 .of_match_table = ad3530r_of_match, 511 }, 512 .probe = ad3530r_probe, 513 .id_table = ad3530r_id, 514 }; 515 module_spi_driver(ad3530r_driver); 516 517 MODULE_AUTHOR("Kim Seer Paller <kimseer.paller@analog.com>"); 518 MODULE_DESCRIPTION("Analog Devices AD3530R and Similar DACs Driver"); 519 MODULE_LICENSE("GPL"); 520