1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD7150 capacitive sensor driver supporting AD7150/1/6 4 * 5 * Copyright 2010-2011 Analog Devices Inc. 6 * Copyright 2021 Jonathan Cameron <Jonathan.Cameron@huawei.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/device.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/i2c.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/slab.h> 18 19 #include <linux/iio/iio.h> 20 #include <linux/iio/sysfs.h> 21 #include <linux/iio/events.h> 22 23 #define AD7150_STATUS_REG 0 24 #define AD7150_STATUS_OUT1 BIT(3) 25 #define AD7150_STATUS_OUT2 BIT(5) 26 #define AD7150_CH1_DATA_HIGH_REG 1 27 #define AD7150_CH2_DATA_HIGH_REG 3 28 #define AD7150_CH1_AVG_HIGH_REG 5 29 #define AD7150_CH2_AVG_HIGH_REG 7 30 #define AD7150_CH1_SENSITIVITY_REG 9 31 #define AD7150_CH1_THR_HOLD_H_REG 9 32 #define AD7150_CH1_TIMEOUT_REG 10 33 #define AD7150_CH_TIMEOUT_RECEDING GENMASK(3, 0) 34 #define AD7150_CH_TIMEOUT_APPROACHING GENMASK(7, 4) 35 #define AD7150_CH1_SETUP_REG 11 36 #define AD7150_CH2_SENSITIVITY_REG 12 37 #define AD7150_CH2_THR_HOLD_H_REG 12 38 #define AD7150_CH2_TIMEOUT_REG 13 39 #define AD7150_CH2_SETUP_REG 14 40 #define AD7150_CFG_REG 15 41 #define AD7150_CFG_FIX BIT(7) 42 #define AD7150_CFG_THRESHTYPE_MSK GENMASK(6, 5) 43 #define AD7150_CFG_TT_NEG 0x0 44 #define AD7150_CFG_TT_POS 0x1 45 #define AD7150_CFG_TT_IN_WINDOW 0x2 46 #define AD7150_CFG_TT_OUT_WINDOW 0x3 47 #define AD7150_PD_TIMER_REG 16 48 #define AD7150_CH1_CAPDAC_REG 17 49 #define AD7150_CH2_CAPDAC_REG 18 50 #define AD7150_SN3_REG 19 51 #define AD7150_SN2_REG 20 52 #define AD7150_SN1_REG 21 53 #define AD7150_SN0_REG 22 54 #define AD7150_ID_REG 23 55 56 enum { 57 AD7150, 58 AD7151, 59 }; 60 61 /** 62 * struct ad7150_chip_info - instance specific chip data 63 * @client: i2c client for this device 64 * @threshold: thresholds for simple capacitance value events 65 * @thresh_sensitivity: threshold for simple capacitance offset 66 * from 'average' value. 67 * @thresh_timeout: a timeout, in samples from the moment an 68 * adaptive threshold event occurs to when the average 69 * value jumps to current value. Note made up of two fields, 70 * 3:0 are for timeout receding - applies if below lower threshold 71 * 7:4 are for timeout approaching - applies if above upper threshold 72 * @state_lock: ensure consistent state of this structure wrt the 73 * hardware. 74 * @interrupts: one or two interrupt numbers depending on device type. 75 * @int_enabled: is a given interrupt currently enabled. 76 * @type: threshold type 77 * @dir: threshold direction 78 */ 79 struct ad7150_chip_info { 80 struct i2c_client *client; 81 u16 threshold[2][2]; 82 u8 thresh_sensitivity[2][2]; 83 u8 thresh_timeout[2][2]; 84 struct mutex state_lock; 85 int interrupts[2]; 86 bool int_enabled[2]; 87 enum iio_event_type type; 88 enum iio_event_direction dir; 89 }; 90 91 static const u8 ad7150_addresses[][6] = { 92 { AD7150_CH1_DATA_HIGH_REG, AD7150_CH1_AVG_HIGH_REG, 93 AD7150_CH1_SETUP_REG, AD7150_CH1_THR_HOLD_H_REG, 94 AD7150_CH1_SENSITIVITY_REG, AD7150_CH1_TIMEOUT_REG }, 95 { AD7150_CH2_DATA_HIGH_REG, AD7150_CH2_AVG_HIGH_REG, 96 AD7150_CH2_SETUP_REG, AD7150_CH2_THR_HOLD_H_REG, 97 AD7150_CH2_SENSITIVITY_REG, AD7150_CH2_TIMEOUT_REG }, 98 }; 99 100 static int ad7150_read_raw(struct iio_dev *indio_dev, 101 struct iio_chan_spec const *chan, 102 int *val, 103 int *val2, 104 long mask) 105 { 106 struct ad7150_chip_info *chip = iio_priv(indio_dev); 107 int channel = chan->channel; 108 int ret; 109 110 switch (mask) { 111 case IIO_CHAN_INFO_RAW: 112 ret = i2c_smbus_read_word_swapped(chip->client, 113 ad7150_addresses[channel][0]); 114 if (ret < 0) 115 return ret; 116 *val = ret >> 4; 117 118 return IIO_VAL_INT; 119 case IIO_CHAN_INFO_AVERAGE_RAW: 120 ret = i2c_smbus_read_word_swapped(chip->client, 121 ad7150_addresses[channel][1]); 122 if (ret < 0) 123 return ret; 124 *val = ret; 125 126 return IIO_VAL_INT; 127 case IIO_CHAN_INFO_SCALE: 128 /* 129 * Base units for capacitance are nano farads and the value 130 * calculated from the datasheet formula is in picofarad 131 * so multiply by 1000 132 */ 133 *val = 1000; 134 *val2 = 40944 >> 4; /* To match shift in _RAW */ 135 return IIO_VAL_FRACTIONAL; 136 case IIO_CHAN_INFO_OFFSET: 137 *val = -(12288 >> 4); /* To match shift in _RAW */ 138 return IIO_VAL_INT; 139 case IIO_CHAN_INFO_SAMP_FREQ: 140 /* Strangely same for both 1 and 2 chan parts */ 141 *val = 100; 142 return IIO_VAL_INT; 143 default: 144 return -EINVAL; 145 } 146 } 147 148 static int ad7150_read_event_config(struct iio_dev *indio_dev, 149 const struct iio_chan_spec *chan, 150 enum iio_event_type type, 151 enum iio_event_direction dir) 152 { 153 struct ad7150_chip_info *chip = iio_priv(indio_dev); 154 u8 threshtype; 155 bool thrfixed; 156 int ret; 157 158 ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG); 159 if (ret < 0) 160 return ret; 161 162 threshtype = FIELD_GET(AD7150_CFG_THRESHTYPE_MSK, ret); 163 164 /*check if threshold mode is fixed or adaptive*/ 165 thrfixed = FIELD_GET(AD7150_CFG_FIX, ret); 166 167 switch (type) { 168 case IIO_EV_TYPE_THRESH_ADAPTIVE: 169 if (dir == IIO_EV_DIR_RISING) 170 return !thrfixed && (threshtype == AD7150_CFG_TT_POS); 171 return !thrfixed && (threshtype == AD7150_CFG_TT_NEG); 172 case IIO_EV_TYPE_THRESH: 173 if (dir == IIO_EV_DIR_RISING) 174 return thrfixed && (threshtype == AD7150_CFG_TT_POS); 175 return thrfixed && (threshtype == AD7150_CFG_TT_NEG); 176 default: 177 break; 178 } 179 return -EINVAL; 180 } 181 182 /* state_lock should be held to ensure consistent state */ 183 static int ad7150_write_event_params(struct iio_dev *indio_dev, 184 unsigned int chan, 185 enum iio_event_type type, 186 enum iio_event_direction dir) 187 { 188 struct ad7150_chip_info *chip = iio_priv(indio_dev); 189 int rising = (dir == IIO_EV_DIR_RISING); 190 191 /* Only update value live, if parameter is in use */ 192 if ((type != chip->type) || (dir != chip->dir)) 193 return 0; 194 195 switch (type) { 196 /* Note completely different from the adaptive versions */ 197 case IIO_EV_TYPE_THRESH: { 198 u16 value = chip->threshold[rising][chan]; 199 return i2c_smbus_write_word_swapped(chip->client, 200 ad7150_addresses[chan][3], 201 value); 202 } 203 case IIO_EV_TYPE_THRESH_ADAPTIVE: { 204 int ret; 205 u8 sens, timeout; 206 207 sens = chip->thresh_sensitivity[rising][chan]; 208 ret = i2c_smbus_write_byte_data(chip->client, 209 ad7150_addresses[chan][4], 210 sens); 211 if (ret) 212 return ret; 213 214 /* 215 * Single timeout register contains timeouts for both 216 * directions. 217 */ 218 timeout = FIELD_PREP(AD7150_CH_TIMEOUT_APPROACHING, 219 chip->thresh_timeout[1][chan]); 220 timeout |= FIELD_PREP(AD7150_CH_TIMEOUT_RECEDING, 221 chip->thresh_timeout[0][chan]); 222 return i2c_smbus_write_byte_data(chip->client, 223 ad7150_addresses[chan][5], 224 timeout); 225 } 226 default: 227 return -EINVAL; 228 } 229 } 230 231 static int ad7150_write_event_config(struct iio_dev *indio_dev, 232 const struct iio_chan_spec *chan, 233 enum iio_event_type type, 234 enum iio_event_direction dir, bool state) 235 { 236 struct ad7150_chip_info *chip = iio_priv(indio_dev); 237 int ret = 0; 238 239 /* 240 * There is only a single shared control and no on chip 241 * interrupt disables for the two interrupt lines. 242 * So, enabling will switch the events configured to enable 243 * whatever was most recently requested and if necessary enable_irq() 244 * the interrupt and any disable will disable_irq() for that 245 * channels interrupt. 246 */ 247 if (!state) { 248 if ((chip->int_enabled[chan->channel]) && 249 (type == chip->type) && (dir == chip->dir)) { 250 disable_irq(chip->interrupts[chan->channel]); 251 chip->int_enabled[chan->channel] = false; 252 } 253 return 0; 254 } 255 256 mutex_lock(&chip->state_lock); 257 if ((type != chip->type) || (dir != chip->dir)) { 258 int rising = (dir == IIO_EV_DIR_RISING); 259 u8 thresh_type, cfg, fixed; 260 261 /* 262 * Need to temporarily disable both interrupts if 263 * enabled - this is to avoid races around changing 264 * config and thresholds. 265 * Note enable/disable_irq() are reference counted so 266 * no need to check if already enabled. 267 */ 268 disable_irq(chip->interrupts[0]); 269 disable_irq(chip->interrupts[1]); 270 271 ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG); 272 if (ret < 0) 273 goto error_ret; 274 275 cfg = ret & ~(AD7150_CFG_THRESHTYPE_MSK | AD7150_CFG_FIX); 276 277 if (type == IIO_EV_TYPE_THRESH_ADAPTIVE) 278 fixed = 0; 279 else 280 fixed = 1; 281 282 if (rising) 283 thresh_type = AD7150_CFG_TT_POS; 284 else 285 thresh_type = AD7150_CFG_TT_NEG; 286 287 cfg |= FIELD_PREP(AD7150_CFG_FIX, fixed) | 288 FIELD_PREP(AD7150_CFG_THRESHTYPE_MSK, thresh_type); 289 290 ret = i2c_smbus_write_byte_data(chip->client, AD7150_CFG_REG, 291 cfg); 292 if (ret < 0) 293 goto error_ret; 294 295 /* 296 * There is a potential race condition here, but not easy 297 * to close given we can't disable the interrupt at the 298 * chip side of things. Rely on the status bit. 299 */ 300 chip->type = type; 301 chip->dir = dir; 302 303 /* update control attributes */ 304 ret = ad7150_write_event_params(indio_dev, chan->channel, type, 305 dir); 306 if (ret) 307 goto error_ret; 308 /* re-enable any IRQs we disabled whilst changing mode */ 309 enable_irq(chip->interrupts[0]); 310 enable_irq(chip->interrupts[1]); 311 } 312 if (!chip->int_enabled[chan->channel]) { 313 enable_irq(chip->interrupts[chan->channel]); 314 chip->int_enabled[chan->channel] = true; 315 } 316 317 error_ret: 318 mutex_unlock(&chip->state_lock); 319 320 return ret; 321 } 322 323 static int ad7150_read_event_value(struct iio_dev *indio_dev, 324 const struct iio_chan_spec *chan, 325 enum iio_event_type type, 326 enum iio_event_direction dir, 327 enum iio_event_info info, 328 int *val, int *val2) 329 { 330 struct ad7150_chip_info *chip = iio_priv(indio_dev); 331 int rising = (dir == IIO_EV_DIR_RISING); 332 333 /* Complex register sharing going on here */ 334 switch (info) { 335 case IIO_EV_INFO_VALUE: 336 switch (type) { 337 case IIO_EV_TYPE_THRESH_ADAPTIVE: 338 *val = chip->thresh_sensitivity[rising][chan->channel]; 339 return IIO_VAL_INT; 340 case IIO_EV_TYPE_THRESH: 341 *val = chip->threshold[rising][chan->channel]; 342 return IIO_VAL_INT; 343 default: 344 return -EINVAL; 345 } 346 case IIO_EV_INFO_TIMEOUT: 347 *val = 0; 348 *val2 = chip->thresh_timeout[rising][chan->channel] * 10000; 349 return IIO_VAL_INT_PLUS_MICRO; 350 default: 351 return -EINVAL; 352 } 353 } 354 355 static int ad7150_write_event_value(struct iio_dev *indio_dev, 356 const struct iio_chan_spec *chan, 357 enum iio_event_type type, 358 enum iio_event_direction dir, 359 enum iio_event_info info, 360 int val, int val2) 361 { 362 int ret; 363 struct ad7150_chip_info *chip = iio_priv(indio_dev); 364 int rising = (dir == IIO_EV_DIR_RISING); 365 366 mutex_lock(&chip->state_lock); 367 switch (info) { 368 case IIO_EV_INFO_VALUE: 369 switch (type) { 370 case IIO_EV_TYPE_THRESH_ADAPTIVE: 371 chip->thresh_sensitivity[rising][chan->channel] = val; 372 break; 373 case IIO_EV_TYPE_THRESH: 374 chip->threshold[rising][chan->channel] = val; 375 break; 376 default: 377 ret = -EINVAL; 378 goto error_ret; 379 } 380 break; 381 case IIO_EV_INFO_TIMEOUT: { 382 /* 383 * Raw timeout is in cycles of 10 msecs as long as both 384 * channels are enabled. 385 * In terms of INT_PLUS_MICRO, that is in units of 10,000 386 */ 387 int timeout = val2 / 10000; 388 389 if (val != 0 || timeout < 0 || timeout > 15 || val2 % 10000) { 390 ret = -EINVAL; 391 goto error_ret; 392 } 393 394 chip->thresh_timeout[rising][chan->channel] = timeout; 395 break; 396 } 397 default: 398 ret = -EINVAL; 399 goto error_ret; 400 } 401 402 /* write back if active */ 403 ret = ad7150_write_event_params(indio_dev, chan->channel, type, dir); 404 405 error_ret: 406 mutex_unlock(&chip->state_lock); 407 return ret; 408 } 409 410 static const struct iio_event_spec ad7150_events[] = { 411 { 412 .type = IIO_EV_TYPE_THRESH, 413 .dir = IIO_EV_DIR_RISING, 414 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 415 BIT(IIO_EV_INFO_ENABLE), 416 }, { 417 .type = IIO_EV_TYPE_THRESH, 418 .dir = IIO_EV_DIR_FALLING, 419 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 420 BIT(IIO_EV_INFO_ENABLE), 421 }, { 422 .type = IIO_EV_TYPE_THRESH_ADAPTIVE, 423 .dir = IIO_EV_DIR_RISING, 424 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 425 BIT(IIO_EV_INFO_ENABLE) | 426 BIT(IIO_EV_INFO_TIMEOUT), 427 }, { 428 .type = IIO_EV_TYPE_THRESH_ADAPTIVE, 429 .dir = IIO_EV_DIR_FALLING, 430 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 431 BIT(IIO_EV_INFO_ENABLE) | 432 BIT(IIO_EV_INFO_TIMEOUT), 433 }, 434 }; 435 436 #define AD7150_CAPACITANCE_CHAN(_chan) { \ 437 .type = IIO_CAPACITANCE, \ 438 .indexed = 1, \ 439 .channel = _chan, \ 440 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 441 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ 442 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 443 BIT(IIO_CHAN_INFO_OFFSET), \ 444 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 445 .event_spec = ad7150_events, \ 446 .num_event_specs = ARRAY_SIZE(ad7150_events), \ 447 } 448 449 #define AD7150_CAPACITANCE_CHAN_NO_IRQ(_chan) { \ 450 .type = IIO_CAPACITANCE, \ 451 .indexed = 1, \ 452 .channel = _chan, \ 453 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 454 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ 455 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 456 BIT(IIO_CHAN_INFO_OFFSET), \ 457 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 458 } 459 460 static const struct iio_chan_spec ad7150_channels[] = { 461 AD7150_CAPACITANCE_CHAN(0), 462 AD7150_CAPACITANCE_CHAN(1), 463 }; 464 465 static const struct iio_chan_spec ad7150_channels_no_irq[] = { 466 AD7150_CAPACITANCE_CHAN_NO_IRQ(0), 467 AD7150_CAPACITANCE_CHAN_NO_IRQ(1), 468 }; 469 470 static const struct iio_chan_spec ad7151_channels[] = { 471 AD7150_CAPACITANCE_CHAN(0), 472 }; 473 474 static const struct iio_chan_spec ad7151_channels_no_irq[] = { 475 AD7150_CAPACITANCE_CHAN_NO_IRQ(0), 476 }; 477 478 static irqreturn_t __ad7150_event_handler(void *private, u8 status_mask, 479 int channel) 480 { 481 struct iio_dev *indio_dev = private; 482 struct ad7150_chip_info *chip = iio_priv(indio_dev); 483 s64 timestamp = iio_get_time_ns(indio_dev); 484 int int_status; 485 486 int_status = i2c_smbus_read_byte_data(chip->client, AD7150_STATUS_REG); 487 if (int_status < 0) 488 return IRQ_HANDLED; 489 490 if (!(int_status & status_mask)) 491 return IRQ_HANDLED; 492 493 iio_push_event(indio_dev, 494 IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, channel, 495 chip->type, chip->dir), 496 timestamp); 497 498 return IRQ_HANDLED; 499 } 500 501 static irqreturn_t ad7150_event_handler_ch1(int irq, void *private) 502 { 503 return __ad7150_event_handler(private, AD7150_STATUS_OUT1, 0); 504 } 505 506 static irqreturn_t ad7150_event_handler_ch2(int irq, void *private) 507 { 508 return __ad7150_event_handler(private, AD7150_STATUS_OUT2, 1); 509 } 510 511 static IIO_CONST_ATTR(in_capacitance_thresh_adaptive_timeout_available, 512 "[0 0.01 0.15]"); 513 514 static struct attribute *ad7150_event_attributes[] = { 515 &iio_const_attr_in_capacitance_thresh_adaptive_timeout_available 516 .dev_attr.attr, 517 NULL, 518 }; 519 520 static const struct attribute_group ad7150_event_attribute_group = { 521 .attrs = ad7150_event_attributes, 522 .name = "events", 523 }; 524 525 static const struct iio_info ad7150_info = { 526 .event_attrs = &ad7150_event_attribute_group, 527 .read_raw = &ad7150_read_raw, 528 .read_event_config = &ad7150_read_event_config, 529 .write_event_config = &ad7150_write_event_config, 530 .read_event_value = &ad7150_read_event_value, 531 .write_event_value = &ad7150_write_event_value, 532 }; 533 534 static const struct iio_info ad7150_info_no_irq = { 535 .read_raw = &ad7150_read_raw, 536 }; 537 538 static int ad7150_probe(struct i2c_client *client) 539 { 540 const struct i2c_device_id *id = i2c_client_get_device_id(client); 541 struct ad7150_chip_info *chip; 542 struct iio_dev *indio_dev; 543 bool use_irq = true; 544 int ret; 545 546 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip)); 547 if (!indio_dev) 548 return -ENOMEM; 549 550 chip = iio_priv(indio_dev); 551 mutex_init(&chip->state_lock); 552 chip->client = client; 553 554 indio_dev->name = id->name; 555 556 indio_dev->modes = INDIO_DIRECT_MODE; 557 558 ret = devm_regulator_get_enable(&client->dev, "vdd"); 559 if (ret) 560 return ret; 561 562 chip->interrupts[0] = fwnode_irq_get(dev_fwnode(&client->dev), 0); 563 if (chip->interrupts[0] < 0) 564 use_irq = false; 565 else if (id->driver_data == AD7150) { 566 chip->interrupts[1] = fwnode_irq_get(dev_fwnode(&client->dev), 1); 567 if (chip->interrupts[1] < 0) 568 use_irq = false; 569 } 570 if (use_irq) { 571 irq_set_status_flags(chip->interrupts[0], IRQ_NOAUTOEN); 572 ret = devm_request_threaded_irq(&client->dev, 573 chip->interrupts[0], 574 NULL, 575 &ad7150_event_handler_ch1, 576 IRQF_TRIGGER_RISING | 577 IRQF_ONESHOT, 578 "ad7150_irq1", 579 indio_dev); 580 if (ret) 581 return ret; 582 583 indio_dev->info = &ad7150_info; 584 switch (id->driver_data) { 585 case AD7150: 586 indio_dev->channels = ad7150_channels; 587 indio_dev->num_channels = ARRAY_SIZE(ad7150_channels); 588 irq_set_status_flags(chip->interrupts[1], IRQ_NOAUTOEN); 589 ret = devm_request_threaded_irq(&client->dev, 590 chip->interrupts[1], 591 NULL, 592 &ad7150_event_handler_ch2, 593 IRQF_TRIGGER_RISING | 594 IRQF_ONESHOT, 595 "ad7150_irq2", 596 indio_dev); 597 if (ret) 598 return ret; 599 break; 600 case AD7151: 601 indio_dev->channels = ad7151_channels; 602 indio_dev->num_channels = ARRAY_SIZE(ad7151_channels); 603 break; 604 default: 605 return -EINVAL; 606 } 607 608 } else { 609 indio_dev->info = &ad7150_info_no_irq; 610 switch (id->driver_data) { 611 case AD7150: 612 indio_dev->channels = ad7150_channels_no_irq; 613 indio_dev->num_channels = 614 ARRAY_SIZE(ad7150_channels_no_irq); 615 break; 616 case AD7151: 617 indio_dev->channels = ad7151_channels_no_irq; 618 indio_dev->num_channels = 619 ARRAY_SIZE(ad7151_channels_no_irq); 620 break; 621 default: 622 return -EINVAL; 623 } 624 } 625 626 return devm_iio_device_register(indio_dev->dev.parent, indio_dev); 627 } 628 629 static const struct i2c_device_id ad7150_id[] = { 630 { .name = "ad7150", .driver_data = AD7150 }, 631 { .name = "ad7151", .driver_data = AD7151 }, 632 { .name = "ad7156", .driver_data = AD7150 }, 633 { } 634 }; 635 636 MODULE_DEVICE_TABLE(i2c, ad7150_id); 637 638 static const struct of_device_id ad7150_of_match[] = { 639 { "adi,ad7150" }, 640 { "adi,ad7151" }, 641 { "adi,ad7156" }, 642 { } 643 }; 644 static struct i2c_driver ad7150_driver = { 645 .driver = { 646 .name = "ad7150", 647 .of_match_table = ad7150_of_match, 648 }, 649 .probe = ad7150_probe, 650 .id_table = ad7150_id, 651 }; 652 module_i2c_driver(ad7150_driver); 653 654 MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>"); 655 MODULE_DESCRIPTION("Analog Devices AD7150/1/6 capacitive sensor driver"); 656 MODULE_LICENSE("GPL v2"); 657