1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2021 Analog Devices, Inc. 4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com> 5 */ 6 7 #include <asm/unaligned.h> 8 #include <linux/bitfield.h> 9 #include <linux/crc8.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/iio/buffer.h> 14 #include <linux/iio/iio.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/trigger.h> 17 #include <linux/iio/trigger_consumer.h> 18 #include <linux/iio/triggered_buffer.h> 19 #include <linux/interrupt.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/spi/spi.h> 25 26 #include <dt-bindings/iio/addac/adi,ad74413r.h> 27 28 #define AD74413R_CRC_POLYNOMIAL 0x7 29 DECLARE_CRC8_TABLE(ad74413r_crc8_table); 30 31 #define AD74413R_CHANNEL_MAX 4 32 33 #define AD74413R_FRAME_SIZE 4 34 35 struct ad74413r_chip_info { 36 const char *name; 37 bool hart_support; 38 }; 39 40 struct ad74413r_channel_config { 41 u32 func; 42 u32 drive_strength; 43 bool gpo_comparator; 44 bool initialized; 45 }; 46 47 struct ad74413r_channels { 48 struct iio_chan_spec *channels; 49 unsigned int num_channels; 50 }; 51 52 struct ad74413r_state { 53 struct ad74413r_channel_config channel_configs[AD74413R_CHANNEL_MAX]; 54 unsigned int gpo_gpio_offsets[AD74413R_CHANNEL_MAX]; 55 unsigned int comp_gpio_offsets[AD74413R_CHANNEL_MAX]; 56 struct gpio_chip gpo_gpiochip; 57 struct gpio_chip comp_gpiochip; 58 struct completion adc_data_completion; 59 unsigned int num_gpo_gpios; 60 unsigned int num_comparator_gpios; 61 u32 sense_resistor_ohms; 62 63 /* 64 * Synchronize consecutive operations when doing a one-shot 65 * conversion and when updating the ADC samples SPI message. 66 */ 67 struct mutex lock; 68 69 const struct ad74413r_chip_info *chip_info; 70 struct spi_device *spi; 71 struct regulator *refin_reg; 72 struct regmap *regmap; 73 struct device *dev; 74 struct iio_trigger *trig; 75 struct gpio_desc *reset_gpio; 76 77 size_t adc_active_channels; 78 struct spi_message adc_samples_msg; 79 struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1]; 80 81 /* 82 * DMA (thus cache coherency maintenance) may require the 83 * transfer buffers to live in their own cache lines. 84 */ 85 struct { 86 u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; 87 s64 timestamp; 88 } adc_samples_buf __aligned(IIO_DMA_MINALIGN); 89 90 u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; 91 u8 reg_tx_buf[AD74413R_FRAME_SIZE]; 92 u8 reg_rx_buf[AD74413R_FRAME_SIZE]; 93 }; 94 95 #define AD74413R_REG_NOP 0x00 96 97 #define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x)) 98 #define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0) 99 100 #define AD74413R_REG_ADC_CONFIG_X(x) (0x05 + (x)) 101 #define AD74413R_ADC_CONFIG_RANGE_MASK GENMASK(7, 5) 102 #define AD74413R_ADC_CONFIG_REJECTION_MASK GENMASK(4, 3) 103 #define AD74413R_ADC_CONFIG_CH_200K_TO_GND BIT(2) 104 #define AD74413R_ADC_RANGE_10V 0b000 105 #define AD74413R_ADC_RANGE_2P5V_EXT_POW 0b001 106 #define AD74413R_ADC_RANGE_2P5V_INT_POW 0b010 107 #define AD74413R_ADC_RANGE_5V_BI_DIR 0b011 108 #define AD74413R_ADC_REJECTION_50_60 0b00 109 #define AD74413R_ADC_REJECTION_NONE 0b01 110 #define AD74413R_ADC_REJECTION_50_60_HART 0b10 111 #define AD74413R_ADC_REJECTION_HART 0b11 112 113 #define AD74413R_REG_DIN_CONFIG_X(x) (0x09 + (x)) 114 #define AD74413R_DIN_DEBOUNCE_MASK GENMASK(4, 0) 115 #define AD74413R_DIN_DEBOUNCE_LEN BIT(5) 116 #define AD74413R_DIN_SINK_MASK GENMASK(9, 6) 117 118 #define AD74413R_REG_DAC_CODE_X(x) (0x16 + (x)) 119 #define AD74413R_DAC_CODE_MAX GENMASK(12, 0) 120 #define AD74413R_DAC_VOLTAGE_MAX 11000 121 122 #define AD74413R_REG_GPO_PAR_DATA 0x0d 123 #define AD74413R_REG_GPO_CONFIG_X(x) (0x0e + (x)) 124 #define AD74413R_GPO_CONFIG_DATA_MASK BIT(3) 125 #define AD74413R_GPO_CONFIG_SELECT_MASK GENMASK(2, 0) 126 #define AD74413R_GPO_CONFIG_100K_PULL_DOWN 0b000 127 #define AD74413R_GPO_CONFIG_LOGIC 0b001 128 #define AD74413R_GPO_CONFIG_LOGIC_PARALLEL 0b010 129 #define AD74413R_GPO_CONFIG_COMPARATOR 0b011 130 #define AD74413R_GPO_CONFIG_HIGH_IMPEDANCE 0b100 131 132 #define AD74413R_REG_ADC_CONV_CTRL 0x23 133 #define AD74413R_CONV_SEQ_MASK GENMASK(9, 8) 134 #define AD74413R_CONV_SEQ_ON 0b00 135 #define AD74413R_CONV_SEQ_SINGLE 0b01 136 #define AD74413R_CONV_SEQ_CONTINUOUS 0b10 137 #define AD74413R_CONV_SEQ_OFF 0b11 138 #define AD74413R_CH_EN_MASK(x) BIT(x) 139 140 #define AD74413R_REG_DIN_COMP_OUT 0x25 141 142 #define AD74413R_REG_ADC_RESULT_X(x) (0x26 + (x)) 143 #define AD74413R_ADC_RESULT_MAX GENMASK(15, 0) 144 145 #define AD74413R_REG_READ_SELECT 0x41 146 147 #define AD74413R_REG_CMD_KEY 0x44 148 #define AD74413R_CMD_KEY_LDAC 0x953a 149 #define AD74413R_CMD_KEY_RESET1 0x15fa 150 #define AD74413R_CMD_KEY_RESET2 0xaf51 151 152 static const int ad74413r_adc_sampling_rates[] = { 153 20, 4800, 154 }; 155 156 static const int ad74413r_adc_sampling_rates_hart[] = { 157 10, 20, 1200, 4800, 158 }; 159 160 static int ad74413r_crc(u8 *buf) 161 { 162 return crc8(ad74413r_crc8_table, buf, 3, 0); 163 } 164 165 static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf) 166 { 167 buf[0] = reg; 168 put_unaligned_be16(val, &buf[1]); 169 buf[3] = ad74413r_crc(buf); 170 } 171 172 static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val) 173 { 174 struct ad74413r_state *st = context; 175 176 ad74413r_format_reg_write(reg, val, st->reg_tx_buf); 177 178 return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE); 179 } 180 181 static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf) 182 { 183 u8 expected_crc = ad74413r_crc(buf); 184 185 if (buf[3] != expected_crc) { 186 dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n", 187 buf[3], buf[0], buf[1], buf[2]); 188 return -EINVAL; 189 } 190 191 return 0; 192 } 193 194 static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val) 195 { 196 struct ad74413r_state *st = context; 197 struct spi_transfer reg_read_xfer[] = { 198 { 199 .tx_buf = st->reg_tx_buf, 200 .len = AD74413R_FRAME_SIZE, 201 .cs_change = 1, 202 }, 203 { 204 .rx_buf = st->reg_rx_buf, 205 .len = AD74413R_FRAME_SIZE, 206 }, 207 }; 208 int ret; 209 210 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, reg, 211 st->reg_tx_buf); 212 213 ret = spi_sync_transfer(st->spi, reg_read_xfer, 214 ARRAY_SIZE(reg_read_xfer)); 215 if (ret) 216 return ret; 217 218 ret = ad74413r_crc_check(st, st->reg_rx_buf); 219 if (ret) 220 return ret; 221 222 *val = get_unaligned_be16(&st->reg_rx_buf[1]); 223 224 return 0; 225 } 226 227 static const struct regmap_config ad74413r_regmap_config = { 228 .reg_bits = 8, 229 .val_bits = 16, 230 .reg_read = ad74413r_reg_read, 231 .reg_write = ad74413r_reg_write, 232 }; 233 234 static int ad74413r_set_gpo_config(struct ad74413r_state *st, 235 unsigned int offset, u8 mode) 236 { 237 return regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(offset), 238 AD74413R_GPO_CONFIG_SELECT_MASK, mode); 239 } 240 241 static const unsigned int ad74413r_debounce_map[AD74413R_DIN_DEBOUNCE_LEN] = { 242 0, 13, 18, 24, 32, 42, 56, 75, 243 100, 130, 180, 240, 320, 420, 560, 750, 244 1000, 1300, 1800, 2400, 3200, 4200, 5600, 7500, 245 10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000, 246 }; 247 248 static int ad74413r_set_comp_debounce(struct ad74413r_state *st, 249 unsigned int offset, 250 unsigned int debounce) 251 { 252 unsigned int val = AD74413R_DIN_DEBOUNCE_LEN - 1; 253 unsigned int i; 254 255 for (i = 0; i < AD74413R_DIN_DEBOUNCE_LEN; i++) 256 if (debounce <= ad74413r_debounce_map[i]) { 257 val = i; 258 break; 259 } 260 261 return regmap_update_bits(st->regmap, 262 AD74413R_REG_DIN_CONFIG_X(offset), 263 AD74413R_DIN_DEBOUNCE_MASK, 264 val); 265 } 266 267 static int ad74413r_set_comp_drive_strength(struct ad74413r_state *st, 268 unsigned int offset, 269 unsigned int strength) 270 { 271 strength = min(strength, 1800U); 272 273 return regmap_update_bits(st->regmap, AD74413R_REG_DIN_CONFIG_X(offset), 274 AD74413R_DIN_SINK_MASK, 275 FIELD_PREP(AD74413R_DIN_SINK_MASK, strength / 120)); 276 } 277 278 279 static void ad74413r_gpio_set(struct gpio_chip *chip, 280 unsigned int offset, int val) 281 { 282 struct ad74413r_state *st = gpiochip_get_data(chip); 283 unsigned int real_offset = st->gpo_gpio_offsets[offset]; 284 int ret; 285 286 ret = ad74413r_set_gpo_config(st, real_offset, 287 AD74413R_GPO_CONFIG_LOGIC); 288 if (ret) 289 return; 290 291 regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(real_offset), 292 AD74413R_GPO_CONFIG_DATA_MASK, 293 val ? AD74413R_GPO_CONFIG_DATA_MASK : 0); 294 } 295 296 static void ad74413r_gpio_set_multiple(struct gpio_chip *chip, 297 unsigned long *mask, 298 unsigned long *bits) 299 { 300 struct ad74413r_state *st = gpiochip_get_data(chip); 301 unsigned long real_mask = 0; 302 unsigned long real_bits = 0; 303 unsigned int offset; 304 int ret; 305 306 for_each_set_bit(offset, mask, chip->ngpio) { 307 unsigned int real_offset = st->gpo_gpio_offsets[offset]; 308 309 ret = ad74413r_set_gpo_config(st, real_offset, 310 AD74413R_GPO_CONFIG_LOGIC_PARALLEL); 311 if (ret) 312 return; 313 314 real_mask |= BIT(real_offset); 315 if (*bits & offset) 316 real_bits |= BIT(real_offset); 317 } 318 319 regmap_update_bits(st->regmap, AD74413R_REG_GPO_PAR_DATA, 320 real_mask, real_bits); 321 } 322 323 static int ad74413r_gpio_get(struct gpio_chip *chip, unsigned int offset) 324 { 325 struct ad74413r_state *st = gpiochip_get_data(chip); 326 unsigned int real_offset = st->comp_gpio_offsets[offset]; 327 unsigned int status; 328 int ret; 329 330 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &status); 331 if (ret) 332 return ret; 333 334 status &= BIT(real_offset); 335 336 return status ? 1 : 0; 337 } 338 339 static int ad74413r_gpio_get_multiple(struct gpio_chip *chip, 340 unsigned long *mask, 341 unsigned long *bits) 342 { 343 struct ad74413r_state *st = gpiochip_get_data(chip); 344 unsigned int offset; 345 unsigned int val; 346 int ret; 347 348 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &val); 349 if (ret) 350 return ret; 351 352 for_each_set_bit(offset, mask, chip->ngpio) { 353 unsigned int real_offset = st->comp_gpio_offsets[offset]; 354 355 __assign_bit(offset, bits, val & BIT(real_offset)); 356 } 357 358 return ret; 359 } 360 361 static int ad74413r_gpio_get_gpo_direction(struct gpio_chip *chip, 362 unsigned int offset) 363 { 364 return GPIO_LINE_DIRECTION_OUT; 365 } 366 367 static int ad74413r_gpio_get_comp_direction(struct gpio_chip *chip, 368 unsigned int offset) 369 { 370 return GPIO_LINE_DIRECTION_IN; 371 } 372 373 static int ad74413r_gpio_set_gpo_config(struct gpio_chip *chip, 374 unsigned int offset, 375 unsigned long config) 376 { 377 struct ad74413r_state *st = gpiochip_get_data(chip); 378 unsigned int real_offset = st->gpo_gpio_offsets[offset]; 379 380 switch (pinconf_to_config_param(config)) { 381 case PIN_CONFIG_BIAS_PULL_DOWN: 382 return ad74413r_set_gpo_config(st, real_offset, 383 AD74413R_GPO_CONFIG_100K_PULL_DOWN); 384 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 385 return ad74413r_set_gpo_config(st, real_offset, 386 AD74413R_GPO_CONFIG_HIGH_IMPEDANCE); 387 default: 388 return -ENOTSUPP; 389 } 390 } 391 392 static int ad74413r_gpio_set_comp_config(struct gpio_chip *chip, 393 unsigned int offset, 394 unsigned long config) 395 { 396 struct ad74413r_state *st = gpiochip_get_data(chip); 397 unsigned int real_offset = st->comp_gpio_offsets[offset]; 398 399 switch (pinconf_to_config_param(config)) { 400 case PIN_CONFIG_INPUT_DEBOUNCE: 401 return ad74413r_set_comp_debounce(st, real_offset, 402 pinconf_to_config_argument(config)); 403 default: 404 return -ENOTSUPP; 405 } 406 } 407 408 static int ad74413r_reset(struct ad74413r_state *st) 409 { 410 int ret; 411 412 if (st->reset_gpio) { 413 gpiod_set_value_cansleep(st->reset_gpio, 1); 414 fsleep(50); 415 gpiod_set_value_cansleep(st->reset_gpio, 0); 416 return 0; 417 } 418 419 ret = regmap_write(st->regmap, AD74413R_REG_CMD_KEY, 420 AD74413R_CMD_KEY_RESET1); 421 if (ret) 422 return ret; 423 424 return regmap_write(st->regmap, AD74413R_REG_CMD_KEY, 425 AD74413R_CMD_KEY_RESET2); 426 } 427 428 static int ad74413r_set_channel_dac_code(struct ad74413r_state *st, 429 unsigned int channel, int dac_code) 430 { 431 struct reg_sequence reg_seq[2] = { 432 { AD74413R_REG_DAC_CODE_X(channel), dac_code }, 433 { AD74413R_REG_CMD_KEY, AD74413R_CMD_KEY_LDAC }, 434 }; 435 436 return regmap_multi_reg_write(st->regmap, reg_seq, 2); 437 } 438 439 static int ad74413r_set_channel_function(struct ad74413r_state *st, 440 unsigned int channel, u8 func) 441 { 442 int ret; 443 444 ret = regmap_update_bits(st->regmap, 445 AD74413R_REG_CH_FUNC_SETUP_X(channel), 446 AD74413R_CH_FUNC_SETUP_MASK, 447 CH_FUNC_HIGH_IMPEDANCE); 448 if (ret) 449 return ret; 450 451 /* Set DAC code to 0 prior to changing channel function */ 452 ret = ad74413r_set_channel_dac_code(st, channel, 0); 453 if (ret) 454 return ret; 455 456 /* Delay required before transition to new desired mode */ 457 usleep_range(130, 150); 458 459 ret = regmap_update_bits(st->regmap, 460 AD74413R_REG_CH_FUNC_SETUP_X(channel), 461 AD74413R_CH_FUNC_SETUP_MASK, func); 462 if (ret) 463 return ret; 464 465 /* Delay required before updating the new DAC code */ 466 usleep_range(150, 170); 467 468 if (func == CH_FUNC_CURRENT_INPUT_LOOP_POWER) 469 ret = regmap_set_bits(st->regmap, 470 AD74413R_REG_ADC_CONFIG_X(channel), 471 AD74413R_ADC_CONFIG_CH_200K_TO_GND); 472 473 return ret; 474 } 475 476 static int ad74413r_set_adc_conv_seq(struct ad74413r_state *st, 477 unsigned int status) 478 { 479 int ret; 480 481 /* 482 * These bits do not clear when a conversion completes. 483 * To enable a subsequent conversion, repeat the write. 484 */ 485 ret = regmap_write_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL, 486 AD74413R_CONV_SEQ_MASK, 487 FIELD_PREP(AD74413R_CONV_SEQ_MASK, status)); 488 if (ret) 489 return ret; 490 491 /* 492 * Wait 100us before starting conversions. 493 */ 494 usleep_range(100, 120); 495 496 return 0; 497 } 498 499 static int ad74413r_set_adc_channel_enable(struct ad74413r_state *st, 500 unsigned int channel, 501 bool status) 502 { 503 return regmap_update_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL, 504 AD74413R_CH_EN_MASK(channel), 505 status ? AD74413R_CH_EN_MASK(channel) : 0); 506 } 507 508 static int ad74413r_get_adc_range(struct ad74413r_state *st, 509 unsigned int channel, 510 unsigned int *val) 511 { 512 int ret; 513 514 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val); 515 if (ret) 516 return ret; 517 518 *val = FIELD_GET(AD74413R_ADC_CONFIG_RANGE_MASK, *val); 519 520 return 0; 521 } 522 523 static int ad74413r_get_adc_rejection(struct ad74413r_state *st, 524 unsigned int channel, 525 unsigned int *val) 526 { 527 int ret; 528 529 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val); 530 if (ret) 531 return ret; 532 533 *val = FIELD_GET(AD74413R_ADC_CONFIG_REJECTION_MASK, *val); 534 535 return 0; 536 } 537 538 static int ad74413r_set_adc_rejection(struct ad74413r_state *st, 539 unsigned int channel, 540 unsigned int val) 541 { 542 return regmap_update_bits(st->regmap, 543 AD74413R_REG_ADC_CONFIG_X(channel), 544 AD74413R_ADC_CONFIG_REJECTION_MASK, 545 FIELD_PREP(AD74413R_ADC_CONFIG_REJECTION_MASK, 546 val)); 547 } 548 549 static int ad74413r_rejection_to_rate(struct ad74413r_state *st, 550 unsigned int rej, int *val) 551 { 552 switch (rej) { 553 case AD74413R_ADC_REJECTION_50_60: 554 *val = 20; 555 return 0; 556 case AD74413R_ADC_REJECTION_NONE: 557 *val = 4800; 558 return 0; 559 case AD74413R_ADC_REJECTION_50_60_HART: 560 *val = 10; 561 return 0; 562 case AD74413R_ADC_REJECTION_HART: 563 *val = 1200; 564 return 0; 565 default: 566 dev_err(st->dev, "ADC rejection invalid\n"); 567 return -EINVAL; 568 } 569 } 570 571 static int ad74413r_rate_to_rejection(struct ad74413r_state *st, 572 int rate, unsigned int *val) 573 { 574 switch (rate) { 575 case 20: 576 *val = AD74413R_ADC_REJECTION_50_60; 577 return 0; 578 case 4800: 579 *val = AD74413R_ADC_REJECTION_NONE; 580 return 0; 581 case 10: 582 *val = AD74413R_ADC_REJECTION_50_60_HART; 583 return 0; 584 case 1200: 585 *val = AD74413R_ADC_REJECTION_HART; 586 return 0; 587 default: 588 dev_err(st->dev, "ADC rate invalid\n"); 589 return -EINVAL; 590 } 591 } 592 593 static int ad74413r_range_to_voltage_range(struct ad74413r_state *st, 594 unsigned int range, int *val) 595 { 596 switch (range) { 597 case AD74413R_ADC_RANGE_10V: 598 *val = 10000; 599 return 0; 600 case AD74413R_ADC_RANGE_2P5V_EXT_POW: 601 case AD74413R_ADC_RANGE_2P5V_INT_POW: 602 *val = 2500; 603 return 0; 604 case AD74413R_ADC_RANGE_5V_BI_DIR: 605 *val = 5000; 606 return 0; 607 default: 608 dev_err(st->dev, "ADC range invalid\n"); 609 return -EINVAL; 610 } 611 } 612 613 static int ad74413r_range_to_voltage_offset(struct ad74413r_state *st, 614 unsigned int range, int *val) 615 { 616 switch (range) { 617 case AD74413R_ADC_RANGE_10V: 618 case AD74413R_ADC_RANGE_2P5V_EXT_POW: 619 *val = 0; 620 return 0; 621 case AD74413R_ADC_RANGE_2P5V_INT_POW: 622 case AD74413R_ADC_RANGE_5V_BI_DIR: 623 *val = -2500; 624 return 0; 625 default: 626 dev_err(st->dev, "ADC range invalid\n"); 627 return -EINVAL; 628 } 629 } 630 631 static int ad74413r_range_to_voltage_offset_raw(struct ad74413r_state *st, 632 unsigned int range, int *val) 633 { 634 switch (range) { 635 case AD74413R_ADC_RANGE_10V: 636 case AD74413R_ADC_RANGE_2P5V_EXT_POW: 637 *val = 0; 638 return 0; 639 case AD74413R_ADC_RANGE_2P5V_INT_POW: 640 *val = -((int)AD74413R_ADC_RESULT_MAX); 641 return 0; 642 case AD74413R_ADC_RANGE_5V_BI_DIR: 643 *val = -((int)AD74413R_ADC_RESULT_MAX / 2); 644 return 0; 645 default: 646 dev_err(st->dev, "ADC range invalid\n"); 647 return -EINVAL; 648 } 649 } 650 651 static int ad74413r_get_output_voltage_scale(struct ad74413r_state *st, 652 int *val, int *val2) 653 { 654 *val = AD74413R_DAC_VOLTAGE_MAX; 655 *val2 = AD74413R_DAC_CODE_MAX; 656 657 return IIO_VAL_FRACTIONAL; 658 } 659 660 static int ad74413r_get_output_current_scale(struct ad74413r_state *st, 661 int *val, int *val2) 662 { 663 *val = regulator_get_voltage(st->refin_reg); 664 *val2 = st->sense_resistor_ohms * AD74413R_DAC_CODE_MAX * 1000; 665 666 return IIO_VAL_FRACTIONAL; 667 } 668 669 static int ad74413r_get_input_voltage_scale(struct ad74413r_state *st, 670 unsigned int channel, 671 int *val, int *val2) 672 { 673 unsigned int range; 674 int ret; 675 676 ret = ad74413r_get_adc_range(st, channel, &range); 677 if (ret) 678 return ret; 679 680 ret = ad74413r_range_to_voltage_range(st, range, val); 681 if (ret) 682 return ret; 683 684 *val2 = AD74413R_ADC_RESULT_MAX; 685 686 return IIO_VAL_FRACTIONAL; 687 } 688 689 static int ad74413r_get_input_voltage_offset(struct ad74413r_state *st, 690 unsigned int channel, int *val) 691 { 692 unsigned int range; 693 int ret; 694 695 ret = ad74413r_get_adc_range(st, channel, &range); 696 if (ret) 697 return ret; 698 699 ret = ad74413r_range_to_voltage_offset_raw(st, range, val); 700 if (ret) 701 return ret; 702 703 return IIO_VAL_INT; 704 } 705 706 static int ad74413r_get_input_current_scale(struct ad74413r_state *st, 707 unsigned int channel, int *val, 708 int *val2) 709 { 710 unsigned int range; 711 int ret; 712 713 ret = ad74413r_get_adc_range(st, channel, &range); 714 if (ret) 715 return ret; 716 717 ret = ad74413r_range_to_voltage_range(st, range, val); 718 if (ret) 719 return ret; 720 721 *val2 = AD74413R_ADC_RESULT_MAX * st->sense_resistor_ohms; 722 723 return IIO_VAL_FRACTIONAL; 724 } 725 726 static int ad74413r_get_input_current_offset(struct ad74413r_state *st, 727 unsigned int channel, int *val) 728 { 729 unsigned int range; 730 int voltage_range; 731 int voltage_offset; 732 int ret; 733 734 ret = ad74413r_get_adc_range(st, channel, &range); 735 if (ret) 736 return ret; 737 738 ret = ad74413r_range_to_voltage_range(st, range, &voltage_range); 739 if (ret) 740 return ret; 741 742 ret = ad74413r_range_to_voltage_offset(st, range, &voltage_offset); 743 if (ret) 744 return ret; 745 746 *val = voltage_offset * (int)AD74413R_ADC_RESULT_MAX / voltage_range; 747 748 return IIO_VAL_INT; 749 } 750 751 static int ad74413r_get_adc_rate(struct ad74413r_state *st, 752 unsigned int channel, int *val) 753 { 754 unsigned int rejection; 755 int ret; 756 757 ret = ad74413r_get_adc_rejection(st, channel, &rejection); 758 if (ret) 759 return ret; 760 761 ret = ad74413r_rejection_to_rate(st, rejection, val); 762 if (ret) 763 return ret; 764 765 return IIO_VAL_INT; 766 } 767 768 static int ad74413r_set_adc_rate(struct ad74413r_state *st, 769 unsigned int channel, int val) 770 { 771 unsigned int rejection; 772 int ret; 773 774 ret = ad74413r_rate_to_rejection(st, val, &rejection); 775 if (ret) 776 return ret; 777 778 return ad74413r_set_adc_rejection(st, channel, rejection); 779 } 780 781 static irqreturn_t ad74413r_trigger_handler(int irq, void *p) 782 { 783 struct iio_poll_func *pf = p; 784 struct iio_dev *indio_dev = pf->indio_dev; 785 struct ad74413r_state *st = iio_priv(indio_dev); 786 u8 *rx_buf = st->adc_samples_buf.rx_buf; 787 unsigned int i; 788 int ret; 789 790 ret = spi_sync(st->spi, &st->adc_samples_msg); 791 if (ret) 792 goto out; 793 794 for (i = 0; i < st->adc_active_channels; i++) 795 ad74413r_crc_check(st, &rx_buf[i * AD74413R_FRAME_SIZE]); 796 797 iio_push_to_buffers_with_timestamp(indio_dev, &st->adc_samples_buf, 798 iio_get_time_ns(indio_dev)); 799 800 out: 801 iio_trigger_notify_done(indio_dev->trig); 802 803 return IRQ_HANDLED; 804 } 805 806 static irqreturn_t ad74413r_adc_data_interrupt(int irq, void *data) 807 { 808 struct iio_dev *indio_dev = data; 809 struct ad74413r_state *st = iio_priv(indio_dev); 810 811 if (iio_buffer_enabled(indio_dev)) 812 iio_trigger_poll(st->trig); 813 else 814 complete(&st->adc_data_completion); 815 816 return IRQ_HANDLED; 817 } 818 819 static int _ad74413r_get_single_adc_result(struct ad74413r_state *st, 820 unsigned int channel, int *val) 821 { 822 unsigned int uval; 823 int ret; 824 825 reinit_completion(&st->adc_data_completion); 826 827 ret = ad74413r_set_adc_channel_enable(st, channel, true); 828 if (ret) 829 return ret; 830 831 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_SINGLE); 832 if (ret) 833 return ret; 834 835 ret = wait_for_completion_timeout(&st->adc_data_completion, 836 msecs_to_jiffies(1000)); 837 if (!ret) { 838 ret = -ETIMEDOUT; 839 return ret; 840 } 841 842 ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel), 843 &uval); 844 if (ret) 845 return ret; 846 847 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); 848 if (ret) 849 return ret; 850 851 ret = ad74413r_set_adc_channel_enable(st, channel, false); 852 if (ret) 853 return ret; 854 855 *val = uval; 856 857 return IIO_VAL_INT; 858 } 859 860 static int ad74413r_get_single_adc_result(struct iio_dev *indio_dev, 861 unsigned int channel, int *val) 862 { 863 struct ad74413r_state *st = iio_priv(indio_dev); 864 int ret; 865 866 ret = iio_device_claim_direct_mode(indio_dev); 867 if (ret) 868 return ret; 869 870 mutex_lock(&st->lock); 871 ret = _ad74413r_get_single_adc_result(st, channel, val); 872 mutex_unlock(&st->lock); 873 874 iio_device_release_direct_mode(indio_dev); 875 876 return ret; 877 } 878 879 static void ad74413r_adc_to_resistance_result(int adc_result, int *val) 880 { 881 if (adc_result == AD74413R_ADC_RESULT_MAX) 882 adc_result = AD74413R_ADC_RESULT_MAX - 1; 883 884 *val = DIV_ROUND_CLOSEST(adc_result * 2100, 885 AD74413R_ADC_RESULT_MAX - adc_result); 886 } 887 888 static int ad74413r_update_scan_mode(struct iio_dev *indio_dev, 889 const unsigned long *active_scan_mask) 890 { 891 struct ad74413r_state *st = iio_priv(indio_dev); 892 struct spi_transfer *xfer = st->adc_samples_xfer; 893 u8 *rx_buf = st->adc_samples_buf.rx_buf; 894 u8 *tx_buf = st->adc_samples_tx_buf; 895 unsigned int channel; 896 int ret = -EINVAL; 897 898 mutex_lock(&st->lock); 899 900 spi_message_init(&st->adc_samples_msg); 901 st->adc_active_channels = 0; 902 903 for_each_clear_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) { 904 ret = ad74413r_set_adc_channel_enable(st, channel, false); 905 if (ret) 906 goto out; 907 } 908 909 if (*active_scan_mask == 0) 910 goto out; 911 912 /* 913 * The read select register is used to select which register's value 914 * will be sent by the slave on the next SPI frame. 915 * 916 * Create an SPI message that, on each step, writes to the read select 917 * register to select the ADC result of the next enabled channel, and 918 * reads the ADC result of the previous enabled channel. 919 * 920 * Example: 921 * W: [WCH1] [WCH2] [WCH2] [WCH3] [ ] 922 * R: [ ] [RCH1] [RCH2] [RCH3] [RCH4] 923 */ 924 925 for_each_set_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) { 926 ret = ad74413r_set_adc_channel_enable(st, channel, true); 927 if (ret) 928 goto out; 929 930 st->adc_active_channels++; 931 932 if (xfer == st->adc_samples_xfer) 933 xfer->rx_buf = NULL; 934 else 935 xfer->rx_buf = rx_buf; 936 937 xfer->tx_buf = tx_buf; 938 xfer->len = AD74413R_FRAME_SIZE; 939 xfer->cs_change = 1; 940 941 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, 942 AD74413R_REG_ADC_RESULT_X(channel), 943 tx_buf); 944 945 spi_message_add_tail(xfer, &st->adc_samples_msg); 946 947 tx_buf += AD74413R_FRAME_SIZE; 948 if (xfer != st->adc_samples_xfer) 949 rx_buf += AD74413R_FRAME_SIZE; 950 xfer++; 951 } 952 953 xfer->rx_buf = rx_buf; 954 xfer->tx_buf = NULL; 955 xfer->len = AD74413R_FRAME_SIZE; 956 xfer->cs_change = 0; 957 958 spi_message_add_tail(xfer, &st->adc_samples_msg); 959 960 out: 961 mutex_unlock(&st->lock); 962 963 return ret; 964 } 965 966 static int ad74413r_buffer_postenable(struct iio_dev *indio_dev) 967 { 968 struct ad74413r_state *st = iio_priv(indio_dev); 969 970 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_CONTINUOUS); 971 } 972 973 static int ad74413r_buffer_predisable(struct iio_dev *indio_dev) 974 { 975 struct ad74413r_state *st = iio_priv(indio_dev); 976 977 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); 978 } 979 980 static int ad74413r_read_raw(struct iio_dev *indio_dev, 981 struct iio_chan_spec const *chan, 982 int *val, int *val2, long info) 983 { 984 struct ad74413r_state *st = iio_priv(indio_dev); 985 986 switch (info) { 987 case IIO_CHAN_INFO_SCALE: 988 switch (chan->type) { 989 case IIO_VOLTAGE: 990 if (chan->output) 991 return ad74413r_get_output_voltage_scale(st, 992 val, val2); 993 else 994 return ad74413r_get_input_voltage_scale(st, 995 chan->channel, val, val2); 996 case IIO_CURRENT: 997 if (chan->output) 998 return ad74413r_get_output_current_scale(st, 999 val, val2); 1000 else 1001 return ad74413r_get_input_current_scale(st, 1002 chan->channel, val, val2); 1003 default: 1004 return -EINVAL; 1005 } 1006 case IIO_CHAN_INFO_OFFSET: 1007 switch (chan->type) { 1008 case IIO_VOLTAGE: 1009 return ad74413r_get_input_voltage_offset(st, 1010 chan->channel, val); 1011 case IIO_CURRENT: 1012 return ad74413r_get_input_current_offset(st, 1013 chan->channel, val); 1014 default: 1015 return -EINVAL; 1016 } 1017 case IIO_CHAN_INFO_RAW: 1018 if (chan->output) 1019 return -EINVAL; 1020 1021 return ad74413r_get_single_adc_result(indio_dev, chan->channel, 1022 val); 1023 case IIO_CHAN_INFO_PROCESSED: { 1024 int ret; 1025 1026 ret = ad74413r_get_single_adc_result(indio_dev, chan->channel, 1027 val); 1028 if (ret < 0) 1029 return ret; 1030 1031 ad74413r_adc_to_resistance_result(*val, val); 1032 1033 return ret; 1034 } 1035 case IIO_CHAN_INFO_SAMP_FREQ: 1036 return ad74413r_get_adc_rate(st, chan->channel, val); 1037 default: 1038 return -EINVAL; 1039 } 1040 } 1041 1042 static int ad74413r_write_raw(struct iio_dev *indio_dev, 1043 struct iio_chan_spec const *chan, 1044 int val, int val2, long info) 1045 { 1046 struct ad74413r_state *st = iio_priv(indio_dev); 1047 1048 switch (info) { 1049 case IIO_CHAN_INFO_RAW: 1050 if (!chan->output) 1051 return -EINVAL; 1052 1053 if (val < 0 || val > AD74413R_DAC_CODE_MAX) { 1054 dev_err(st->dev, "Invalid DAC code\n"); 1055 return -EINVAL; 1056 } 1057 1058 return ad74413r_set_channel_dac_code(st, chan->channel, val); 1059 case IIO_CHAN_INFO_SAMP_FREQ: 1060 return ad74413r_set_adc_rate(st, chan->channel, val); 1061 default: 1062 return -EINVAL; 1063 } 1064 } 1065 1066 static int ad74413r_read_avail(struct iio_dev *indio_dev, 1067 struct iio_chan_spec const *chan, 1068 const int **vals, int *type, int *length, 1069 long info) 1070 { 1071 struct ad74413r_state *st = iio_priv(indio_dev); 1072 1073 switch (info) { 1074 case IIO_CHAN_INFO_SAMP_FREQ: 1075 if (st->chip_info->hart_support) { 1076 *vals = ad74413r_adc_sampling_rates_hart; 1077 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates_hart); 1078 } else { 1079 *vals = ad74413r_adc_sampling_rates; 1080 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates); 1081 } 1082 *type = IIO_VAL_INT; 1083 return IIO_AVAIL_LIST; 1084 default: 1085 return -EINVAL; 1086 } 1087 } 1088 1089 static const struct iio_buffer_setup_ops ad74413r_buffer_ops = { 1090 .postenable = &ad74413r_buffer_postenable, 1091 .predisable = &ad74413r_buffer_predisable, 1092 }; 1093 1094 static const struct iio_trigger_ops ad74413r_trigger_ops = { 1095 .validate_device = iio_trigger_validate_own_device, 1096 }; 1097 1098 static const struct iio_info ad74413r_info = { 1099 .read_raw = &ad74413r_read_raw, 1100 .write_raw = &ad74413r_write_raw, 1101 .read_avail = &ad74413r_read_avail, 1102 .update_scan_mode = &ad74413r_update_scan_mode, 1103 }; 1104 1105 #define AD74413R_DAC_CHANNEL(_type, extra_mask_separate) \ 1106 { \ 1107 .type = (_type), \ 1108 .indexed = 1, \ 1109 .output = 1, \ 1110 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 1111 | (extra_mask_separate), \ 1112 } 1113 1114 #define AD74413R_ADC_CHANNEL(_type, extra_mask_separate) \ 1115 { \ 1116 .type = (_type), \ 1117 .indexed = 1, \ 1118 .output = 0, \ 1119 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 1120 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \ 1121 | (extra_mask_separate), \ 1122 .info_mask_separate_available = \ 1123 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 1124 .scan_type = { \ 1125 .sign = 'u', \ 1126 .realbits = 16, \ 1127 .storagebits = 32, \ 1128 .shift = 8, \ 1129 .endianness = IIO_BE, \ 1130 }, \ 1131 } 1132 1133 #define AD74413R_ADC_VOLTAGE_CHANNEL \ 1134 AD74413R_ADC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE) \ 1135 | BIT(IIO_CHAN_INFO_OFFSET)) 1136 1137 #define AD74413R_ADC_CURRENT_CHANNEL \ 1138 AD74413R_ADC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE) \ 1139 | BIT(IIO_CHAN_INFO_OFFSET)) 1140 1141 static struct iio_chan_spec ad74413r_voltage_output_channels[] = { 1142 AD74413R_DAC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)), 1143 AD74413R_ADC_CURRENT_CHANNEL, 1144 }; 1145 1146 static struct iio_chan_spec ad74413r_current_output_channels[] = { 1147 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)), 1148 AD74413R_ADC_VOLTAGE_CHANNEL, 1149 }; 1150 1151 static struct iio_chan_spec ad74413r_voltage_input_channels[] = { 1152 AD74413R_ADC_VOLTAGE_CHANNEL, 1153 }; 1154 1155 static struct iio_chan_spec ad74413r_current_input_channels[] = { 1156 AD74413R_ADC_CURRENT_CHANNEL, 1157 }; 1158 1159 static struct iio_chan_spec ad74413r_current_input_loop_channels[] = { 1160 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)), 1161 AD74413R_ADC_CURRENT_CHANNEL, 1162 }; 1163 1164 static struct iio_chan_spec ad74413r_resistance_input_channels[] = { 1165 AD74413R_ADC_CHANNEL(IIO_RESISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)), 1166 }; 1167 1168 static struct iio_chan_spec ad74413r_digital_input_channels[] = { 1169 AD74413R_ADC_VOLTAGE_CHANNEL, 1170 }; 1171 1172 #define _AD74413R_CHANNELS(_channels) \ 1173 { \ 1174 .channels = _channels, \ 1175 .num_channels = ARRAY_SIZE(_channels), \ 1176 } 1177 1178 #define AD74413R_CHANNELS(name) \ 1179 _AD74413R_CHANNELS(ad74413r_ ## name ## _channels) 1180 1181 static const struct ad74413r_channels ad74413r_channels_map[] = { 1182 [CH_FUNC_HIGH_IMPEDANCE] = AD74413R_CHANNELS(voltage_input), 1183 [CH_FUNC_VOLTAGE_OUTPUT] = AD74413R_CHANNELS(voltage_output), 1184 [CH_FUNC_CURRENT_OUTPUT] = AD74413R_CHANNELS(current_output), 1185 [CH_FUNC_VOLTAGE_INPUT] = AD74413R_CHANNELS(voltage_input), 1186 [CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74413R_CHANNELS(current_input), 1187 [CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74413R_CHANNELS(current_input_loop), 1188 [CH_FUNC_RESISTANCE_INPUT] = AD74413R_CHANNELS(resistance_input), 1189 [CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74413R_CHANNELS(digital_input), 1190 [CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74413R_CHANNELS(digital_input), 1191 [CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74413R_CHANNELS(current_input), 1192 [CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74413R_CHANNELS(current_input), 1193 }; 1194 1195 static int ad74413r_parse_channel_config(struct iio_dev *indio_dev, 1196 struct fwnode_handle *channel_node) 1197 { 1198 struct ad74413r_state *st = iio_priv(indio_dev); 1199 struct ad74413r_channel_config *config; 1200 u32 index; 1201 int ret; 1202 1203 ret = fwnode_property_read_u32(channel_node, "reg", &index); 1204 if (ret) { 1205 dev_err(st->dev, "Failed to read channel reg: %d\n", ret); 1206 return ret; 1207 } 1208 1209 if (index >= AD74413R_CHANNEL_MAX) { 1210 dev_err(st->dev, "Channel index %u is too large\n", index); 1211 return -EINVAL; 1212 } 1213 1214 config = &st->channel_configs[index]; 1215 if (config->initialized) { 1216 dev_err(st->dev, "Channel %u already initialized\n", index); 1217 return -EINVAL; 1218 } 1219 1220 config->func = CH_FUNC_HIGH_IMPEDANCE; 1221 fwnode_property_read_u32(channel_node, "adi,ch-func", &config->func); 1222 1223 if (config->func < CH_FUNC_MIN || config->func > CH_FUNC_MAX) { 1224 dev_err(st->dev, "Invalid channel function %u\n", config->func); 1225 return -EINVAL; 1226 } 1227 1228 if (!st->chip_info->hart_support && 1229 (config->func == CH_FUNC_CURRENT_INPUT_EXT_POWER_HART || 1230 config->func == CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART)) { 1231 dev_err(st->dev, "Unsupported HART function %u\n", config->func); 1232 return -EINVAL; 1233 } 1234 1235 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC || 1236 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) 1237 st->num_comparator_gpios++; 1238 1239 config->gpo_comparator = fwnode_property_read_bool(channel_node, 1240 "adi,gpo-comparator"); 1241 1242 fwnode_property_read_u32(channel_node, "drive-strength-microamp", 1243 &config->drive_strength); 1244 1245 if (!config->gpo_comparator) 1246 st->num_gpo_gpios++; 1247 1248 indio_dev->num_channels += ad74413r_channels_map[config->func].num_channels; 1249 1250 config->initialized = true; 1251 1252 return 0; 1253 } 1254 1255 static int ad74413r_parse_channel_configs(struct iio_dev *indio_dev) 1256 { 1257 struct ad74413r_state *st = iio_priv(indio_dev); 1258 int ret; 1259 1260 device_for_each_child_node_scoped(st->dev, channel_node) { 1261 ret = ad74413r_parse_channel_config(indio_dev, channel_node); 1262 if (ret) 1263 return ret; 1264 } 1265 1266 return 0; 1267 } 1268 1269 static int ad74413r_setup_channels(struct iio_dev *indio_dev) 1270 { 1271 struct ad74413r_state *st = iio_priv(indio_dev); 1272 struct ad74413r_channel_config *config; 1273 struct iio_chan_spec *channels, *chans; 1274 unsigned int i, num_chans, chan_i; 1275 int ret; 1276 1277 channels = devm_kcalloc(st->dev, sizeof(*channels), 1278 indio_dev->num_channels, GFP_KERNEL); 1279 if (!channels) 1280 return -ENOMEM; 1281 1282 indio_dev->channels = channels; 1283 1284 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) { 1285 config = &st->channel_configs[i]; 1286 chans = ad74413r_channels_map[config->func].channels; 1287 num_chans = ad74413r_channels_map[config->func].num_channels; 1288 1289 memcpy(channels, chans, num_chans * sizeof(*chans)); 1290 1291 for (chan_i = 0; chan_i < num_chans; chan_i++) { 1292 struct iio_chan_spec *chan = &channels[chan_i]; 1293 1294 chan->channel = i; 1295 if (chan->output) 1296 chan->scan_index = -1; 1297 else 1298 chan->scan_index = i; 1299 } 1300 1301 ret = ad74413r_set_channel_function(st, i, config->func); 1302 if (ret) 1303 return ret; 1304 1305 channels += num_chans; 1306 } 1307 1308 return 0; 1309 } 1310 1311 static int ad74413r_setup_gpios(struct ad74413r_state *st) 1312 { 1313 struct ad74413r_channel_config *config; 1314 unsigned int comp_gpio_i = 0; 1315 unsigned int gpo_gpio_i = 0; 1316 unsigned int i; 1317 u8 gpo_config; 1318 u32 strength; 1319 int ret; 1320 1321 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) { 1322 config = &st->channel_configs[i]; 1323 1324 if (config->gpo_comparator) { 1325 gpo_config = AD74413R_GPO_CONFIG_COMPARATOR; 1326 } else { 1327 gpo_config = AD74413R_GPO_CONFIG_LOGIC; 1328 st->gpo_gpio_offsets[gpo_gpio_i++] = i; 1329 } 1330 1331 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC || 1332 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) { 1333 st->comp_gpio_offsets[comp_gpio_i++] = i; 1334 1335 strength = config->drive_strength; 1336 ret = ad74413r_set_comp_drive_strength(st, i, strength); 1337 if (ret) 1338 return ret; 1339 } 1340 1341 ret = ad74413r_set_gpo_config(st, i, gpo_config); 1342 if (ret) 1343 return ret; 1344 } 1345 1346 return 0; 1347 } 1348 1349 static void ad74413r_regulator_disable(void *regulator) 1350 { 1351 regulator_disable(regulator); 1352 } 1353 1354 static int ad74413r_probe(struct spi_device *spi) 1355 { 1356 struct ad74413r_state *st; 1357 struct iio_dev *indio_dev; 1358 int ret; 1359 1360 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1361 if (!indio_dev) 1362 return -ENOMEM; 1363 1364 st = iio_priv(indio_dev); 1365 1366 st->spi = spi; 1367 st->dev = &spi->dev; 1368 st->chip_info = spi_get_device_match_data(spi); 1369 if (!st->chip_info) 1370 return -EINVAL; 1371 1372 mutex_init(&st->lock); 1373 init_completion(&st->adc_data_completion); 1374 1375 st->regmap = devm_regmap_init(st->dev, NULL, st, 1376 &ad74413r_regmap_config); 1377 if (IS_ERR(st->regmap)) 1378 return PTR_ERR(st->regmap); 1379 1380 st->reset_gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW); 1381 if (IS_ERR(st->reset_gpio)) 1382 return PTR_ERR(st->reset_gpio); 1383 1384 st->refin_reg = devm_regulator_get(st->dev, "refin"); 1385 if (IS_ERR(st->refin_reg)) 1386 return dev_err_probe(st->dev, PTR_ERR(st->refin_reg), 1387 "Failed to get refin regulator\n"); 1388 1389 ret = regulator_enable(st->refin_reg); 1390 if (ret) 1391 return ret; 1392 1393 ret = devm_add_action_or_reset(st->dev, ad74413r_regulator_disable, 1394 st->refin_reg); 1395 if (ret) 1396 return ret; 1397 1398 st->sense_resistor_ohms = 100000000; 1399 device_property_read_u32(st->dev, "shunt-resistor-micro-ohms", 1400 &st->sense_resistor_ohms); 1401 st->sense_resistor_ohms /= 1000000; 1402 1403 st->trig = devm_iio_trigger_alloc(st->dev, "%s-dev%d", 1404 st->chip_info->name, iio_device_id(indio_dev)); 1405 if (!st->trig) 1406 return -ENOMEM; 1407 1408 st->trig->ops = &ad74413r_trigger_ops; 1409 iio_trigger_set_drvdata(st->trig, st); 1410 1411 ret = devm_iio_trigger_register(st->dev, st->trig); 1412 if (ret) 1413 return ret; 1414 1415 indio_dev->name = st->chip_info->name; 1416 indio_dev->modes = INDIO_DIRECT_MODE; 1417 indio_dev->info = &ad74413r_info; 1418 indio_dev->trig = iio_trigger_get(st->trig); 1419 1420 ret = ad74413r_reset(st); 1421 if (ret) 1422 return ret; 1423 1424 ret = ad74413r_parse_channel_configs(indio_dev); 1425 if (ret) 1426 return ret; 1427 1428 ret = ad74413r_setup_channels(indio_dev); 1429 if (ret) 1430 return ret; 1431 1432 ret = ad74413r_setup_gpios(st); 1433 if (ret) 1434 return ret; 1435 1436 if (st->num_gpo_gpios) { 1437 st->gpo_gpiochip.owner = THIS_MODULE; 1438 st->gpo_gpiochip.label = st->chip_info->name; 1439 st->gpo_gpiochip.base = -1; 1440 st->gpo_gpiochip.ngpio = st->num_gpo_gpios; 1441 st->gpo_gpiochip.parent = st->dev; 1442 st->gpo_gpiochip.can_sleep = true; 1443 st->gpo_gpiochip.set = ad74413r_gpio_set; 1444 st->gpo_gpiochip.set_multiple = ad74413r_gpio_set_multiple; 1445 st->gpo_gpiochip.set_config = ad74413r_gpio_set_gpo_config; 1446 st->gpo_gpiochip.get_direction = 1447 ad74413r_gpio_get_gpo_direction; 1448 1449 ret = devm_gpiochip_add_data(st->dev, &st->gpo_gpiochip, st); 1450 if (ret) 1451 return ret; 1452 } 1453 1454 if (st->num_comparator_gpios) { 1455 st->comp_gpiochip.owner = THIS_MODULE; 1456 st->comp_gpiochip.label = st->chip_info->name; 1457 st->comp_gpiochip.base = -1; 1458 st->comp_gpiochip.ngpio = st->num_comparator_gpios; 1459 st->comp_gpiochip.parent = st->dev; 1460 st->comp_gpiochip.can_sleep = true; 1461 st->comp_gpiochip.get = ad74413r_gpio_get; 1462 st->comp_gpiochip.get_multiple = ad74413r_gpio_get_multiple; 1463 st->comp_gpiochip.set_config = ad74413r_gpio_set_comp_config; 1464 st->comp_gpiochip.get_direction = 1465 ad74413r_gpio_get_comp_direction; 1466 1467 ret = devm_gpiochip_add_data(st->dev, &st->comp_gpiochip, st); 1468 if (ret) 1469 return ret; 1470 } 1471 1472 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF); 1473 if (ret) 1474 return ret; 1475 1476 ret = devm_request_irq(st->dev, spi->irq, ad74413r_adc_data_interrupt, 1477 0, st->chip_info->name, indio_dev); 1478 if (ret) 1479 return dev_err_probe(st->dev, ret, "Failed to request irq\n"); 1480 1481 ret = devm_iio_triggered_buffer_setup(st->dev, indio_dev, 1482 &iio_pollfunc_store_time, 1483 &ad74413r_trigger_handler, 1484 &ad74413r_buffer_ops); 1485 if (ret) 1486 return ret; 1487 1488 return devm_iio_device_register(st->dev, indio_dev); 1489 } 1490 1491 static int ad74413r_unregister_driver(struct spi_driver *spi) 1492 { 1493 spi_unregister_driver(spi); 1494 1495 return 0; 1496 } 1497 1498 static int __init ad74413r_register_driver(struct spi_driver *spi) 1499 { 1500 crc8_populate_msb(ad74413r_crc8_table, AD74413R_CRC_POLYNOMIAL); 1501 1502 return spi_register_driver(spi); 1503 } 1504 1505 static const struct ad74413r_chip_info ad74412r_chip_info_data = { 1506 .hart_support = false, 1507 .name = "ad74412r", 1508 }; 1509 1510 static const struct ad74413r_chip_info ad74413r_chip_info_data = { 1511 .hart_support = true, 1512 .name = "ad74413r", 1513 }; 1514 1515 static const struct of_device_id ad74413r_dt_id[] = { 1516 { 1517 .compatible = "adi,ad74412r", 1518 .data = &ad74412r_chip_info_data, 1519 }, 1520 { 1521 .compatible = "adi,ad74413r", 1522 .data = &ad74413r_chip_info_data, 1523 }, 1524 {}, 1525 }; 1526 MODULE_DEVICE_TABLE(of, ad74413r_dt_id); 1527 1528 static const struct spi_device_id ad74413r_spi_id[] = { 1529 { .name = "ad74412r", .driver_data = (kernel_ulong_t)&ad74412r_chip_info_data }, 1530 { .name = "ad74413r", .driver_data = (kernel_ulong_t)&ad74413r_chip_info_data }, 1531 {} 1532 }; 1533 MODULE_DEVICE_TABLE(spi, ad74413r_spi_id); 1534 1535 static struct spi_driver ad74413r_driver = { 1536 .driver = { 1537 .name = "ad74413r", 1538 .of_match_table = ad74413r_dt_id, 1539 }, 1540 .probe = ad74413r_probe, 1541 .id_table = ad74413r_spi_id, 1542 }; 1543 1544 module_driver(ad74413r_driver, 1545 ad74413r_register_driver, 1546 ad74413r_unregister_driver); 1547 1548 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>"); 1549 MODULE_DESCRIPTION("Analog Devices AD74413R ADDAC"); 1550 MODULE_LICENSE("GPL v2"); 1551