1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx AMS driver 4 * 5 * Copyright (C) 2021 Xilinx, Inc. 6 * 7 * Manish Narani <mnarani@xilinx.com> 8 * Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> 9 */ 10 11 #include <linux/bits.h> 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/devm-helpers.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/overflow.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 #include <linux/slab.h> 26 27 #include <linux/iio/events.h> 28 #include <linux/iio/iio.h> 29 30 /* AMS registers definitions */ 31 #define AMS_ISR_0 0x010 32 #define AMS_ISR_1 0x014 33 #define AMS_IER_0 0x020 34 #define AMS_IER_1 0x024 35 #define AMS_IDR_0 0x028 36 #define AMS_IDR_1 0x02C 37 #define AMS_PS_CSTS 0x040 38 #define AMS_PL_CSTS 0x044 39 40 #define AMS_VCC_PSPLL0 0x060 41 #define AMS_VCC_PSPLL3 0x06C 42 #define AMS_VCCINT 0x078 43 #define AMS_VCCBRAM 0x07C 44 #define AMS_VCCAUX 0x080 45 #define AMS_PSDDRPLL 0x084 46 #define AMS_PSINTFPDDR 0x09C 47 48 #define AMS_VCC_PSPLL0_CH 48 49 #define AMS_VCC_PSPLL3_CH 51 50 #define AMS_VCCINT_CH 54 51 #define AMS_VCCBRAM_CH 55 52 #define AMS_VCCAUX_CH 56 53 #define AMS_PSDDRPLL_CH 57 54 #define AMS_PSINTFPDDR_CH 63 55 56 #define AMS_REG_CONFIG0 0x100 57 #define AMS_REG_CONFIG1 0x104 58 #define AMS_REG_CONFIG3 0x10C 59 #define AMS_REG_CONFIG4 0x110 60 #define AMS_REG_SEQ_CH0 0x120 61 #define AMS_REG_SEQ_CH1 0x124 62 #define AMS_REG_SEQ_CH2 0x118 63 64 #define AMS_VUSER0_MASK BIT(0) 65 #define AMS_VUSER1_MASK BIT(1) 66 #define AMS_VUSER2_MASK BIT(2) 67 #define AMS_VUSER3_MASK BIT(3) 68 69 #define AMS_TEMP 0x000 70 #define AMS_SUPPLY1 0x004 71 #define AMS_SUPPLY2 0x008 72 #define AMS_VP_VN 0x00C 73 #define AMS_VREFP 0x010 74 #define AMS_VREFN 0x014 75 #define AMS_SUPPLY3 0x018 76 #define AMS_SUPPLY4 0x034 77 #define AMS_SUPPLY5 0x038 78 #define AMS_SUPPLY6 0x03C 79 #define AMS_SUPPLY7 0x200 80 #define AMS_SUPPLY8 0x204 81 #define AMS_SUPPLY9 0x208 82 #define AMS_SUPPLY10 0x20C 83 #define AMS_VCCAMS 0x210 84 #define AMS_TEMP_REMOTE 0x214 85 86 #define AMS_REG_VAUX(x) (0x40 + 4 * (x)) 87 88 #define AMS_PS_RESET_VALUE 0xFFFF 89 #define AMS_PL_RESET_VALUE 0xFFFF 90 91 #define AMS_CONF0_CHANNEL_NUM_MASK GENMASK(6, 0) 92 93 #define AMS_CONF1_SEQ_MASK GENMASK(15, 12) 94 #define AMS_CONF1_SEQ_DEFAULT FIELD_PREP(AMS_CONF1_SEQ_MASK, 0) 95 #define AMS_CONF1_SEQ_CONTINUOUS FIELD_PREP(AMS_CONF1_SEQ_MASK, 2) 96 #define AMS_CONF1_SEQ_SINGLE_CHANNEL FIELD_PREP(AMS_CONF1_SEQ_MASK, 3) 97 98 #define AMS_REG_SEQ0_MASK GENMASK(15, 0) 99 #define AMS_REG_SEQ2_MASK GENMASK(21, 16) 100 #define AMS_REG_SEQ1_MASK GENMASK_ULL(37, 22) 101 102 #define AMS_PS_SEQ_MASK GENMASK(21, 0) 103 #define AMS_PL_SEQ_MASK GENMASK_ULL(59, 22) 104 105 #define AMS_ALARM_NONE 0x000 /* not a real offset */ 106 #define AMS_ALARM_TEMP 0x140 107 #define AMS_ALARM_SUPPLY1 0x144 108 #define AMS_ALARM_SUPPLY2 0x148 109 #define AMS_ALARM_SUPPLY3 0x160 110 #define AMS_ALARM_SUPPLY4 0x164 111 #define AMS_ALARM_SUPPLY5 0x168 112 #define AMS_ALARM_SUPPLY6 0x16C 113 #define AMS_ALARM_SUPPLY7 0x180 114 #define AMS_ALARM_SUPPLY8 0x184 115 #define AMS_ALARM_SUPPLY9 0x188 116 #define AMS_ALARM_SUPPLY10 0x18C 117 #define AMS_ALARM_VCCAMS 0x190 118 #define AMS_ALARM_TEMP_REMOTE 0x194 119 #define AMS_ALARM_THRESHOLD_OFF_10 0x10 120 #define AMS_ALARM_THRESHOLD_OFF_20 0x20 121 122 #define AMS_ALARM_THR_DIRECT_MASK BIT(0) 123 #define AMS_ALARM_THR_MIN 0x0000 124 #define AMS_ALARM_THR_MAX (BIT(16) - 1) 125 126 #define AMS_ALARM_MASK GENMASK_ULL(63, 0) 127 #define AMS_NO_OF_ALARMS 32 128 #define AMS_PL_ALARM_START 16 129 #define AMS_PL_ALARM_MASK GENMASK(31, 16) 130 #define AMS_ISR0_ALARM_MASK GENMASK(31, 0) 131 #define AMS_ISR1_ALARM_MASK (GENMASK(31, 29) | GENMASK(4, 0)) 132 #define AMS_ISR1_EOC_MASK BIT(3) 133 #define AMS_ISR1_INTR_MASK GENMASK_ULL(63, 32) 134 #define AMS_ISR0_ALARM_2_TO_0_MASK GENMASK(2, 0) 135 #define AMS_ISR0_ALARM_6_TO_3_MASK GENMASK(6, 3) 136 #define AMS_ISR0_ALARM_12_TO_7_MASK GENMASK(13, 8) 137 #define AMS_CONF1_ALARM_2_TO_0_MASK GENMASK(3, 1) 138 #define AMS_CONF1_ALARM_6_TO_3_MASK GENMASK(11, 8) 139 #define AMS_CONF1_ALARM_12_TO_7_MASK GENMASK(5, 0) 140 #define AMS_REGCFG1_ALARM_MASK \ 141 (AMS_CONF1_ALARM_2_TO_0_MASK | AMS_CONF1_ALARM_6_TO_3_MASK | BIT(0)) 142 #define AMS_REGCFG3_ALARM_MASK AMS_CONF1_ALARM_12_TO_7_MASK 143 144 #define AMS_PS_CSTS_PS_READY (BIT(27) | BIT(16)) 145 #define AMS_PL_CSTS_ACCESS_MASK BIT(1) 146 147 #define AMS_PL_MAX_FIXED_CHANNEL 10 148 #define AMS_PL_MAX_EXT_CHANNEL 20 149 150 #define AMS_INIT_POLL_TIME_US 200 151 #define AMS_INIT_TIMEOUT_US 10000 152 #define AMS_UNMASK_TIMEOUT_MS 500 153 154 /* 155 * Following scale and offset value is derived from 156 * UG580 (v1.7) December 20, 2016 157 */ 158 #define AMS_SUPPLY_SCALE_1VOLT_mV 1000 159 #define AMS_SUPPLY_SCALE_3VOLT_mV 3000 160 #define AMS_SUPPLY_SCALE_6VOLT_mV 6000 161 #define AMS_SUPPLY_SCALE_DIV_BIT 16 162 163 #define AMS_TEMP_SCALE 509314 164 #define AMS_TEMP_SCALE_DIV_BIT 16 165 #define AMS_TEMP_OFFSET -((280230LL << 16) / 509314) 166 167 enum ams_alarm_bit { 168 AMS_ALARM_BIT_TEMP = 0, 169 AMS_ALARM_BIT_SUPPLY1 = 1, 170 AMS_ALARM_BIT_SUPPLY2 = 2, 171 AMS_ALARM_BIT_SUPPLY3 = 3, 172 AMS_ALARM_BIT_SUPPLY4 = 4, 173 AMS_ALARM_BIT_SUPPLY5 = 5, 174 AMS_ALARM_BIT_SUPPLY6 = 6, 175 AMS_ALARM_BIT_RESERVED = 7, 176 AMS_ALARM_BIT_SUPPLY7 = 8, 177 AMS_ALARM_BIT_SUPPLY8 = 9, 178 AMS_ALARM_BIT_SUPPLY9 = 10, 179 AMS_ALARM_BIT_SUPPLY10 = 11, 180 AMS_ALARM_BIT_VCCAMS = 12, 181 AMS_ALARM_BIT_TEMP_REMOTE = 13, 182 }; 183 184 enum ams_seq { 185 AMS_SEQ_VCC_PSPLL = 0, 186 AMS_SEQ_VCC_PSBATT = 1, 187 AMS_SEQ_VCCINT = 2, 188 AMS_SEQ_VCCBRAM = 3, 189 AMS_SEQ_VCCAUX = 4, 190 AMS_SEQ_PSDDRPLL = 5, 191 AMS_SEQ_INTDDR = 6, 192 }; 193 194 enum ams_ps_pl_seq { 195 AMS_SEQ_CALIB = 0, 196 AMS_SEQ_RSVD_1 = 1, 197 AMS_SEQ_RSVD_2 = 2, 198 AMS_SEQ_TEST = 3, 199 AMS_SEQ_RSVD_4 = 4, 200 AMS_SEQ_SUPPLY4 = 5, 201 AMS_SEQ_SUPPLY5 = 6, 202 AMS_SEQ_SUPPLY6 = 7, 203 AMS_SEQ_TEMP = 8, 204 AMS_SEQ_SUPPLY2 = 9, 205 AMS_SEQ_SUPPLY1 = 10, 206 AMS_SEQ_VP_VN = 11, 207 AMS_SEQ_VREFP = 12, 208 AMS_SEQ_VREFN = 13, 209 AMS_SEQ_SUPPLY3 = 14, 210 AMS_SEQ_CURRENT_MON = 15, 211 AMS_SEQ_SUPPLY7 = 16, 212 AMS_SEQ_SUPPLY8 = 17, 213 AMS_SEQ_SUPPLY9 = 18, 214 AMS_SEQ_SUPPLY10 = 19, 215 AMS_SEQ_VCCAMS = 20, 216 AMS_SEQ_TEMP_REMOTE = 21, 217 AMS_SEQ_MAX = 22 218 }; 219 220 #define AMS_PS_SEQ_MAX AMS_SEQ_MAX 221 #define AMS_SEQ(x) (AMS_SEQ_MAX + (x)) 222 #define PS_SEQ(x) (x) 223 #define PL_SEQ(x) (AMS_PS_SEQ_MAX + (x)) 224 #define AMS_CTRL_SEQ_BASE (AMS_PS_SEQ_MAX * 3) 225 226 #define AMS_CHAN_TEMP(_scan_index, _addr, _name) { \ 227 .type = IIO_TEMP, \ 228 .indexed = 1, \ 229 .address = (_addr), \ 230 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 231 BIT(IIO_CHAN_INFO_SCALE) | \ 232 BIT(IIO_CHAN_INFO_OFFSET), \ 233 .event_spec = ams_temp_events, \ 234 .scan_index = _scan_index, \ 235 .num_event_specs = ARRAY_SIZE(ams_temp_events), \ 236 .datasheet_name = _name, \ 237 } 238 239 #define AMS_CHAN_VOLTAGE(_scan_index, _addr, _alarm, _name) { \ 240 .type = IIO_VOLTAGE, \ 241 .indexed = 1, \ 242 .address = (_addr), \ 243 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 244 BIT(IIO_CHAN_INFO_SCALE), \ 245 .event_spec = (_alarm) ? ams_voltage_events : NULL, \ 246 .scan_index = _scan_index, \ 247 .num_event_specs = (_alarm) ? ARRAY_SIZE(ams_voltage_events) : 0, \ 248 .datasheet_name = _name, \ 249 } 250 251 #define AMS_PS_CHAN_TEMP(_scan_index, _addr, _name) \ 252 AMS_CHAN_TEMP(PS_SEQ(_scan_index), _addr, _name) 253 #define AMS_PS_CHAN_VOLTAGE(_scan_index, _addr, _name) \ 254 AMS_CHAN_VOLTAGE(PS_SEQ(_scan_index), _addr, true, _name) 255 256 #define AMS_PL_CHAN_TEMP(_scan_index, _addr, _name) \ 257 AMS_CHAN_TEMP(PL_SEQ(_scan_index), _addr, _name) 258 #define AMS_PL_CHAN_VOLTAGE(_scan_index, _addr, _alarm, _name) \ 259 AMS_CHAN_VOLTAGE(PL_SEQ(_scan_index), _addr, _alarm, _name) 260 #define AMS_PL_AUX_CHAN_VOLTAGE(_auxno) \ 261 AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(_auxno)), AMS_REG_VAUX(_auxno), false, \ 262 "VAUX" #_auxno) 263 #define AMS_CTRL_CHAN_VOLTAGE(_scan_index, _addr, _name) \ 264 AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(AMS_SEQ(_scan_index))), _addr, false, \ 265 _name) 266 267 /** 268 * struct ams - This structure contains necessary state for xilinx-ams to operate 269 * @base: physical base address of device 270 * @ps_base: physical base address of PS device 271 * @pl_base: physical base address of PL device 272 * @clk: clocks associated with the device 273 * @dev: pointer to device struct 274 * @lock: to handle multiple user interaction 275 * @intr_lock: to protect interrupt mask values 276 * @alarm_mask: alarm configuration 277 * @current_masked_alarm: currently masked due to alarm 278 * @intr_mask: interrupt configuration 279 * @ams_unmask_work: re-enables event once the event condition disappears 280 * 281 */ 282 struct ams { 283 void __iomem *base; 284 void __iomem *ps_base; 285 void __iomem *pl_base; 286 struct clk *clk; 287 struct device *dev; 288 struct mutex lock; 289 spinlock_t intr_lock; 290 unsigned int alarm_mask; 291 unsigned int current_masked_alarm; 292 u64 intr_mask; 293 struct delayed_work ams_unmask_work; 294 }; 295 296 static inline void ams_ps_update_reg(struct ams *ams, unsigned int offset, 297 u32 mask, u32 data) 298 { 299 u32 val, regval; 300 301 val = readl(ams->ps_base + offset); 302 regval = (val & ~mask) | (data & mask); 303 writel(regval, ams->ps_base + offset); 304 } 305 306 static inline void ams_pl_update_reg(struct ams *ams, unsigned int offset, 307 u32 mask, u32 data) 308 { 309 u32 val, regval; 310 311 val = readl(ams->pl_base + offset); 312 regval = (val & ~mask) | (data & mask); 313 writel(regval, ams->pl_base + offset); 314 } 315 316 static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val) 317 { 318 u32 regval; 319 320 ams->intr_mask = (ams->intr_mask & ~mask) | (val & mask); 321 322 regval = ~(ams->intr_mask | ams->current_masked_alarm); 323 writel(regval, ams->base + AMS_IER_0); 324 325 regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask)); 326 writel(regval, ams->base + AMS_IER_1); 327 328 regval = ams->intr_mask | ams->current_masked_alarm; 329 writel(regval, ams->base + AMS_IDR_0); 330 331 regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask); 332 writel(regval, ams->base + AMS_IDR_1); 333 } 334 335 static void ams_disable_all_alarms(struct ams *ams) 336 { 337 /* disable PS module alarm */ 338 if (ams->ps_base) { 339 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, 340 AMS_REGCFG1_ALARM_MASK); 341 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, 342 AMS_REGCFG3_ALARM_MASK); 343 } 344 345 /* disable PL module alarm */ 346 if (ams->pl_base) { 347 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, 348 AMS_REGCFG1_ALARM_MASK); 349 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, 350 AMS_REGCFG3_ALARM_MASK); 351 } 352 } 353 354 static void ams_update_ps_alarm(struct ams *ams, unsigned long alarm_mask) 355 { 356 u32 cfg; 357 u32 val; 358 359 val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, alarm_mask); 360 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val)); 361 362 val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, alarm_mask); 363 cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val)); 364 365 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg); 366 367 val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, alarm_mask); 368 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val)); 369 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg); 370 } 371 372 static void ams_update_pl_alarm(struct ams *ams, unsigned long alarm_mask) 373 { 374 unsigned long pl_alarm_mask; 375 u32 cfg; 376 u32 val; 377 378 pl_alarm_mask = FIELD_GET(AMS_PL_ALARM_MASK, alarm_mask); 379 380 val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, pl_alarm_mask); 381 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val)); 382 383 val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, pl_alarm_mask); 384 cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val)); 385 386 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg); 387 388 val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, pl_alarm_mask); 389 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val)); 390 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg); 391 } 392 393 static void ams_unmask(struct ams *ams) 394 { 395 unsigned int status, unmask; 396 397 status = readl(ams->base + AMS_ISR_0); 398 399 /* Clear those bits which are not active anymore */ 400 unmask = (ams->current_masked_alarm ^ status) & ams->current_masked_alarm; 401 402 /* Clear status of disabled alarm */ 403 unmask |= ams->intr_mask; 404 405 ams->current_masked_alarm &= status; 406 407 /* Also clear those which are masked out anyway */ 408 ams->current_masked_alarm &= ~ams->intr_mask; 409 410 /* Clear the interrupts before we unmask them */ 411 writel(unmask, ams->base + AMS_ISR_0); 412 413 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK); 414 } 415 416 static void ams_update_alarm(struct ams *ams, unsigned long alarm_mask) 417 { 418 unsigned long flags; 419 420 if (ams->ps_base) 421 ams_update_ps_alarm(ams, alarm_mask); 422 423 if (ams->pl_base) 424 ams_update_pl_alarm(ams, alarm_mask); 425 426 spin_lock_irqsave(&ams->intr_lock, flags); 427 ams_update_intrmask(ams, AMS_ISR0_ALARM_MASK, ~alarm_mask); 428 ams_unmask(ams); 429 spin_unlock_irqrestore(&ams->intr_lock, flags); 430 } 431 432 static void ams_enable_channel_sequence(struct iio_dev *indio_dev) 433 { 434 struct ams *ams = iio_priv(indio_dev); 435 unsigned long long scan_mask; 436 int i; 437 u32 regval; 438 439 /* 440 * Enable channel sequence. First 22 bits of scan_mask represent 441 * PS channels, and next remaining bits represent PL channels. 442 */ 443 444 /* Run calibration of PS & PL as part of the sequence */ 445 scan_mask = BIT(0) | BIT(AMS_PS_SEQ_MAX); 446 for (i = 0; i < indio_dev->num_channels; i++) { 447 const struct iio_chan_spec *chan = &indio_dev->channels[i]; 448 449 if (chan->scan_index < AMS_CTRL_SEQ_BASE) 450 scan_mask |= BIT_ULL(chan->scan_index); 451 } 452 453 if (ams->ps_base) { 454 /* put sysmon in a soft reset to change the sequence */ 455 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 456 AMS_CONF1_SEQ_DEFAULT); 457 458 /* configure basic channels */ 459 regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask); 460 writel(regval, ams->ps_base + AMS_REG_SEQ_CH0); 461 462 regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask); 463 writel(regval, ams->ps_base + AMS_REG_SEQ_CH2); 464 465 /* set continuous sequence mode */ 466 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 467 AMS_CONF1_SEQ_CONTINUOUS); 468 } 469 470 if (ams->pl_base) { 471 /* put sysmon in a soft reset to change the sequence */ 472 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 473 AMS_CONF1_SEQ_DEFAULT); 474 475 /* configure basic channels */ 476 scan_mask = FIELD_GET(AMS_PL_SEQ_MASK, scan_mask); 477 478 regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask); 479 writel(regval, ams->pl_base + AMS_REG_SEQ_CH0); 480 481 regval = FIELD_GET(AMS_REG_SEQ1_MASK, scan_mask); 482 writel(regval, ams->pl_base + AMS_REG_SEQ_CH1); 483 484 regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask); 485 writel(regval, ams->pl_base + AMS_REG_SEQ_CH2); 486 487 /* set continuous sequence mode */ 488 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 489 AMS_CONF1_SEQ_CONTINUOUS); 490 } 491 } 492 493 static int ams_init_device(struct ams *ams) 494 { 495 u32 expect = AMS_PS_CSTS_PS_READY; 496 u32 reg, value; 497 int ret; 498 499 /* reset AMS */ 500 if (ams->ps_base) { 501 writel(AMS_PS_RESET_VALUE, ams->ps_base + AMS_VP_VN); 502 503 ret = readl_poll_timeout(ams->base + AMS_PS_CSTS, reg, (reg & expect), 504 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US); 505 if (ret) 506 return ret; 507 508 /* put sysmon in a default state */ 509 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 510 AMS_CONF1_SEQ_DEFAULT); 511 } 512 513 if (ams->pl_base) { 514 value = readl(ams->base + AMS_PL_CSTS); 515 if (value == 0) 516 return 0; 517 518 writel(AMS_PL_RESET_VALUE, ams->pl_base + AMS_VP_VN); 519 520 /* put sysmon in a default state */ 521 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 522 AMS_CONF1_SEQ_DEFAULT); 523 } 524 525 ams_disable_all_alarms(ams); 526 527 /* Disable interrupt */ 528 ams_update_intrmask(ams, AMS_ALARM_MASK, AMS_ALARM_MASK); 529 530 /* Clear any pending interrupt */ 531 writel(AMS_ISR0_ALARM_MASK, ams->base + AMS_ISR_0); 532 writel(AMS_ISR1_ALARM_MASK, ams->base + AMS_ISR_1); 533 534 return 0; 535 } 536 537 static int ams_read_label(struct iio_dev *indio_dev, 538 struct iio_chan_spec const *chan, char *label) 539 { 540 return sysfs_emit(label, "%s\n", chan->datasheet_name); 541 } 542 543 static int ams_enable_single_channel(struct ams *ams, unsigned int offset) 544 { 545 u8 channel_num; 546 547 switch (offset) { 548 case AMS_VCC_PSPLL0: 549 channel_num = AMS_VCC_PSPLL0_CH; 550 break; 551 case AMS_VCC_PSPLL3: 552 channel_num = AMS_VCC_PSPLL3_CH; 553 break; 554 case AMS_VCCINT: 555 channel_num = AMS_VCCINT_CH; 556 break; 557 case AMS_VCCBRAM: 558 channel_num = AMS_VCCBRAM_CH; 559 break; 560 case AMS_VCCAUX: 561 channel_num = AMS_VCCAUX_CH; 562 break; 563 case AMS_PSDDRPLL: 564 channel_num = AMS_PSDDRPLL_CH; 565 break; 566 case AMS_PSINTFPDDR: 567 channel_num = AMS_PSINTFPDDR_CH; 568 break; 569 default: 570 return -EINVAL; 571 } 572 573 /* put sysmon in a soft reset to change the sequence */ 574 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 575 AMS_CONF1_SEQ_DEFAULT); 576 577 /* write the channel number */ 578 ams_ps_update_reg(ams, AMS_REG_CONFIG0, AMS_CONF0_CHANNEL_NUM_MASK, 579 channel_num); 580 581 /* set single channel, sequencer off mode */ 582 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 583 AMS_CONF1_SEQ_SINGLE_CHANNEL); 584 585 return 0; 586 } 587 588 static int ams_read_vcc_reg(struct ams *ams, unsigned int offset, u32 *data) 589 { 590 u32 expect = AMS_ISR1_EOC_MASK; 591 u32 reg; 592 int ret; 593 594 ret = ams_enable_single_channel(ams, offset); 595 if (ret) 596 return ret; 597 598 /* clear end-of-conversion flag, wait for next conversion to complete */ 599 writel(expect, ams->base + AMS_ISR_1); 600 ret = readl_poll_timeout(ams->base + AMS_ISR_1, reg, (reg & expect), 601 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US); 602 if (ret) 603 return ret; 604 605 *data = readl(ams->base + offset); 606 607 return 0; 608 } 609 610 static int ams_get_ps_scale(int address) 611 { 612 int val; 613 614 switch (address) { 615 case AMS_SUPPLY1: 616 case AMS_SUPPLY2: 617 case AMS_SUPPLY3: 618 case AMS_SUPPLY4: 619 case AMS_SUPPLY9: 620 case AMS_SUPPLY10: 621 case AMS_VCCAMS: 622 val = AMS_SUPPLY_SCALE_3VOLT_mV; 623 break; 624 case AMS_SUPPLY5: 625 case AMS_SUPPLY6: 626 case AMS_SUPPLY7: 627 case AMS_SUPPLY8: 628 val = AMS_SUPPLY_SCALE_6VOLT_mV; 629 break; 630 default: 631 val = AMS_SUPPLY_SCALE_1VOLT_mV; 632 break; 633 } 634 635 return val; 636 } 637 638 static int ams_get_pl_scale(struct ams *ams, int address) 639 { 640 int val, regval; 641 642 switch (address) { 643 case AMS_SUPPLY1: 644 case AMS_SUPPLY2: 645 case AMS_SUPPLY3: 646 case AMS_SUPPLY4: 647 case AMS_SUPPLY5: 648 case AMS_SUPPLY6: 649 case AMS_VCCAMS: 650 case AMS_VREFP: 651 case AMS_VREFN: 652 val = AMS_SUPPLY_SCALE_3VOLT_mV; 653 break; 654 case AMS_SUPPLY7: 655 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 656 if (FIELD_GET(AMS_VUSER0_MASK, regval)) 657 val = AMS_SUPPLY_SCALE_6VOLT_mV; 658 else 659 val = AMS_SUPPLY_SCALE_3VOLT_mV; 660 break; 661 case AMS_SUPPLY8: 662 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 663 if (FIELD_GET(AMS_VUSER1_MASK, regval)) 664 val = AMS_SUPPLY_SCALE_6VOLT_mV; 665 else 666 val = AMS_SUPPLY_SCALE_3VOLT_mV; 667 break; 668 case AMS_SUPPLY9: 669 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 670 if (FIELD_GET(AMS_VUSER2_MASK, regval)) 671 val = AMS_SUPPLY_SCALE_6VOLT_mV; 672 else 673 val = AMS_SUPPLY_SCALE_3VOLT_mV; 674 break; 675 case AMS_SUPPLY10: 676 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 677 if (FIELD_GET(AMS_VUSER3_MASK, regval)) 678 val = AMS_SUPPLY_SCALE_6VOLT_mV; 679 else 680 val = AMS_SUPPLY_SCALE_3VOLT_mV; 681 break; 682 case AMS_VP_VN: 683 case AMS_REG_VAUX(0) ... AMS_REG_VAUX(15): 684 val = AMS_SUPPLY_SCALE_1VOLT_mV; 685 break; 686 default: 687 val = AMS_SUPPLY_SCALE_1VOLT_mV; 688 break; 689 } 690 691 return val; 692 } 693 694 static int ams_get_ctrl_scale(int address) 695 { 696 int val; 697 698 switch (address) { 699 case AMS_VCC_PSPLL0: 700 case AMS_VCC_PSPLL3: 701 case AMS_VCCINT: 702 case AMS_VCCBRAM: 703 case AMS_VCCAUX: 704 case AMS_PSDDRPLL: 705 case AMS_PSINTFPDDR: 706 val = AMS_SUPPLY_SCALE_3VOLT_mV; 707 break; 708 default: 709 val = AMS_SUPPLY_SCALE_1VOLT_mV; 710 break; 711 } 712 713 return val; 714 } 715 716 static int ams_read_raw(struct iio_dev *indio_dev, 717 struct iio_chan_spec const *chan, 718 int *val, int *val2, long mask) 719 { 720 struct ams *ams = iio_priv(indio_dev); 721 int ret; 722 723 switch (mask) { 724 case IIO_CHAN_INFO_RAW: { 725 guard(mutex)(&ams->lock); 726 if (chan->scan_index >= AMS_CTRL_SEQ_BASE) { 727 ret = ams_read_vcc_reg(ams, chan->address, val); 728 if (ret) 729 return ret; 730 ams_enable_channel_sequence(indio_dev); 731 } else if (chan->scan_index >= AMS_PS_SEQ_MAX) 732 *val = readl(ams->pl_base + chan->address); 733 else 734 *val = readl(ams->ps_base + chan->address); 735 736 return IIO_VAL_INT; 737 } 738 case IIO_CHAN_INFO_SCALE: 739 switch (chan->type) { 740 case IIO_VOLTAGE: 741 if (chan->scan_index < AMS_PS_SEQ_MAX) 742 *val = ams_get_ps_scale(chan->address); 743 else if (chan->scan_index >= AMS_PS_SEQ_MAX && 744 chan->scan_index < AMS_CTRL_SEQ_BASE) 745 *val = ams_get_pl_scale(ams, chan->address); 746 else 747 *val = ams_get_ctrl_scale(chan->address); 748 749 *val2 = AMS_SUPPLY_SCALE_DIV_BIT; 750 return IIO_VAL_FRACTIONAL_LOG2; 751 case IIO_TEMP: 752 *val = AMS_TEMP_SCALE; 753 *val2 = AMS_TEMP_SCALE_DIV_BIT; 754 return IIO_VAL_FRACTIONAL_LOG2; 755 default: 756 return -EINVAL; 757 } 758 case IIO_CHAN_INFO_OFFSET: 759 /* Only the temperature channel has an offset */ 760 *val = AMS_TEMP_OFFSET; 761 return IIO_VAL_INT; 762 default: 763 return -EINVAL; 764 } 765 } 766 767 struct ams_alarm_map { 768 enum ams_ps_pl_seq scan_index; 769 unsigned int base_offset; 770 }; 771 772 /* 773 * Array index matches enum ams_alarm_bit. 774 * Entries with base_offset == AMS_ALARM_NONE are unused/invalid 775 * (e.g. RESERVED) and must be skipped. 776 */ 777 static const struct ams_alarm_map alarm_map[] = { 778 [AMS_ALARM_BIT_TEMP] = { AMS_SEQ_TEMP, AMS_ALARM_TEMP }, 779 [AMS_ALARM_BIT_SUPPLY1] = { AMS_SEQ_SUPPLY1, AMS_ALARM_SUPPLY1 }, 780 [AMS_ALARM_BIT_SUPPLY2] = { AMS_SEQ_SUPPLY2, AMS_ALARM_SUPPLY2 }, 781 [AMS_ALARM_BIT_SUPPLY3] = { AMS_SEQ_SUPPLY3, AMS_ALARM_SUPPLY3 }, 782 [AMS_ALARM_BIT_SUPPLY4] = { AMS_SEQ_SUPPLY4, AMS_ALARM_SUPPLY4 }, 783 [AMS_ALARM_BIT_SUPPLY5] = { AMS_SEQ_SUPPLY5, AMS_ALARM_SUPPLY5 }, 784 [AMS_ALARM_BIT_SUPPLY6] = { AMS_SEQ_SUPPLY6, AMS_ALARM_SUPPLY6 }, 785 [AMS_ALARM_BIT_RESERVED] = { 0, AMS_ALARM_NONE }, 786 [AMS_ALARM_BIT_SUPPLY7] = { AMS_SEQ_SUPPLY7, AMS_ALARM_SUPPLY7 }, 787 [AMS_ALARM_BIT_SUPPLY8] = { AMS_SEQ_SUPPLY8, AMS_ALARM_SUPPLY8 }, 788 [AMS_ALARM_BIT_SUPPLY9] = { AMS_SEQ_SUPPLY9, AMS_ALARM_SUPPLY9 }, 789 [AMS_ALARM_BIT_SUPPLY10] = { AMS_SEQ_SUPPLY10, AMS_ALARM_SUPPLY10 }, 790 [AMS_ALARM_BIT_VCCAMS] = { AMS_SEQ_VCCAMS, AMS_ALARM_VCCAMS }, 791 [AMS_ALARM_BIT_TEMP_REMOTE] = { AMS_SEQ_TEMP_REMOTE, AMS_ALARM_TEMP_REMOTE }, 792 }; 793 794 static int ams_scan_index_to_event(int scan_index) 795 { 796 for (unsigned int i = 0; i < ARRAY_SIZE(alarm_map); i++) { 797 if (alarm_map[i].base_offset == AMS_ALARM_NONE) 798 continue; 799 800 if (alarm_map[i].scan_index == scan_index) 801 return i; 802 } 803 804 return -EINVAL; 805 } 806 807 static int ams_get_alarm_offset(int scan_index, enum iio_event_direction dir) 808 { 809 int offset, event; 810 811 if (scan_index >= AMS_PS_SEQ_MAX) 812 scan_index -= AMS_PS_SEQ_MAX; 813 814 if (dir == IIO_EV_DIR_FALLING) { 815 if (scan_index < AMS_SEQ_SUPPLY7) 816 offset = AMS_ALARM_THRESHOLD_OFF_10; 817 else 818 offset = AMS_ALARM_THRESHOLD_OFF_20; 819 } else { 820 offset = 0; 821 } 822 823 event = ams_scan_index_to_event(scan_index); 824 if (event < 0 || alarm_map[event].base_offset == AMS_ALARM_NONE) 825 return 0; 826 827 return alarm_map[event].base_offset + offset; 828 } 829 830 static const struct iio_chan_spec *ams_event_to_channel(struct iio_dev *dev, 831 u32 event) 832 { 833 int scan_index = 0, i; 834 835 if (event >= AMS_PL_ALARM_START) { 836 event -= AMS_PL_ALARM_START; 837 scan_index = AMS_PS_SEQ_MAX; 838 } 839 840 if (event >= ARRAY_SIZE(alarm_map)) 841 return NULL; 842 843 if (alarm_map[event].base_offset == AMS_ALARM_NONE) 844 return NULL; 845 846 scan_index += alarm_map[event].scan_index; 847 848 for (i = 0; i < dev->num_channels; i++) 849 if (dev->channels[i].scan_index == scan_index) 850 break; 851 852 if (i == dev->num_channels) 853 return NULL; 854 855 return &dev->channels[i]; 856 } 857 858 static int ams_get_alarm_mask(int scan_index) 859 { 860 int bit = 0, event; 861 862 if (scan_index >= AMS_PS_SEQ_MAX) { 863 bit = AMS_PL_ALARM_START; 864 scan_index -= AMS_PS_SEQ_MAX; 865 } 866 867 event = ams_scan_index_to_event(scan_index); 868 if (event < 0) 869 return 0; 870 871 return BIT(event + bit); 872 } 873 874 static int ams_read_event_config(struct iio_dev *indio_dev, 875 const struct iio_chan_spec *chan, 876 enum iio_event_type type, 877 enum iio_event_direction dir) 878 { 879 struct ams *ams = iio_priv(indio_dev); 880 881 return !!(ams->alarm_mask & ams_get_alarm_mask(chan->scan_index)); 882 } 883 884 static int ams_write_event_config(struct iio_dev *indio_dev, 885 const struct iio_chan_spec *chan, 886 enum iio_event_type type, 887 enum iio_event_direction dir, 888 bool state) 889 { 890 struct ams *ams = iio_priv(indio_dev); 891 unsigned int alarm; 892 893 alarm = ams_get_alarm_mask(chan->scan_index); 894 895 guard(mutex)(&ams->lock); 896 897 if (state) 898 ams->alarm_mask |= alarm; 899 else 900 ams->alarm_mask &= ~alarm; 901 902 ams_update_alarm(ams, ams->alarm_mask); 903 904 return 0; 905 } 906 907 static int ams_read_event_value(struct iio_dev *indio_dev, 908 const struct iio_chan_spec *chan, 909 enum iio_event_type type, 910 enum iio_event_direction dir, 911 enum iio_event_info info, int *val, int *val2) 912 { 913 struct ams *ams = iio_priv(indio_dev); 914 unsigned int offset = ams_get_alarm_offset(chan->scan_index, dir); 915 916 guard(mutex)(&ams->lock); 917 918 if (chan->scan_index >= AMS_PS_SEQ_MAX) 919 *val = readl(ams->pl_base + offset); 920 else 921 *val = readl(ams->ps_base + offset); 922 923 return IIO_VAL_INT; 924 } 925 926 static int ams_write_event_value(struct iio_dev *indio_dev, 927 const struct iio_chan_spec *chan, 928 enum iio_event_type type, 929 enum iio_event_direction dir, 930 enum iio_event_info info, int val, int val2) 931 { 932 struct ams *ams = iio_priv(indio_dev); 933 unsigned int offset; 934 935 guard(mutex)(&ams->lock); 936 937 /* Set temperature channel threshold to direct threshold */ 938 if (chan->type == IIO_TEMP) { 939 offset = ams_get_alarm_offset(chan->scan_index, IIO_EV_DIR_FALLING); 940 941 if (chan->scan_index >= AMS_PS_SEQ_MAX) 942 ams_pl_update_reg(ams, offset, 943 AMS_ALARM_THR_DIRECT_MASK, 944 AMS_ALARM_THR_DIRECT_MASK); 945 else 946 ams_ps_update_reg(ams, offset, 947 AMS_ALARM_THR_DIRECT_MASK, 948 AMS_ALARM_THR_DIRECT_MASK); 949 } 950 951 offset = ams_get_alarm_offset(chan->scan_index, dir); 952 if (chan->scan_index >= AMS_PS_SEQ_MAX) 953 writel(val, ams->pl_base + offset); 954 else 955 writel(val, ams->ps_base + offset); 956 957 return 0; 958 } 959 960 static void ams_handle_event(struct iio_dev *indio_dev, u32 event) 961 { 962 const struct iio_chan_spec *chan; 963 964 chan = ams_event_to_channel(indio_dev, event); 965 if (!chan) 966 return; 967 968 if (chan->type == IIO_TEMP) { 969 /* 970 * The temperature channel only supports over-temperature 971 * events. 972 */ 973 iio_push_event(indio_dev, 974 IIO_UNMOD_EVENT_CODE(chan->type, chan->channel, 975 IIO_EV_TYPE_THRESH, 976 IIO_EV_DIR_RISING), 977 iio_get_time_ns(indio_dev)); 978 } else { 979 /* 980 * For other channels we don't know whether it is a upper or 981 * lower threshold event. Userspace will have to check the 982 * channel value if it wants to know. 983 */ 984 iio_push_event(indio_dev, 985 IIO_UNMOD_EVENT_CODE(chan->type, chan->channel, 986 IIO_EV_TYPE_THRESH, 987 IIO_EV_DIR_EITHER), 988 iio_get_time_ns(indio_dev)); 989 } 990 } 991 992 static void ams_handle_events(struct iio_dev *indio_dev, unsigned long events) 993 { 994 unsigned int bit; 995 996 for_each_set_bit(bit, &events, AMS_NO_OF_ALARMS) 997 ams_handle_event(indio_dev, bit); 998 } 999 1000 /** 1001 * ams_unmask_worker - ams alarm interrupt unmask worker 1002 * @work: work to be done 1003 * 1004 * The ZynqMP threshold interrupts are level sensitive. Since we can't make the 1005 * threshold condition go way from within the interrupt handler, this means as 1006 * soon as a threshold condition is present we would enter the interrupt handler 1007 * again and again. To work around this we mask all active threshold interrupts 1008 * in the interrupt handler and start a timer. In this timer we poll the 1009 * interrupt status and only if the interrupt is inactive we unmask it again. 1010 */ 1011 static void ams_unmask_worker(struct work_struct *work) 1012 { 1013 struct ams *ams = container_of(work, struct ams, ams_unmask_work.work); 1014 1015 spin_lock_irq(&ams->intr_lock); 1016 ams_unmask(ams); 1017 spin_unlock_irq(&ams->intr_lock); 1018 1019 /* If still pending some alarm re-trigger the timer */ 1020 if (ams->current_masked_alarm) 1021 schedule_delayed_work(&ams->ams_unmask_work, 1022 msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS)); 1023 } 1024 1025 static irqreturn_t ams_irq(int irq, void *data) 1026 { 1027 struct iio_dev *indio_dev = data; 1028 struct ams *ams = iio_priv(indio_dev); 1029 u32 isr0; 1030 1031 spin_lock(&ams->intr_lock); 1032 1033 isr0 = readl(ams->base + AMS_ISR_0); 1034 1035 /* Only process alarms that are not masked */ 1036 isr0 &= ~((ams->intr_mask & AMS_ISR0_ALARM_MASK) | ams->current_masked_alarm); 1037 if (!isr0) { 1038 spin_unlock(&ams->intr_lock); 1039 return IRQ_NONE; 1040 } 1041 1042 /* Clear interrupt */ 1043 writel(isr0, ams->base + AMS_ISR_0); 1044 1045 /* Mask the alarm interrupts until cleared */ 1046 ams->current_masked_alarm |= isr0; 1047 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK); 1048 1049 ams_handle_events(indio_dev, isr0); 1050 1051 schedule_delayed_work(&ams->ams_unmask_work, 1052 msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS)); 1053 1054 spin_unlock(&ams->intr_lock); 1055 1056 return IRQ_HANDLED; 1057 } 1058 1059 static const struct iio_event_spec ams_temp_events[] = { 1060 { 1061 .type = IIO_EV_TYPE_THRESH, 1062 .dir = IIO_EV_DIR_RISING, 1063 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE), 1064 }, 1065 }; 1066 1067 static const struct iio_event_spec ams_voltage_events[] = { 1068 { 1069 .type = IIO_EV_TYPE_THRESH, 1070 .dir = IIO_EV_DIR_RISING, 1071 .mask_separate = BIT(IIO_EV_INFO_VALUE), 1072 }, 1073 { 1074 .type = IIO_EV_TYPE_THRESH, 1075 .dir = IIO_EV_DIR_FALLING, 1076 .mask_separate = BIT(IIO_EV_INFO_VALUE), 1077 }, 1078 { 1079 .type = IIO_EV_TYPE_THRESH, 1080 .dir = IIO_EV_DIR_EITHER, 1081 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1082 }, 1083 }; 1084 1085 static const struct iio_chan_spec ams_ps_channels[] = { 1086 AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP, "Temp_LPD"), 1087 AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP_REMOTE, AMS_TEMP_REMOTE, "Temp_FPD"), 1088 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1, "VCC_PSINTLP"), 1089 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2, "VCC_PSINTFP"), 1090 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3, "VCC_PSAUX"), 1091 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4, "VCC_PSDDR"), 1092 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5, "VCC_PSIO3"), 1093 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6, "VCC_PSIO0"), 1094 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7, "VCC_PSIO1"), 1095 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8, "VCC_PSIO2"), 1096 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9, "PS_MGTRAVCC"), 1097 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10, "PS_MGTRAVTT"), 1098 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS, "VCC_PSADC"), 1099 }; 1100 1101 static const struct iio_chan_spec ams_pl_channels[] = { 1102 AMS_PL_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP, "Temp_PL"), 1103 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1, true, "VCCINT"), 1104 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2, true, "VCCAUX"), 1105 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFP, AMS_VREFP, false, "VREFP"), 1106 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFN, AMS_VREFN, false, "VREFN"), 1107 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3, true, "VCCBRAM"), 1108 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4, true, "VCC_PSINTLP"), 1109 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5, true, "VCC_PSINTFP"), 1110 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6, true, "VCC_PSAUX"), 1111 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS, true, "VCCAMS"), 1112 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VP_VN, AMS_VP_VN, false, "VP_VN"), 1113 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7, true, "VUser0"), 1114 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8, true, "VUser1"), 1115 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9, true, "VUser2"), 1116 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10, true, "VUser3"), 1117 AMS_PL_AUX_CHAN_VOLTAGE(0), 1118 AMS_PL_AUX_CHAN_VOLTAGE(1), 1119 AMS_PL_AUX_CHAN_VOLTAGE(2), 1120 AMS_PL_AUX_CHAN_VOLTAGE(3), 1121 AMS_PL_AUX_CHAN_VOLTAGE(4), 1122 AMS_PL_AUX_CHAN_VOLTAGE(5), 1123 AMS_PL_AUX_CHAN_VOLTAGE(6), 1124 AMS_PL_AUX_CHAN_VOLTAGE(7), 1125 AMS_PL_AUX_CHAN_VOLTAGE(8), 1126 AMS_PL_AUX_CHAN_VOLTAGE(9), 1127 AMS_PL_AUX_CHAN_VOLTAGE(10), 1128 AMS_PL_AUX_CHAN_VOLTAGE(11), 1129 AMS_PL_AUX_CHAN_VOLTAGE(12), 1130 AMS_PL_AUX_CHAN_VOLTAGE(13), 1131 AMS_PL_AUX_CHAN_VOLTAGE(14), 1132 AMS_PL_AUX_CHAN_VOLTAGE(15), 1133 }; 1134 1135 static const struct iio_chan_spec ams_ctrl_channels[] = { 1136 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSPLL, AMS_VCC_PSPLL0, "VCC_PSPLL"), 1137 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSBATT, AMS_VCC_PSPLL3, "VCC_PSBATT"), 1138 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCINT, AMS_VCCINT, "VCCINT"), 1139 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCBRAM, AMS_VCCBRAM, "VCCBRAM"), 1140 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCAUX, AMS_VCCAUX, "VCCAUX"), 1141 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_PSDDRPLL, AMS_PSDDRPLL, "VCC_PSDDR_PLL"), 1142 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_INTDDR, AMS_PSINTFPDDR, "VCC_PSINTFP_DDR"), 1143 }; 1144 1145 static int ams_get_ext_chan(struct fwnode_handle *chan_node, 1146 struct iio_chan_spec *channels, int num_channels) 1147 { 1148 struct iio_chan_spec *chan; 1149 struct fwnode_handle *child; 1150 unsigned int reg, ext_chan; 1151 int ret; 1152 1153 fwnode_for_each_child_node(chan_node, child) { 1154 ret = fwnode_property_read_u32(child, "reg", ®); 1155 if (ret || reg > AMS_PL_MAX_EXT_CHANNEL + 30) 1156 continue; 1157 1158 chan = &channels[num_channels]; 1159 ext_chan = reg + AMS_PL_MAX_FIXED_CHANNEL - 30; 1160 memcpy(chan, &ams_pl_channels[ext_chan], sizeof(*channels)); 1161 1162 if (fwnode_property_read_bool(child, "xlnx,bipolar")) 1163 chan->scan_type.sign = 's'; 1164 1165 num_channels++; 1166 } 1167 1168 return num_channels; 1169 } 1170 1171 static void ams_iounmap_ps(void *data) 1172 { 1173 struct ams *ams = data; 1174 1175 iounmap(ams->ps_base); 1176 } 1177 1178 static void ams_iounmap_pl(void *data) 1179 { 1180 struct ams *ams = data; 1181 1182 iounmap(ams->pl_base); 1183 } 1184 1185 static int ams_init_module(struct iio_dev *indio_dev, 1186 struct fwnode_handle *fwnode, 1187 struct iio_chan_spec *channels) 1188 { 1189 struct device *dev = indio_dev->dev.parent; 1190 struct ams *ams = iio_priv(indio_dev); 1191 int num_channels = 0; 1192 int ret; 1193 1194 if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-ps")) { 1195 ams->ps_base = fwnode_iomap(fwnode, 0); 1196 if (!ams->ps_base) 1197 return -ENXIO; 1198 ret = devm_add_action_or_reset(dev, ams_iounmap_ps, ams); 1199 if (ret < 0) 1200 return ret; 1201 1202 /* add PS channels to iio device channels */ 1203 memcpy(channels, ams_ps_channels, sizeof(ams_ps_channels)); 1204 num_channels = ARRAY_SIZE(ams_ps_channels); 1205 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-pl")) { 1206 ams->pl_base = fwnode_iomap(fwnode, 0); 1207 if (!ams->pl_base) 1208 return -ENXIO; 1209 1210 ret = devm_add_action_or_reset(dev, ams_iounmap_pl, ams); 1211 if (ret < 0) 1212 return ret; 1213 1214 /* Copy only first 10 fix channels */ 1215 memcpy(channels, ams_pl_channels, AMS_PL_MAX_FIXED_CHANNEL * sizeof(*channels)); 1216 num_channels += AMS_PL_MAX_FIXED_CHANNEL; 1217 num_channels = ams_get_ext_chan(fwnode, channels, 1218 num_channels); 1219 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams")) { 1220 /* add AMS channels to iio device channels */ 1221 memcpy(channels, ams_ctrl_channels, sizeof(ams_ctrl_channels)); 1222 num_channels += ARRAY_SIZE(ams_ctrl_channels); 1223 } else { 1224 return -EINVAL; 1225 } 1226 1227 return num_channels; 1228 } 1229 1230 static int ams_parse_firmware(struct iio_dev *indio_dev) 1231 { 1232 struct ams *ams = iio_priv(indio_dev); 1233 struct iio_chan_spec *ams_channels, *dev_channels; 1234 struct device *dev = indio_dev->dev.parent; 1235 struct fwnode_handle *fwnode = dev_fwnode(dev); 1236 size_t ams_size; 1237 int ret, ch_cnt = 0, i, rising_off, falling_off; 1238 unsigned int num_channels = 0; 1239 1240 ams_size = ARRAY_SIZE(ams_ps_channels) + ARRAY_SIZE(ams_pl_channels) + 1241 ARRAY_SIZE(ams_ctrl_channels); 1242 1243 /* Initialize buffer for channel specification */ 1244 ams_channels = devm_kcalloc(dev, ams_size, sizeof(*ams_channels), GFP_KERNEL); 1245 if (!ams_channels) 1246 return -ENOMEM; 1247 1248 if (fwnode_device_is_available(fwnode)) { 1249 ret = ams_init_module(indio_dev, fwnode, ams_channels); 1250 if (ret < 0) 1251 return ret; 1252 1253 num_channels += ret; 1254 } 1255 1256 device_for_each_child_node_scoped(dev, child) { 1257 ret = ams_init_module(indio_dev, child, ams_channels + num_channels); 1258 if (ret < 0) 1259 return ret; 1260 1261 num_channels += ret; 1262 } 1263 1264 for (i = 0; i < num_channels; i++) { 1265 ams_channels[i].channel = ch_cnt++; 1266 1267 if (ams_channels[i].scan_index < AMS_CTRL_SEQ_BASE) { 1268 /* set threshold to max and min for each channel */ 1269 falling_off = 1270 ams_get_alarm_offset(ams_channels[i].scan_index, 1271 IIO_EV_DIR_FALLING); 1272 rising_off = 1273 ams_get_alarm_offset(ams_channels[i].scan_index, 1274 IIO_EV_DIR_RISING); 1275 if (ams_channels[i].scan_index >= AMS_PS_SEQ_MAX) { 1276 writel(AMS_ALARM_THR_MIN, 1277 ams->pl_base + falling_off); 1278 writel(AMS_ALARM_THR_MAX, 1279 ams->pl_base + rising_off); 1280 } else { 1281 writel(AMS_ALARM_THR_MIN, 1282 ams->ps_base + falling_off); 1283 writel(AMS_ALARM_THR_MAX, 1284 ams->ps_base + rising_off); 1285 } 1286 } 1287 } 1288 1289 dev_channels = devm_krealloc_array(dev, ams_channels, num_channels, 1290 sizeof(*dev_channels), GFP_KERNEL); 1291 if (!dev_channels) 1292 return -ENOMEM; 1293 1294 indio_dev->channels = dev_channels; 1295 indio_dev->num_channels = num_channels; 1296 1297 return 0; 1298 } 1299 1300 static const struct iio_info iio_ams_info = { 1301 .read_label = ams_read_label, 1302 .read_raw = &ams_read_raw, 1303 .read_event_config = &ams_read_event_config, 1304 .write_event_config = &ams_write_event_config, 1305 .read_event_value = &ams_read_event_value, 1306 .write_event_value = &ams_write_event_value, 1307 }; 1308 1309 static const struct of_device_id ams_of_match_table[] = { 1310 { .compatible = "xlnx,zynqmp-ams" }, 1311 { } 1312 }; 1313 MODULE_DEVICE_TABLE(of, ams_of_match_table); 1314 1315 static int ams_probe(struct platform_device *pdev) 1316 { 1317 struct iio_dev *indio_dev; 1318 struct ams *ams; 1319 int ret; 1320 int irq; 1321 1322 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ams)); 1323 if (!indio_dev) 1324 return -ENOMEM; 1325 1326 ams = iio_priv(indio_dev); 1327 mutex_init(&ams->lock); 1328 spin_lock_init(&ams->intr_lock); 1329 1330 indio_dev->name = "xilinx-ams"; 1331 1332 indio_dev->info = &iio_ams_info; 1333 indio_dev->modes = INDIO_DIRECT_MODE; 1334 1335 ams->base = devm_platform_ioremap_resource(pdev, 0); 1336 if (IS_ERR(ams->base)) 1337 return PTR_ERR(ams->base); 1338 1339 ams->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1340 if (IS_ERR(ams->clk)) 1341 return PTR_ERR(ams->clk); 1342 1343 ret = devm_delayed_work_autocancel(&pdev->dev, &ams->ams_unmask_work, 1344 ams_unmask_worker); 1345 if (ret < 0) 1346 return ret; 1347 1348 ret = ams_parse_firmware(indio_dev); 1349 if (ret) 1350 return dev_err_probe(&pdev->dev, ret, "failure in parsing DT\n"); 1351 1352 ret = ams_init_device(ams); 1353 if (ret) 1354 return dev_err_probe(&pdev->dev, ret, "failed to initialize AMS\n"); 1355 1356 ams_enable_channel_sequence(indio_dev); 1357 1358 irq = platform_get_irq(pdev, 0); 1359 if (irq < 0) 1360 return irq; 1361 1362 ret = devm_request_irq(&pdev->dev, irq, &ams_irq, 0, "ams-irq", 1363 indio_dev); 1364 if (ret < 0) 1365 return dev_err_probe(&pdev->dev, ret, "failed to register interrupt\n"); 1366 1367 platform_set_drvdata(pdev, indio_dev); 1368 1369 return devm_iio_device_register(&pdev->dev, indio_dev); 1370 } 1371 1372 static int ams_suspend(struct device *dev) 1373 { 1374 struct ams *ams = iio_priv(dev_get_drvdata(dev)); 1375 1376 clk_disable_unprepare(ams->clk); 1377 1378 return 0; 1379 } 1380 1381 static int ams_resume(struct device *dev) 1382 { 1383 struct ams *ams = iio_priv(dev_get_drvdata(dev)); 1384 1385 return clk_prepare_enable(ams->clk); 1386 } 1387 1388 static DEFINE_SIMPLE_DEV_PM_OPS(ams_pm_ops, ams_suspend, ams_resume); 1389 1390 static struct platform_driver ams_driver = { 1391 .probe = ams_probe, 1392 .driver = { 1393 .name = "xilinx-ams", 1394 .pm = pm_sleep_ptr(&ams_pm_ops), 1395 .of_match_table = ams_of_match_table, 1396 }, 1397 }; 1398 module_platform_driver(ams_driver); 1399 1400 MODULE_DESCRIPTION("Xilinx AMS driver"); 1401 MODULE_LICENSE("GPL v2"); 1402 MODULE_AUTHOR("Xilinx, Inc."); 1403