1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx AMS driver 4 * 5 * Copyright (C) 2021 Xilinx, Inc. 6 * 7 * Manish Narani <mnarani@xilinx.com> 8 * Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> 9 */ 10 11 #include <linux/bits.h> 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/devm-helpers.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/overflow.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 #include <linux/slab.h> 26 27 #include <linux/iio/events.h> 28 #include <linux/iio/iio.h> 29 30 /* AMS registers definitions */ 31 #define AMS_ISR_0 0x010 32 #define AMS_ISR_1 0x014 33 #define AMS_IER_0 0x020 34 #define AMS_IER_1 0x024 35 #define AMS_IDR_0 0x028 36 #define AMS_IDR_1 0x02C 37 #define AMS_PS_CSTS 0x040 38 #define AMS_PL_CSTS 0x044 39 40 #define AMS_VCC_PSPLL0 0x060 41 #define AMS_VCC_PSPLL3 0x06C 42 #define AMS_VCCINT 0x078 43 #define AMS_VCCBRAM 0x07C 44 #define AMS_VCCAUX 0x080 45 #define AMS_PSDDRPLL 0x084 46 #define AMS_PSINTFPDDR 0x09C 47 48 #define AMS_VCC_PSPLL0_CH 48 49 #define AMS_VCC_PSPLL3_CH 51 50 #define AMS_VCCINT_CH 54 51 #define AMS_VCCBRAM_CH 55 52 #define AMS_VCCAUX_CH 56 53 #define AMS_PSDDRPLL_CH 57 54 #define AMS_PSINTFPDDR_CH 63 55 56 #define AMS_REG_CONFIG0 0x100 57 #define AMS_REG_CONFIG1 0x104 58 #define AMS_REG_CONFIG3 0x10C 59 #define AMS_REG_CONFIG4 0x110 60 #define AMS_REG_SEQ_CH0 0x120 61 #define AMS_REG_SEQ_CH1 0x124 62 #define AMS_REG_SEQ_CH2 0x118 63 64 #define AMS_VUSER0_MASK BIT(0) 65 #define AMS_VUSER1_MASK BIT(1) 66 #define AMS_VUSER2_MASK BIT(2) 67 #define AMS_VUSER3_MASK BIT(3) 68 69 #define AMS_TEMP 0x000 70 #define AMS_SUPPLY1 0x004 71 #define AMS_SUPPLY2 0x008 72 #define AMS_VP_VN 0x00C 73 #define AMS_VREFP 0x010 74 #define AMS_VREFN 0x014 75 #define AMS_SUPPLY3 0x018 76 #define AMS_SUPPLY4 0x034 77 #define AMS_SUPPLY5 0x038 78 #define AMS_SUPPLY6 0x03C 79 #define AMS_SUPPLY7 0x200 80 #define AMS_SUPPLY8 0x204 81 #define AMS_SUPPLY9 0x208 82 #define AMS_SUPPLY10 0x20C 83 #define AMS_VCCAMS 0x210 84 #define AMS_TEMP_REMOTE 0x214 85 86 #define AMS_REG_VAUX(x) (0x40 + 4 * (x)) 87 88 #define AMS_PS_RESET_VALUE 0xFFFF 89 #define AMS_PL_RESET_VALUE 0xFFFF 90 91 #define AMS_CONF0_CHANNEL_NUM_MASK GENMASK(6, 0) 92 93 #define AMS_CONF1_SEQ_MASK GENMASK(15, 12) 94 #define AMS_CONF1_SEQ_DEFAULT FIELD_PREP(AMS_CONF1_SEQ_MASK, 0) 95 #define AMS_CONF1_SEQ_CONTINUOUS FIELD_PREP(AMS_CONF1_SEQ_MASK, 2) 96 #define AMS_CONF1_SEQ_SINGLE_CHANNEL FIELD_PREP(AMS_CONF1_SEQ_MASK, 3) 97 98 #define AMS_REG_SEQ0_MASK GENMASK(15, 0) 99 #define AMS_REG_SEQ2_MASK GENMASK(21, 16) 100 #define AMS_REG_SEQ1_MASK GENMASK_ULL(37, 22) 101 102 #define AMS_PS_SEQ_MASK GENMASK(21, 0) 103 #define AMS_PL_SEQ_MASK GENMASK_ULL(59, 22) 104 105 #define AMS_ALARM_TEMP 0x140 106 #define AMS_ALARM_SUPPLY1 0x144 107 #define AMS_ALARM_SUPPLY2 0x148 108 #define AMS_ALARM_SUPPLY3 0x160 109 #define AMS_ALARM_SUPPLY4 0x164 110 #define AMS_ALARM_SUPPLY5 0x168 111 #define AMS_ALARM_SUPPLY6 0x16C 112 #define AMS_ALARM_SUPPLY7 0x180 113 #define AMS_ALARM_SUPPLY8 0x184 114 #define AMS_ALARM_SUPPLY9 0x188 115 #define AMS_ALARM_SUPPLY10 0x18C 116 #define AMS_ALARM_VCCAMS 0x190 117 #define AMS_ALARM_TEMP_REMOTE 0x194 118 #define AMS_ALARM_THRESHOLD_OFF_10 0x10 119 #define AMS_ALARM_THRESHOLD_OFF_20 0x20 120 121 #define AMS_ALARM_THR_DIRECT_MASK BIT(1) 122 #define AMS_ALARM_THR_MIN 0x0000 123 #define AMS_ALARM_THR_MAX (BIT(16) - 1) 124 125 #define AMS_ALARM_MASK GENMASK_ULL(63, 0) 126 #define AMS_NO_OF_ALARMS 32 127 #define AMS_PL_ALARM_START 16 128 #define AMS_PL_ALARM_MASK GENMASK(31, 16) 129 #define AMS_ISR0_ALARM_MASK GENMASK(31, 0) 130 #define AMS_ISR1_ALARM_MASK (GENMASK(31, 29) | GENMASK(4, 0)) 131 #define AMS_ISR1_EOC_MASK BIT(3) 132 #define AMS_ISR1_INTR_MASK GENMASK_ULL(63, 32) 133 #define AMS_ISR0_ALARM_2_TO_0_MASK GENMASK(2, 0) 134 #define AMS_ISR0_ALARM_6_TO_3_MASK GENMASK(6, 3) 135 #define AMS_ISR0_ALARM_12_TO_7_MASK GENMASK(13, 8) 136 #define AMS_CONF1_ALARM_2_TO_0_MASK GENMASK(3, 1) 137 #define AMS_CONF1_ALARM_6_TO_3_MASK GENMASK(11, 8) 138 #define AMS_CONF1_ALARM_12_TO_7_MASK GENMASK(5, 0) 139 #define AMS_REGCFG1_ALARM_MASK \ 140 (AMS_CONF1_ALARM_2_TO_0_MASK | AMS_CONF1_ALARM_6_TO_3_MASK | BIT(0)) 141 #define AMS_REGCFG3_ALARM_MASK AMS_CONF1_ALARM_12_TO_7_MASK 142 143 #define AMS_PS_CSTS_PS_READY (BIT(27) | BIT(16)) 144 #define AMS_PL_CSTS_ACCESS_MASK BIT(1) 145 146 #define AMS_PL_MAX_FIXED_CHANNEL 10 147 #define AMS_PL_MAX_EXT_CHANNEL 20 148 149 #define AMS_INIT_POLL_TIME_US 200 150 #define AMS_INIT_TIMEOUT_US 10000 151 #define AMS_UNMASK_TIMEOUT_MS 500 152 153 /* 154 * Following scale and offset value is derived from 155 * UG580 (v1.7) December 20, 2016 156 */ 157 #define AMS_SUPPLY_SCALE_1VOLT_mV 1000 158 #define AMS_SUPPLY_SCALE_3VOLT_mV 3000 159 #define AMS_SUPPLY_SCALE_6VOLT_mV 6000 160 #define AMS_SUPPLY_SCALE_DIV_BIT 16 161 162 #define AMS_TEMP_SCALE 509314 163 #define AMS_TEMP_SCALE_DIV_BIT 16 164 #define AMS_TEMP_OFFSET -((280230LL << 16) / 509314) 165 166 enum ams_alarm_bit { 167 AMS_ALARM_BIT_TEMP = 0, 168 AMS_ALARM_BIT_SUPPLY1 = 1, 169 AMS_ALARM_BIT_SUPPLY2 = 2, 170 AMS_ALARM_BIT_SUPPLY3 = 3, 171 AMS_ALARM_BIT_SUPPLY4 = 4, 172 AMS_ALARM_BIT_SUPPLY5 = 5, 173 AMS_ALARM_BIT_SUPPLY6 = 6, 174 AMS_ALARM_BIT_RESERVED = 7, 175 AMS_ALARM_BIT_SUPPLY7 = 8, 176 AMS_ALARM_BIT_SUPPLY8 = 9, 177 AMS_ALARM_BIT_SUPPLY9 = 10, 178 AMS_ALARM_BIT_SUPPLY10 = 11, 179 AMS_ALARM_BIT_VCCAMS = 12, 180 AMS_ALARM_BIT_TEMP_REMOTE = 13, 181 }; 182 183 enum ams_seq { 184 AMS_SEQ_VCC_PSPLL = 0, 185 AMS_SEQ_VCC_PSBATT = 1, 186 AMS_SEQ_VCCINT = 2, 187 AMS_SEQ_VCCBRAM = 3, 188 AMS_SEQ_VCCAUX = 4, 189 AMS_SEQ_PSDDRPLL = 5, 190 AMS_SEQ_INTDDR = 6, 191 }; 192 193 enum ams_ps_pl_seq { 194 AMS_SEQ_CALIB = 0, 195 AMS_SEQ_RSVD_1 = 1, 196 AMS_SEQ_RSVD_2 = 2, 197 AMS_SEQ_TEST = 3, 198 AMS_SEQ_RSVD_4 = 4, 199 AMS_SEQ_SUPPLY4 = 5, 200 AMS_SEQ_SUPPLY5 = 6, 201 AMS_SEQ_SUPPLY6 = 7, 202 AMS_SEQ_TEMP = 8, 203 AMS_SEQ_SUPPLY2 = 9, 204 AMS_SEQ_SUPPLY1 = 10, 205 AMS_SEQ_VP_VN = 11, 206 AMS_SEQ_VREFP = 12, 207 AMS_SEQ_VREFN = 13, 208 AMS_SEQ_SUPPLY3 = 14, 209 AMS_SEQ_CURRENT_MON = 15, 210 AMS_SEQ_SUPPLY7 = 16, 211 AMS_SEQ_SUPPLY8 = 17, 212 AMS_SEQ_SUPPLY9 = 18, 213 AMS_SEQ_SUPPLY10 = 19, 214 AMS_SEQ_VCCAMS = 20, 215 AMS_SEQ_TEMP_REMOTE = 21, 216 AMS_SEQ_MAX = 22 217 }; 218 219 #define AMS_PS_SEQ_MAX AMS_SEQ_MAX 220 #define AMS_SEQ(x) (AMS_SEQ_MAX + (x)) 221 #define PS_SEQ(x) (x) 222 #define PL_SEQ(x) (AMS_PS_SEQ_MAX + (x)) 223 #define AMS_CTRL_SEQ_BASE (AMS_PS_SEQ_MAX * 3) 224 225 #define AMS_CHAN_TEMP(_scan_index, _addr, _name) { \ 226 .type = IIO_TEMP, \ 227 .indexed = 1, \ 228 .address = (_addr), \ 229 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 230 BIT(IIO_CHAN_INFO_SCALE) | \ 231 BIT(IIO_CHAN_INFO_OFFSET), \ 232 .event_spec = ams_temp_events, \ 233 .scan_index = _scan_index, \ 234 .num_event_specs = ARRAY_SIZE(ams_temp_events), \ 235 .datasheet_name = _name, \ 236 } 237 238 #define AMS_CHAN_VOLTAGE(_scan_index, _addr, _alarm, _name) { \ 239 .type = IIO_VOLTAGE, \ 240 .indexed = 1, \ 241 .address = (_addr), \ 242 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 243 BIT(IIO_CHAN_INFO_SCALE), \ 244 .event_spec = (_alarm) ? ams_voltage_events : NULL, \ 245 .scan_index = _scan_index, \ 246 .num_event_specs = (_alarm) ? ARRAY_SIZE(ams_voltage_events) : 0, \ 247 .datasheet_name = _name, \ 248 } 249 250 #define AMS_PS_CHAN_TEMP(_scan_index, _addr, _name) \ 251 AMS_CHAN_TEMP(PS_SEQ(_scan_index), _addr, _name) 252 #define AMS_PS_CHAN_VOLTAGE(_scan_index, _addr, _name) \ 253 AMS_CHAN_VOLTAGE(PS_SEQ(_scan_index), _addr, true, _name) 254 255 #define AMS_PL_CHAN_TEMP(_scan_index, _addr, _name) \ 256 AMS_CHAN_TEMP(PL_SEQ(_scan_index), _addr, _name) 257 #define AMS_PL_CHAN_VOLTAGE(_scan_index, _addr, _alarm, _name) \ 258 AMS_CHAN_VOLTAGE(PL_SEQ(_scan_index), _addr, _alarm, _name) 259 #define AMS_PL_AUX_CHAN_VOLTAGE(_auxno) \ 260 AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(_auxno)), AMS_REG_VAUX(_auxno), false, \ 261 "VAUX" #_auxno) 262 #define AMS_CTRL_CHAN_VOLTAGE(_scan_index, _addr, _name) \ 263 AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(AMS_SEQ(_scan_index))), _addr, false, \ 264 _name) 265 266 /** 267 * struct ams - This structure contains necessary state for xilinx-ams to operate 268 * @base: physical base address of device 269 * @ps_base: physical base address of PS device 270 * @pl_base: physical base address of PL device 271 * @clk: clocks associated with the device 272 * @dev: pointer to device struct 273 * @lock: to handle multiple user interaction 274 * @intr_lock: to protect interrupt mask values 275 * @alarm_mask: alarm configuration 276 * @current_masked_alarm: currently masked due to alarm 277 * @intr_mask: interrupt configuration 278 * @ams_unmask_work: re-enables event once the event condition disappears 279 * 280 */ 281 struct ams { 282 void __iomem *base; 283 void __iomem *ps_base; 284 void __iomem *pl_base; 285 struct clk *clk; 286 struct device *dev; 287 struct mutex lock; 288 spinlock_t intr_lock; 289 unsigned int alarm_mask; 290 unsigned int current_masked_alarm; 291 u64 intr_mask; 292 struct delayed_work ams_unmask_work; 293 }; 294 295 static inline void ams_ps_update_reg(struct ams *ams, unsigned int offset, 296 u32 mask, u32 data) 297 { 298 u32 val, regval; 299 300 val = readl(ams->ps_base + offset); 301 regval = (val & ~mask) | (data & mask); 302 writel(regval, ams->ps_base + offset); 303 } 304 305 static inline void ams_pl_update_reg(struct ams *ams, unsigned int offset, 306 u32 mask, u32 data) 307 { 308 u32 val, regval; 309 310 val = readl(ams->pl_base + offset); 311 regval = (val & ~mask) | (data & mask); 312 writel(regval, ams->pl_base + offset); 313 } 314 315 static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val) 316 { 317 u32 regval; 318 319 ams->intr_mask = (ams->intr_mask & ~mask) | (val & mask); 320 321 regval = ~(ams->intr_mask | ams->current_masked_alarm); 322 writel(regval, ams->base + AMS_IER_0); 323 324 regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask)); 325 writel(regval, ams->base + AMS_IER_1); 326 327 regval = ams->intr_mask | ams->current_masked_alarm; 328 writel(regval, ams->base + AMS_IDR_0); 329 330 regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask); 331 writel(regval, ams->base + AMS_IDR_1); 332 } 333 334 static void ams_disable_all_alarms(struct ams *ams) 335 { 336 /* disable PS module alarm */ 337 if (ams->ps_base) { 338 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, 339 AMS_REGCFG1_ALARM_MASK); 340 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, 341 AMS_REGCFG3_ALARM_MASK); 342 } 343 344 /* disable PL module alarm */ 345 if (ams->pl_base) { 346 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, 347 AMS_REGCFG1_ALARM_MASK); 348 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, 349 AMS_REGCFG3_ALARM_MASK); 350 } 351 } 352 353 static void ams_update_ps_alarm(struct ams *ams, unsigned long alarm_mask) 354 { 355 u32 cfg; 356 u32 val; 357 358 val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, alarm_mask); 359 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val)); 360 361 val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, alarm_mask); 362 cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val)); 363 364 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg); 365 366 val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, alarm_mask); 367 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val)); 368 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg); 369 } 370 371 static void ams_update_pl_alarm(struct ams *ams, unsigned long alarm_mask) 372 { 373 unsigned long pl_alarm_mask; 374 u32 cfg; 375 u32 val; 376 377 pl_alarm_mask = FIELD_GET(AMS_PL_ALARM_MASK, alarm_mask); 378 379 val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, pl_alarm_mask); 380 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val)); 381 382 val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, pl_alarm_mask); 383 cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val)); 384 385 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg); 386 387 val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, pl_alarm_mask); 388 cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val)); 389 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg); 390 } 391 392 static void ams_update_alarm(struct ams *ams, unsigned long alarm_mask) 393 { 394 unsigned long flags; 395 396 if (ams->ps_base) 397 ams_update_ps_alarm(ams, alarm_mask); 398 399 if (ams->pl_base) 400 ams_update_pl_alarm(ams, alarm_mask); 401 402 spin_lock_irqsave(&ams->intr_lock, flags); 403 ams_update_intrmask(ams, AMS_ISR0_ALARM_MASK, ~alarm_mask); 404 spin_unlock_irqrestore(&ams->intr_lock, flags); 405 } 406 407 static void ams_enable_channel_sequence(struct iio_dev *indio_dev) 408 { 409 struct ams *ams = iio_priv(indio_dev); 410 unsigned long long scan_mask; 411 int i; 412 u32 regval; 413 414 /* 415 * Enable channel sequence. First 22 bits of scan_mask represent 416 * PS channels, and next remaining bits represent PL channels. 417 */ 418 419 /* Run calibration of PS & PL as part of the sequence */ 420 scan_mask = BIT(0) | BIT(AMS_PS_SEQ_MAX); 421 for (i = 0; i < indio_dev->num_channels; i++) { 422 const struct iio_chan_spec *chan = &indio_dev->channels[i]; 423 424 if (chan->scan_index < AMS_CTRL_SEQ_BASE) 425 scan_mask |= BIT_ULL(chan->scan_index); 426 } 427 428 if (ams->ps_base) { 429 /* put sysmon in a soft reset to change the sequence */ 430 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 431 AMS_CONF1_SEQ_DEFAULT); 432 433 /* configure basic channels */ 434 regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask); 435 writel(regval, ams->ps_base + AMS_REG_SEQ_CH0); 436 437 regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask); 438 writel(regval, ams->ps_base + AMS_REG_SEQ_CH2); 439 440 /* set continuous sequence mode */ 441 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 442 AMS_CONF1_SEQ_CONTINUOUS); 443 } 444 445 if (ams->pl_base) { 446 /* put sysmon in a soft reset to change the sequence */ 447 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 448 AMS_CONF1_SEQ_DEFAULT); 449 450 /* configure basic channels */ 451 scan_mask = FIELD_GET(AMS_PL_SEQ_MASK, scan_mask); 452 453 regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask); 454 writel(regval, ams->pl_base + AMS_REG_SEQ_CH0); 455 456 regval = FIELD_GET(AMS_REG_SEQ1_MASK, scan_mask); 457 writel(regval, ams->pl_base + AMS_REG_SEQ_CH1); 458 459 regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask); 460 writel(regval, ams->pl_base + AMS_REG_SEQ_CH2); 461 462 /* set continuous sequence mode */ 463 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 464 AMS_CONF1_SEQ_CONTINUOUS); 465 } 466 } 467 468 static int ams_init_device(struct ams *ams) 469 { 470 u32 expect = AMS_PS_CSTS_PS_READY; 471 u32 reg, value; 472 int ret; 473 474 /* reset AMS */ 475 if (ams->ps_base) { 476 writel(AMS_PS_RESET_VALUE, ams->ps_base + AMS_VP_VN); 477 478 ret = readl_poll_timeout(ams->base + AMS_PS_CSTS, reg, (reg & expect), 479 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US); 480 if (ret) 481 return ret; 482 483 /* put sysmon in a default state */ 484 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 485 AMS_CONF1_SEQ_DEFAULT); 486 } 487 488 if (ams->pl_base) { 489 value = readl(ams->base + AMS_PL_CSTS); 490 if (value == 0) 491 return 0; 492 493 writel(AMS_PL_RESET_VALUE, ams->pl_base + AMS_VP_VN); 494 495 /* put sysmon in a default state */ 496 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 497 AMS_CONF1_SEQ_DEFAULT); 498 } 499 500 ams_disable_all_alarms(ams); 501 502 /* Disable interrupt */ 503 ams_update_intrmask(ams, AMS_ALARM_MASK, AMS_ALARM_MASK); 504 505 /* Clear any pending interrupt */ 506 writel(AMS_ISR0_ALARM_MASK, ams->base + AMS_ISR_0); 507 writel(AMS_ISR1_ALARM_MASK, ams->base + AMS_ISR_1); 508 509 return 0; 510 } 511 512 static int ams_read_label(struct iio_dev *indio_dev, 513 struct iio_chan_spec const *chan, char *label) 514 { 515 return sysfs_emit(label, "%s\n", chan->datasheet_name); 516 } 517 518 static int ams_enable_single_channel(struct ams *ams, unsigned int offset) 519 { 520 u8 channel_num; 521 522 switch (offset) { 523 case AMS_VCC_PSPLL0: 524 channel_num = AMS_VCC_PSPLL0_CH; 525 break; 526 case AMS_VCC_PSPLL3: 527 channel_num = AMS_VCC_PSPLL3_CH; 528 break; 529 case AMS_VCCINT: 530 channel_num = AMS_VCCINT_CH; 531 break; 532 case AMS_VCCBRAM: 533 channel_num = AMS_VCCBRAM_CH; 534 break; 535 case AMS_VCCAUX: 536 channel_num = AMS_VCCAUX_CH; 537 break; 538 case AMS_PSDDRPLL: 539 channel_num = AMS_PSDDRPLL_CH; 540 break; 541 case AMS_PSINTFPDDR: 542 channel_num = AMS_PSINTFPDDR_CH; 543 break; 544 default: 545 return -EINVAL; 546 } 547 548 /* put sysmon in a soft reset to change the sequence */ 549 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 550 AMS_CONF1_SEQ_DEFAULT); 551 552 /* write the channel number */ 553 ams_ps_update_reg(ams, AMS_REG_CONFIG0, AMS_CONF0_CHANNEL_NUM_MASK, 554 channel_num); 555 556 /* set single channel, sequencer off mode */ 557 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, 558 AMS_CONF1_SEQ_SINGLE_CHANNEL); 559 560 return 0; 561 } 562 563 static int ams_read_vcc_reg(struct ams *ams, unsigned int offset, u32 *data) 564 { 565 u32 expect = AMS_ISR1_EOC_MASK; 566 u32 reg; 567 int ret; 568 569 ret = ams_enable_single_channel(ams, offset); 570 if (ret) 571 return ret; 572 573 /* clear end-of-conversion flag, wait for next conversion to complete */ 574 writel(expect, ams->base + AMS_ISR_1); 575 ret = readl_poll_timeout(ams->base + AMS_ISR_1, reg, (reg & expect), 576 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US); 577 if (ret) 578 return ret; 579 580 *data = readl(ams->base + offset); 581 582 return 0; 583 } 584 585 static int ams_get_ps_scale(int address) 586 { 587 int val; 588 589 switch (address) { 590 case AMS_SUPPLY1: 591 case AMS_SUPPLY2: 592 case AMS_SUPPLY3: 593 case AMS_SUPPLY4: 594 case AMS_SUPPLY9: 595 case AMS_SUPPLY10: 596 case AMS_VCCAMS: 597 val = AMS_SUPPLY_SCALE_3VOLT_mV; 598 break; 599 case AMS_SUPPLY5: 600 case AMS_SUPPLY6: 601 case AMS_SUPPLY7: 602 case AMS_SUPPLY8: 603 val = AMS_SUPPLY_SCALE_6VOLT_mV; 604 break; 605 default: 606 val = AMS_SUPPLY_SCALE_1VOLT_mV; 607 break; 608 } 609 610 return val; 611 } 612 613 static int ams_get_pl_scale(struct ams *ams, int address) 614 { 615 int val, regval; 616 617 switch (address) { 618 case AMS_SUPPLY1: 619 case AMS_SUPPLY2: 620 case AMS_SUPPLY3: 621 case AMS_SUPPLY4: 622 case AMS_SUPPLY5: 623 case AMS_SUPPLY6: 624 case AMS_VCCAMS: 625 case AMS_VREFP: 626 case AMS_VREFN: 627 val = AMS_SUPPLY_SCALE_3VOLT_mV; 628 break; 629 case AMS_SUPPLY7: 630 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 631 if (FIELD_GET(AMS_VUSER0_MASK, regval)) 632 val = AMS_SUPPLY_SCALE_6VOLT_mV; 633 else 634 val = AMS_SUPPLY_SCALE_3VOLT_mV; 635 break; 636 case AMS_SUPPLY8: 637 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 638 if (FIELD_GET(AMS_VUSER1_MASK, regval)) 639 val = AMS_SUPPLY_SCALE_6VOLT_mV; 640 else 641 val = AMS_SUPPLY_SCALE_3VOLT_mV; 642 break; 643 case AMS_SUPPLY9: 644 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 645 if (FIELD_GET(AMS_VUSER2_MASK, regval)) 646 val = AMS_SUPPLY_SCALE_6VOLT_mV; 647 else 648 val = AMS_SUPPLY_SCALE_3VOLT_mV; 649 break; 650 case AMS_SUPPLY10: 651 regval = readl(ams->pl_base + AMS_REG_CONFIG4); 652 if (FIELD_GET(AMS_VUSER3_MASK, regval)) 653 val = AMS_SUPPLY_SCALE_6VOLT_mV; 654 else 655 val = AMS_SUPPLY_SCALE_3VOLT_mV; 656 break; 657 case AMS_VP_VN: 658 case AMS_REG_VAUX(0) ... AMS_REG_VAUX(15): 659 val = AMS_SUPPLY_SCALE_1VOLT_mV; 660 break; 661 default: 662 val = AMS_SUPPLY_SCALE_1VOLT_mV; 663 break; 664 } 665 666 return val; 667 } 668 669 static int ams_get_ctrl_scale(int address) 670 { 671 int val; 672 673 switch (address) { 674 case AMS_VCC_PSPLL0: 675 case AMS_VCC_PSPLL3: 676 case AMS_VCCINT: 677 case AMS_VCCBRAM: 678 case AMS_VCCAUX: 679 case AMS_PSDDRPLL: 680 case AMS_PSINTFPDDR: 681 val = AMS_SUPPLY_SCALE_3VOLT_mV; 682 break; 683 default: 684 val = AMS_SUPPLY_SCALE_1VOLT_mV; 685 break; 686 } 687 688 return val; 689 } 690 691 static int ams_read_raw(struct iio_dev *indio_dev, 692 struct iio_chan_spec const *chan, 693 int *val, int *val2, long mask) 694 { 695 struct ams *ams = iio_priv(indio_dev); 696 int ret; 697 698 switch (mask) { 699 case IIO_CHAN_INFO_RAW: 700 mutex_lock(&ams->lock); 701 if (chan->scan_index >= AMS_CTRL_SEQ_BASE) { 702 ret = ams_read_vcc_reg(ams, chan->address, val); 703 if (ret) 704 goto unlock_mutex; 705 ams_enable_channel_sequence(indio_dev); 706 } else if (chan->scan_index >= AMS_PS_SEQ_MAX) 707 *val = readl(ams->pl_base + chan->address); 708 else 709 *val = readl(ams->ps_base + chan->address); 710 711 ret = IIO_VAL_INT; 712 unlock_mutex: 713 mutex_unlock(&ams->lock); 714 return ret; 715 case IIO_CHAN_INFO_SCALE: 716 switch (chan->type) { 717 case IIO_VOLTAGE: 718 if (chan->scan_index < AMS_PS_SEQ_MAX) 719 *val = ams_get_ps_scale(chan->address); 720 else if (chan->scan_index >= AMS_PS_SEQ_MAX && 721 chan->scan_index < AMS_CTRL_SEQ_BASE) 722 *val = ams_get_pl_scale(ams, chan->address); 723 else 724 *val = ams_get_ctrl_scale(chan->address); 725 726 *val2 = AMS_SUPPLY_SCALE_DIV_BIT; 727 return IIO_VAL_FRACTIONAL_LOG2; 728 case IIO_TEMP: 729 *val = AMS_TEMP_SCALE; 730 *val2 = AMS_TEMP_SCALE_DIV_BIT; 731 return IIO_VAL_FRACTIONAL_LOG2; 732 default: 733 return -EINVAL; 734 } 735 case IIO_CHAN_INFO_OFFSET: 736 /* Only the temperature channel has an offset */ 737 *val = AMS_TEMP_OFFSET; 738 return IIO_VAL_INT; 739 default: 740 return -EINVAL; 741 } 742 } 743 744 static int ams_get_alarm_offset(int scan_index, enum iio_event_direction dir) 745 { 746 int offset; 747 748 if (scan_index >= AMS_PS_SEQ_MAX) 749 scan_index -= AMS_PS_SEQ_MAX; 750 751 if (dir == IIO_EV_DIR_FALLING) { 752 if (scan_index < AMS_SEQ_SUPPLY7) 753 offset = AMS_ALARM_THRESHOLD_OFF_10; 754 else 755 offset = AMS_ALARM_THRESHOLD_OFF_20; 756 } else { 757 offset = 0; 758 } 759 760 switch (scan_index) { 761 case AMS_SEQ_TEMP: 762 return AMS_ALARM_TEMP + offset; 763 case AMS_SEQ_SUPPLY1: 764 return AMS_ALARM_SUPPLY1 + offset; 765 case AMS_SEQ_SUPPLY2: 766 return AMS_ALARM_SUPPLY2 + offset; 767 case AMS_SEQ_SUPPLY3: 768 return AMS_ALARM_SUPPLY3 + offset; 769 case AMS_SEQ_SUPPLY4: 770 return AMS_ALARM_SUPPLY4 + offset; 771 case AMS_SEQ_SUPPLY5: 772 return AMS_ALARM_SUPPLY5 + offset; 773 case AMS_SEQ_SUPPLY6: 774 return AMS_ALARM_SUPPLY6 + offset; 775 case AMS_SEQ_SUPPLY7: 776 return AMS_ALARM_SUPPLY7 + offset; 777 case AMS_SEQ_SUPPLY8: 778 return AMS_ALARM_SUPPLY8 + offset; 779 case AMS_SEQ_SUPPLY9: 780 return AMS_ALARM_SUPPLY9 + offset; 781 case AMS_SEQ_SUPPLY10: 782 return AMS_ALARM_SUPPLY10 + offset; 783 case AMS_SEQ_VCCAMS: 784 return AMS_ALARM_VCCAMS + offset; 785 case AMS_SEQ_TEMP_REMOTE: 786 return AMS_ALARM_TEMP_REMOTE + offset; 787 default: 788 return 0; 789 } 790 } 791 792 static const struct iio_chan_spec *ams_event_to_channel(struct iio_dev *dev, 793 u32 event) 794 { 795 int scan_index = 0, i; 796 797 if (event >= AMS_PL_ALARM_START) { 798 event -= AMS_PL_ALARM_START; 799 scan_index = AMS_PS_SEQ_MAX; 800 } 801 802 switch (event) { 803 case AMS_ALARM_BIT_TEMP: 804 scan_index += AMS_SEQ_TEMP; 805 break; 806 case AMS_ALARM_BIT_SUPPLY1: 807 scan_index += AMS_SEQ_SUPPLY1; 808 break; 809 case AMS_ALARM_BIT_SUPPLY2: 810 scan_index += AMS_SEQ_SUPPLY2; 811 break; 812 case AMS_ALARM_BIT_SUPPLY3: 813 scan_index += AMS_SEQ_SUPPLY3; 814 break; 815 case AMS_ALARM_BIT_SUPPLY4: 816 scan_index += AMS_SEQ_SUPPLY4; 817 break; 818 case AMS_ALARM_BIT_SUPPLY5: 819 scan_index += AMS_SEQ_SUPPLY5; 820 break; 821 case AMS_ALARM_BIT_SUPPLY6: 822 scan_index += AMS_SEQ_SUPPLY6; 823 break; 824 case AMS_ALARM_BIT_SUPPLY7: 825 scan_index += AMS_SEQ_SUPPLY7; 826 break; 827 case AMS_ALARM_BIT_SUPPLY8: 828 scan_index += AMS_SEQ_SUPPLY8; 829 break; 830 case AMS_ALARM_BIT_SUPPLY9: 831 scan_index += AMS_SEQ_SUPPLY9; 832 break; 833 case AMS_ALARM_BIT_SUPPLY10: 834 scan_index += AMS_SEQ_SUPPLY10; 835 break; 836 case AMS_ALARM_BIT_VCCAMS: 837 scan_index += AMS_SEQ_VCCAMS; 838 break; 839 case AMS_ALARM_BIT_TEMP_REMOTE: 840 scan_index += AMS_SEQ_TEMP_REMOTE; 841 break; 842 default: 843 break; 844 } 845 846 for (i = 0; i < dev->num_channels; i++) 847 if (dev->channels[i].scan_index == scan_index) 848 break; 849 850 return &dev->channels[i]; 851 } 852 853 static int ams_get_alarm_mask(int scan_index) 854 { 855 int bit = 0; 856 857 if (scan_index >= AMS_PS_SEQ_MAX) { 858 bit = AMS_PL_ALARM_START; 859 scan_index -= AMS_PS_SEQ_MAX; 860 } 861 862 switch (scan_index) { 863 case AMS_SEQ_TEMP: 864 return BIT(AMS_ALARM_BIT_TEMP + bit); 865 case AMS_SEQ_SUPPLY1: 866 return BIT(AMS_ALARM_BIT_SUPPLY1 + bit); 867 case AMS_SEQ_SUPPLY2: 868 return BIT(AMS_ALARM_BIT_SUPPLY2 + bit); 869 case AMS_SEQ_SUPPLY3: 870 return BIT(AMS_ALARM_BIT_SUPPLY3 + bit); 871 case AMS_SEQ_SUPPLY4: 872 return BIT(AMS_ALARM_BIT_SUPPLY4 + bit); 873 case AMS_SEQ_SUPPLY5: 874 return BIT(AMS_ALARM_BIT_SUPPLY5 + bit); 875 case AMS_SEQ_SUPPLY6: 876 return BIT(AMS_ALARM_BIT_SUPPLY6 + bit); 877 case AMS_SEQ_SUPPLY7: 878 return BIT(AMS_ALARM_BIT_SUPPLY7 + bit); 879 case AMS_SEQ_SUPPLY8: 880 return BIT(AMS_ALARM_BIT_SUPPLY8 + bit); 881 case AMS_SEQ_SUPPLY9: 882 return BIT(AMS_ALARM_BIT_SUPPLY9 + bit); 883 case AMS_SEQ_SUPPLY10: 884 return BIT(AMS_ALARM_BIT_SUPPLY10 + bit); 885 case AMS_SEQ_VCCAMS: 886 return BIT(AMS_ALARM_BIT_VCCAMS + bit); 887 case AMS_SEQ_TEMP_REMOTE: 888 return BIT(AMS_ALARM_BIT_TEMP_REMOTE + bit); 889 default: 890 return 0; 891 } 892 } 893 894 static int ams_read_event_config(struct iio_dev *indio_dev, 895 const struct iio_chan_spec *chan, 896 enum iio_event_type type, 897 enum iio_event_direction dir) 898 { 899 struct ams *ams = iio_priv(indio_dev); 900 901 return !!(ams->alarm_mask & ams_get_alarm_mask(chan->scan_index)); 902 } 903 904 static int ams_write_event_config(struct iio_dev *indio_dev, 905 const struct iio_chan_spec *chan, 906 enum iio_event_type type, 907 enum iio_event_direction dir, 908 int state) 909 { 910 struct ams *ams = iio_priv(indio_dev); 911 unsigned int alarm; 912 913 alarm = ams_get_alarm_mask(chan->scan_index); 914 915 mutex_lock(&ams->lock); 916 917 if (state) 918 ams->alarm_mask |= alarm; 919 else 920 ams->alarm_mask &= ~alarm; 921 922 ams_update_alarm(ams, ams->alarm_mask); 923 924 mutex_unlock(&ams->lock); 925 926 return 0; 927 } 928 929 static int ams_read_event_value(struct iio_dev *indio_dev, 930 const struct iio_chan_spec *chan, 931 enum iio_event_type type, 932 enum iio_event_direction dir, 933 enum iio_event_info info, int *val, int *val2) 934 { 935 struct ams *ams = iio_priv(indio_dev); 936 unsigned int offset = ams_get_alarm_offset(chan->scan_index, dir); 937 938 mutex_lock(&ams->lock); 939 940 if (chan->scan_index >= AMS_PS_SEQ_MAX) 941 *val = readl(ams->pl_base + offset); 942 else 943 *val = readl(ams->ps_base + offset); 944 945 mutex_unlock(&ams->lock); 946 947 return IIO_VAL_INT; 948 } 949 950 static int ams_write_event_value(struct iio_dev *indio_dev, 951 const struct iio_chan_spec *chan, 952 enum iio_event_type type, 953 enum iio_event_direction dir, 954 enum iio_event_info info, int val, int val2) 955 { 956 struct ams *ams = iio_priv(indio_dev); 957 unsigned int offset; 958 959 mutex_lock(&ams->lock); 960 961 /* Set temperature channel threshold to direct threshold */ 962 if (chan->type == IIO_TEMP) { 963 offset = ams_get_alarm_offset(chan->scan_index, IIO_EV_DIR_FALLING); 964 965 if (chan->scan_index >= AMS_PS_SEQ_MAX) 966 ams_pl_update_reg(ams, offset, 967 AMS_ALARM_THR_DIRECT_MASK, 968 AMS_ALARM_THR_DIRECT_MASK); 969 else 970 ams_ps_update_reg(ams, offset, 971 AMS_ALARM_THR_DIRECT_MASK, 972 AMS_ALARM_THR_DIRECT_MASK); 973 } 974 975 offset = ams_get_alarm_offset(chan->scan_index, dir); 976 if (chan->scan_index >= AMS_PS_SEQ_MAX) 977 writel(val, ams->pl_base + offset); 978 else 979 writel(val, ams->ps_base + offset); 980 981 mutex_unlock(&ams->lock); 982 983 return 0; 984 } 985 986 static void ams_handle_event(struct iio_dev *indio_dev, u32 event) 987 { 988 const struct iio_chan_spec *chan; 989 990 chan = ams_event_to_channel(indio_dev, event); 991 992 if (chan->type == IIO_TEMP) { 993 /* 994 * The temperature channel only supports over-temperature 995 * events. 996 */ 997 iio_push_event(indio_dev, 998 IIO_UNMOD_EVENT_CODE(chan->type, chan->channel, 999 IIO_EV_TYPE_THRESH, 1000 IIO_EV_DIR_RISING), 1001 iio_get_time_ns(indio_dev)); 1002 } else { 1003 /* 1004 * For other channels we don't know whether it is a upper or 1005 * lower threshold event. Userspace will have to check the 1006 * channel value if it wants to know. 1007 */ 1008 iio_push_event(indio_dev, 1009 IIO_UNMOD_EVENT_CODE(chan->type, chan->channel, 1010 IIO_EV_TYPE_THRESH, 1011 IIO_EV_DIR_EITHER), 1012 iio_get_time_ns(indio_dev)); 1013 } 1014 } 1015 1016 static void ams_handle_events(struct iio_dev *indio_dev, unsigned long events) 1017 { 1018 unsigned int bit; 1019 1020 for_each_set_bit(bit, &events, AMS_NO_OF_ALARMS) 1021 ams_handle_event(indio_dev, bit); 1022 } 1023 1024 /** 1025 * ams_unmask_worker - ams alarm interrupt unmask worker 1026 * @work: work to be done 1027 * 1028 * The ZynqMP threshold interrupts are level sensitive. Since we can't make the 1029 * threshold condition go way from within the interrupt handler, this means as 1030 * soon as a threshold condition is present we would enter the interrupt handler 1031 * again and again. To work around this we mask all active threshold interrupts 1032 * in the interrupt handler and start a timer. In this timer we poll the 1033 * interrupt status and only if the interrupt is inactive we unmask it again. 1034 */ 1035 static void ams_unmask_worker(struct work_struct *work) 1036 { 1037 struct ams *ams = container_of(work, struct ams, ams_unmask_work.work); 1038 unsigned int status, unmask; 1039 1040 spin_lock_irq(&ams->intr_lock); 1041 1042 status = readl(ams->base + AMS_ISR_0); 1043 1044 /* Clear those bits which are not active anymore */ 1045 unmask = (ams->current_masked_alarm ^ status) & ams->current_masked_alarm; 1046 1047 /* Clear status of disabled alarm */ 1048 unmask |= ams->intr_mask; 1049 1050 ams->current_masked_alarm &= status; 1051 1052 /* Also clear those which are masked out anyway */ 1053 ams->current_masked_alarm &= ~ams->intr_mask; 1054 1055 /* Clear the interrupts before we unmask them */ 1056 writel(unmask, ams->base + AMS_ISR_0); 1057 1058 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK); 1059 1060 spin_unlock_irq(&ams->intr_lock); 1061 1062 /* If still pending some alarm re-trigger the timer */ 1063 if (ams->current_masked_alarm) 1064 schedule_delayed_work(&ams->ams_unmask_work, 1065 msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS)); 1066 } 1067 1068 static irqreturn_t ams_irq(int irq, void *data) 1069 { 1070 struct iio_dev *indio_dev = data; 1071 struct ams *ams = iio_priv(indio_dev); 1072 u32 isr0; 1073 1074 spin_lock(&ams->intr_lock); 1075 1076 isr0 = readl(ams->base + AMS_ISR_0); 1077 1078 /* Only process alarms that are not masked */ 1079 isr0 &= ~((ams->intr_mask & AMS_ISR0_ALARM_MASK) | ams->current_masked_alarm); 1080 if (!isr0) { 1081 spin_unlock(&ams->intr_lock); 1082 return IRQ_NONE; 1083 } 1084 1085 /* Clear interrupt */ 1086 writel(isr0, ams->base + AMS_ISR_0); 1087 1088 /* Mask the alarm interrupts until cleared */ 1089 ams->current_masked_alarm |= isr0; 1090 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK); 1091 1092 ams_handle_events(indio_dev, isr0); 1093 1094 schedule_delayed_work(&ams->ams_unmask_work, 1095 msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS)); 1096 1097 spin_unlock(&ams->intr_lock); 1098 1099 return IRQ_HANDLED; 1100 } 1101 1102 static const struct iio_event_spec ams_temp_events[] = { 1103 { 1104 .type = IIO_EV_TYPE_THRESH, 1105 .dir = IIO_EV_DIR_RISING, 1106 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE), 1107 }, 1108 }; 1109 1110 static const struct iio_event_spec ams_voltage_events[] = { 1111 { 1112 .type = IIO_EV_TYPE_THRESH, 1113 .dir = IIO_EV_DIR_RISING, 1114 .mask_separate = BIT(IIO_EV_INFO_VALUE), 1115 }, 1116 { 1117 .type = IIO_EV_TYPE_THRESH, 1118 .dir = IIO_EV_DIR_FALLING, 1119 .mask_separate = BIT(IIO_EV_INFO_VALUE), 1120 }, 1121 { 1122 .type = IIO_EV_TYPE_THRESH, 1123 .dir = IIO_EV_DIR_EITHER, 1124 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1125 }, 1126 }; 1127 1128 static const struct iio_chan_spec ams_ps_channels[] = { 1129 AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP, "Temp_LPD"), 1130 AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP_REMOTE, AMS_TEMP_REMOTE, "Temp_FPD"), 1131 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1, "VCC_PSINTLP"), 1132 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2, "VCC_PSINTFP"), 1133 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3, "VCC_PSAUX"), 1134 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4, "VCC_PSDDR"), 1135 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5, "VCC_PSIO3"), 1136 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6, "VCC_PSIO0"), 1137 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7, "VCC_PSIO1"), 1138 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8, "VCC_PSIO2"), 1139 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9, "PS_MGTRAVCC"), 1140 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10, "PS_MGTRAVTT"), 1141 AMS_PS_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS, "VCC_PSADC"), 1142 }; 1143 1144 static const struct iio_chan_spec ams_pl_channels[] = { 1145 AMS_PL_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP, "Temp_PL"), 1146 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1, true, "VCCINT"), 1147 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2, true, "VCCAUX"), 1148 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFP, AMS_VREFP, false, "VREFP"), 1149 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFN, AMS_VREFN, false, "VREFN"), 1150 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3, true, "VCCBRAM"), 1151 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4, true, "VCC_PSINTLP"), 1152 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5, true, "VCC_PSINTFP"), 1153 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6, true, "VCC_PSAUX"), 1154 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS, true, "VCCAMS"), 1155 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VP_VN, AMS_VP_VN, false, "VP_VN"), 1156 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7, true, "VUser0"), 1157 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8, true, "VUser1"), 1158 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9, true, "VUser2"), 1159 AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10, true, "VUser3"), 1160 AMS_PL_AUX_CHAN_VOLTAGE(0), 1161 AMS_PL_AUX_CHAN_VOLTAGE(1), 1162 AMS_PL_AUX_CHAN_VOLTAGE(2), 1163 AMS_PL_AUX_CHAN_VOLTAGE(3), 1164 AMS_PL_AUX_CHAN_VOLTAGE(4), 1165 AMS_PL_AUX_CHAN_VOLTAGE(5), 1166 AMS_PL_AUX_CHAN_VOLTAGE(6), 1167 AMS_PL_AUX_CHAN_VOLTAGE(7), 1168 AMS_PL_AUX_CHAN_VOLTAGE(8), 1169 AMS_PL_AUX_CHAN_VOLTAGE(9), 1170 AMS_PL_AUX_CHAN_VOLTAGE(10), 1171 AMS_PL_AUX_CHAN_VOLTAGE(11), 1172 AMS_PL_AUX_CHAN_VOLTAGE(12), 1173 AMS_PL_AUX_CHAN_VOLTAGE(13), 1174 AMS_PL_AUX_CHAN_VOLTAGE(14), 1175 AMS_PL_AUX_CHAN_VOLTAGE(15), 1176 }; 1177 1178 static const struct iio_chan_spec ams_ctrl_channels[] = { 1179 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSPLL, AMS_VCC_PSPLL0, "VCC_PSPLL"), 1180 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSBATT, AMS_VCC_PSPLL3, "VCC_PSBATT"), 1181 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCINT, AMS_VCCINT, "VCCINT"), 1182 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCBRAM, AMS_VCCBRAM, "VCCBRAM"), 1183 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCAUX, AMS_VCCAUX, "VCCAUX"), 1184 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_PSDDRPLL, AMS_PSDDRPLL, "VCC_PSDDR_PLL"), 1185 AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_INTDDR, AMS_PSINTFPDDR, "VCC_PSINTFP_DDR"), 1186 }; 1187 1188 static int ams_get_ext_chan(struct fwnode_handle *chan_node, 1189 struct iio_chan_spec *channels, int num_channels) 1190 { 1191 struct iio_chan_spec *chan; 1192 struct fwnode_handle *child; 1193 unsigned int reg, ext_chan; 1194 int ret; 1195 1196 fwnode_for_each_child_node(chan_node, child) { 1197 ret = fwnode_property_read_u32(child, "reg", ®); 1198 if (ret || reg > AMS_PL_MAX_EXT_CHANNEL + 30) 1199 continue; 1200 1201 chan = &channels[num_channels]; 1202 ext_chan = reg + AMS_PL_MAX_FIXED_CHANNEL - 30; 1203 memcpy(chan, &ams_pl_channels[ext_chan], sizeof(*channels)); 1204 1205 if (fwnode_property_read_bool(child, "xlnx,bipolar")) 1206 chan->scan_type.sign = 's'; 1207 1208 num_channels++; 1209 } 1210 1211 return num_channels; 1212 } 1213 1214 static void ams_iounmap_ps(void *data) 1215 { 1216 struct ams *ams = data; 1217 1218 iounmap(ams->ps_base); 1219 } 1220 1221 static void ams_iounmap_pl(void *data) 1222 { 1223 struct ams *ams = data; 1224 1225 iounmap(ams->pl_base); 1226 } 1227 1228 static int ams_init_module(struct iio_dev *indio_dev, 1229 struct fwnode_handle *fwnode, 1230 struct iio_chan_spec *channels) 1231 { 1232 struct device *dev = indio_dev->dev.parent; 1233 struct ams *ams = iio_priv(indio_dev); 1234 int num_channels = 0; 1235 int ret; 1236 1237 if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-ps")) { 1238 ams->ps_base = fwnode_iomap(fwnode, 0); 1239 if (!ams->ps_base) 1240 return -ENXIO; 1241 ret = devm_add_action_or_reset(dev, ams_iounmap_ps, ams); 1242 if (ret < 0) 1243 return ret; 1244 1245 /* add PS channels to iio device channels */ 1246 memcpy(channels, ams_ps_channels, sizeof(ams_ps_channels)); 1247 num_channels = ARRAY_SIZE(ams_ps_channels); 1248 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-pl")) { 1249 ams->pl_base = fwnode_iomap(fwnode, 0); 1250 if (!ams->pl_base) 1251 return -ENXIO; 1252 1253 ret = devm_add_action_or_reset(dev, ams_iounmap_pl, ams); 1254 if (ret < 0) 1255 return ret; 1256 1257 /* Copy only first 10 fix channels */ 1258 memcpy(channels, ams_pl_channels, AMS_PL_MAX_FIXED_CHANNEL * sizeof(*channels)); 1259 num_channels += AMS_PL_MAX_FIXED_CHANNEL; 1260 num_channels = ams_get_ext_chan(fwnode, channels, 1261 num_channels); 1262 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams")) { 1263 /* add AMS channels to iio device channels */ 1264 memcpy(channels, ams_ctrl_channels, sizeof(ams_ctrl_channels)); 1265 num_channels += ARRAY_SIZE(ams_ctrl_channels); 1266 } else { 1267 return -EINVAL; 1268 } 1269 1270 return num_channels; 1271 } 1272 1273 static int ams_parse_firmware(struct iio_dev *indio_dev) 1274 { 1275 struct ams *ams = iio_priv(indio_dev); 1276 struct iio_chan_spec *ams_channels, *dev_channels; 1277 struct device *dev = indio_dev->dev.parent; 1278 struct fwnode_handle *child = NULL; 1279 struct fwnode_handle *fwnode = dev_fwnode(dev); 1280 size_t ams_size; 1281 int ret, ch_cnt = 0, i, rising_off, falling_off; 1282 unsigned int num_channels = 0; 1283 1284 ams_size = ARRAY_SIZE(ams_ps_channels) + ARRAY_SIZE(ams_pl_channels) + 1285 ARRAY_SIZE(ams_ctrl_channels); 1286 1287 /* Initialize buffer for channel specification */ 1288 ams_channels = devm_kcalloc(dev, ams_size, sizeof(*ams_channels), GFP_KERNEL); 1289 if (!ams_channels) 1290 return -ENOMEM; 1291 1292 if (fwnode_device_is_available(fwnode)) { 1293 ret = ams_init_module(indio_dev, fwnode, ams_channels); 1294 if (ret < 0) 1295 return ret; 1296 1297 num_channels += ret; 1298 } 1299 1300 fwnode_for_each_child_node(fwnode, child) { 1301 if (fwnode_device_is_available(child)) { 1302 ret = ams_init_module(indio_dev, child, ams_channels + num_channels); 1303 if (ret < 0) { 1304 fwnode_handle_put(child); 1305 return ret; 1306 } 1307 1308 num_channels += ret; 1309 } 1310 } 1311 1312 for (i = 0; i < num_channels; i++) { 1313 ams_channels[i].channel = ch_cnt++; 1314 1315 if (ams_channels[i].scan_index < AMS_CTRL_SEQ_BASE) { 1316 /* set threshold to max and min for each channel */ 1317 falling_off = 1318 ams_get_alarm_offset(ams_channels[i].scan_index, 1319 IIO_EV_DIR_FALLING); 1320 rising_off = 1321 ams_get_alarm_offset(ams_channels[i].scan_index, 1322 IIO_EV_DIR_RISING); 1323 if (ams_channels[i].scan_index >= AMS_PS_SEQ_MAX) { 1324 writel(AMS_ALARM_THR_MIN, 1325 ams->pl_base + falling_off); 1326 writel(AMS_ALARM_THR_MAX, 1327 ams->pl_base + rising_off); 1328 } else { 1329 writel(AMS_ALARM_THR_MIN, 1330 ams->ps_base + falling_off); 1331 writel(AMS_ALARM_THR_MAX, 1332 ams->ps_base + rising_off); 1333 } 1334 } 1335 } 1336 1337 dev_channels = devm_krealloc_array(dev, ams_channels, num_channels, 1338 sizeof(*dev_channels), GFP_KERNEL); 1339 if (!dev_channels) 1340 return -ENOMEM; 1341 1342 indio_dev->channels = dev_channels; 1343 indio_dev->num_channels = num_channels; 1344 1345 return 0; 1346 } 1347 1348 static const struct iio_info iio_ams_info = { 1349 .read_label = ams_read_label, 1350 .read_raw = &ams_read_raw, 1351 .read_event_config = &ams_read_event_config, 1352 .write_event_config = &ams_write_event_config, 1353 .read_event_value = &ams_read_event_value, 1354 .write_event_value = &ams_write_event_value, 1355 }; 1356 1357 static const struct of_device_id ams_of_match_table[] = { 1358 { .compatible = "xlnx,zynqmp-ams" }, 1359 { } 1360 }; 1361 MODULE_DEVICE_TABLE(of, ams_of_match_table); 1362 1363 static int ams_probe(struct platform_device *pdev) 1364 { 1365 struct iio_dev *indio_dev; 1366 struct ams *ams; 1367 int ret; 1368 int irq; 1369 1370 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ams)); 1371 if (!indio_dev) 1372 return -ENOMEM; 1373 1374 ams = iio_priv(indio_dev); 1375 mutex_init(&ams->lock); 1376 spin_lock_init(&ams->intr_lock); 1377 1378 indio_dev->name = "xilinx-ams"; 1379 1380 indio_dev->info = &iio_ams_info; 1381 indio_dev->modes = INDIO_DIRECT_MODE; 1382 1383 ams->base = devm_platform_ioremap_resource(pdev, 0); 1384 if (IS_ERR(ams->base)) 1385 return PTR_ERR(ams->base); 1386 1387 ams->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1388 if (IS_ERR(ams->clk)) 1389 return PTR_ERR(ams->clk); 1390 1391 ret = devm_delayed_work_autocancel(&pdev->dev, &ams->ams_unmask_work, 1392 ams_unmask_worker); 1393 if (ret < 0) 1394 return ret; 1395 1396 ret = ams_parse_firmware(indio_dev); 1397 if (ret) 1398 return dev_err_probe(&pdev->dev, ret, "failure in parsing DT\n"); 1399 1400 ret = ams_init_device(ams); 1401 if (ret) 1402 return dev_err_probe(&pdev->dev, ret, "failed to initialize AMS\n"); 1403 1404 ams_enable_channel_sequence(indio_dev); 1405 1406 irq = platform_get_irq(pdev, 0); 1407 if (irq < 0) 1408 return irq; 1409 1410 ret = devm_request_irq(&pdev->dev, irq, &ams_irq, 0, "ams-irq", 1411 indio_dev); 1412 if (ret < 0) 1413 return dev_err_probe(&pdev->dev, ret, "failed to register interrupt\n"); 1414 1415 platform_set_drvdata(pdev, indio_dev); 1416 1417 return devm_iio_device_register(&pdev->dev, indio_dev); 1418 } 1419 1420 static int ams_suspend(struct device *dev) 1421 { 1422 struct ams *ams = iio_priv(dev_get_drvdata(dev)); 1423 1424 clk_disable_unprepare(ams->clk); 1425 1426 return 0; 1427 } 1428 1429 static int ams_resume(struct device *dev) 1430 { 1431 struct ams *ams = iio_priv(dev_get_drvdata(dev)); 1432 1433 return clk_prepare_enable(ams->clk); 1434 } 1435 1436 static DEFINE_SIMPLE_DEV_PM_OPS(ams_pm_ops, ams_suspend, ams_resume); 1437 1438 static struct platform_driver ams_driver = { 1439 .probe = ams_probe, 1440 .driver = { 1441 .name = "xilinx-ams", 1442 .pm = pm_sleep_ptr(&ams_pm_ops), 1443 .of_match_table = ams_of_match_table, 1444 }, 1445 }; 1446 module_platform_driver(ams_driver); 1447 1448 MODULE_DESCRIPTION("Xilinx AMS driver"); 1449 MODULE_LICENSE("GPL v2"); 1450 MODULE_AUTHOR("Xilinx, Inc."); 1451