1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale Vybrid vf610 ADC driver 4 * 5 * Copyright 2013 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/mutex.h> 11 #include <linux/property.h> 12 #include <linux/platform_device.h> 13 #include <linux/interrupt.h> 14 #include <linux/cleanup.h> 15 #include <linux/delay.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/io.h> 19 #include <linux/clk.h> 20 #include <linux/completion.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/err.h> 23 24 #include <linux/iio/iio.h> 25 #include <linux/iio/buffer.h> 26 #include <linux/iio/sysfs.h> 27 #include <linux/iio/trigger.h> 28 #include <linux/iio/trigger_consumer.h> 29 #include <linux/iio/triggered_buffer.h> 30 31 /* This will be the driver name the kernel reports */ 32 #define DRIVER_NAME "vf610-adc" 33 34 /* Vybrid/IMX ADC registers */ 35 #define VF610_REG_ADC_HC0 0x00 36 #define VF610_REG_ADC_HC1 0x04 37 #define VF610_REG_ADC_HS 0x08 38 #define VF610_REG_ADC_R0 0x0c 39 #define VF610_REG_ADC_R1 0x10 40 #define VF610_REG_ADC_CFG 0x14 41 #define VF610_REG_ADC_GC 0x18 42 #define VF610_REG_ADC_GS 0x1c 43 #define VF610_REG_ADC_CV 0x20 44 #define VF610_REG_ADC_OFS 0x24 45 #define VF610_REG_ADC_CAL 0x28 46 #define VF610_REG_ADC_PCTL 0x30 47 48 /* Configuration register field define */ 49 #define VF610_ADC_MODE_BIT8 0x00 50 #define VF610_ADC_MODE_BIT10 0x04 51 #define VF610_ADC_MODE_BIT12 0x08 52 #define VF610_ADC_MODE_MASK 0x0c 53 #define VF610_ADC_BUSCLK2_SEL 0x01 54 #define VF610_ADC_ALTCLK_SEL 0x02 55 #define VF610_ADC_ADACK_SEL 0x03 56 #define VF610_ADC_ADCCLK_MASK 0x03 57 #define VF610_ADC_CLK_DIV2 0x20 58 #define VF610_ADC_CLK_DIV4 0x40 59 #define VF610_ADC_CLK_DIV8 0x60 60 #define VF610_ADC_CLK_MASK 0x60 61 #define VF610_ADC_ADLSMP_LONG 0x10 62 #define VF610_ADC_ADSTS_SHORT 0x100 63 #define VF610_ADC_ADSTS_NORMAL 0x200 64 #define VF610_ADC_ADSTS_LONG 0x300 65 #define VF610_ADC_ADSTS_MASK 0x300 66 #define VF610_ADC_ADLPC_EN 0x80 67 #define VF610_ADC_ADHSC_EN 0x400 68 #define VF610_ADC_REFSEL_VALT 0x800 69 #define VF610_ADC_REFSEL_VBG 0x1000 70 #define VF610_ADC_ADTRG_HARD 0x2000 71 #define VF610_ADC_AVGS_8 0x4000 72 #define VF610_ADC_AVGS_16 0x8000 73 #define VF610_ADC_AVGS_32 0xC000 74 #define VF610_ADC_AVGS_MASK 0xC000 75 #define VF610_ADC_OVWREN 0x10000 76 77 /* General control register field define */ 78 #define VF610_ADC_ADACKEN 0x1 79 #define VF610_ADC_DMAEN 0x2 80 #define VF610_ADC_ACREN 0x4 81 #define VF610_ADC_ACFGT 0x8 82 #define VF610_ADC_ACFE 0x10 83 #define VF610_ADC_AVGEN 0x20 84 #define VF610_ADC_ADCON 0x40 85 #define VF610_ADC_CAL 0x80 86 87 /* Other field define */ 88 #define VF610_ADC_ADCHC(x) ((x) & 0x1F) 89 #define VF610_ADC_AIEN (0x1 << 7) 90 #define VF610_ADC_CONV_DISABLE 0x1F 91 #define VF610_ADC_HS_COCO0 0x1 92 #define VF610_ADC_CALF 0x2 93 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100) 94 95 #define DEFAULT_SAMPLE_TIME 1000 96 97 /* V at 25°C of 696 mV */ 98 #define VF610_VTEMP25_3V0 950 99 /* V at 25°C of 699 mV */ 100 #define VF610_VTEMP25_3V3 867 101 /* Typical sensor slope coefficient at all temperatures */ 102 #define VF610_TEMP_SLOPE_COEFF 1840 103 104 enum clk_sel { 105 VF610_ADCIOC_BUSCLK_SET, 106 VF610_ADCIOC_ALTCLK_SET, 107 VF610_ADCIOC_ADACK_SET, 108 }; 109 110 enum vol_ref { 111 VF610_ADCIOC_VR_VREF_SET, 112 VF610_ADCIOC_VR_VALT_SET, 113 VF610_ADCIOC_VR_VBG_SET, 114 }; 115 116 enum average_sel { 117 VF610_ADC_SAMPLE_1, 118 VF610_ADC_SAMPLE_4, 119 VF610_ADC_SAMPLE_8, 120 VF610_ADC_SAMPLE_16, 121 VF610_ADC_SAMPLE_32, 122 }; 123 124 enum conversion_mode_sel { 125 VF610_ADC_CONV_NORMAL, 126 VF610_ADC_CONV_HIGH_SPEED, 127 VF610_ADC_CONV_LOW_POWER, 128 }; 129 130 enum lst_adder_sel { 131 VF610_ADCK_CYCLES_3, 132 VF610_ADCK_CYCLES_5, 133 VF610_ADCK_CYCLES_7, 134 VF610_ADCK_CYCLES_9, 135 VF610_ADCK_CYCLES_13, 136 VF610_ADCK_CYCLES_17, 137 VF610_ADCK_CYCLES_21, 138 VF610_ADCK_CYCLES_25, 139 }; 140 141 struct vf610_adc_feature { 142 enum clk_sel clk_sel; 143 enum vol_ref vol_ref; 144 enum conversion_mode_sel conv_mode; 145 146 int clk_div; 147 int sample_rate; 148 int res_mode; 149 u32 lst_adder_index; 150 u32 default_sample_time; 151 152 bool calibration; 153 bool ovwren; 154 }; 155 156 struct vf610_adc { 157 struct device *dev; 158 void __iomem *regs; 159 struct clk *clk; 160 161 /* lock to protect against multiple access to the device */ 162 struct mutex lock; 163 164 u32 vref_uv; 165 u32 value; 166 struct regulator *vref; 167 168 u32 max_adck_rate[3]; 169 struct vf610_adc_feature adc_feature; 170 171 u32 sample_freq_avail[5]; 172 173 struct completion completion; 174 /* Ensure the timestamp is naturally aligned */ 175 struct { 176 u16 chan; 177 aligned_s64 timestamp; 178 } scan; 179 }; 180 181 struct vf610_chip_info { 182 u8 num_channels; 183 }; 184 185 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 }; 186 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 }; 187 188 static inline void vf610_adc_calculate_rates(struct vf610_adc *info) 189 { 190 struct vf610_adc_feature *adc_feature = &info->adc_feature; 191 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk); 192 u32 adck_period, lst_addr_min; 193 int divisor, i; 194 195 adck_rate = info->max_adck_rate[adc_feature->conv_mode]; 196 197 if (adck_rate) { 198 /* calculate clk divider which is within specification */ 199 divisor = ipg_rate / adck_rate; 200 adc_feature->clk_div = 1 << fls(divisor + 1); 201 } else { 202 /* fall-back value using a safe divisor */ 203 adc_feature->clk_div = 8; 204 } 205 206 adck_rate = ipg_rate / adc_feature->clk_div; 207 208 /* 209 * Determine the long sample time adder value to be used based 210 * on the default minimum sample time provided. 211 */ 212 adck_period = NSEC_PER_SEC / adck_rate; 213 lst_addr_min = adc_feature->default_sample_time / adck_period; 214 for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) { 215 if (vf610_lst_adder[i] > lst_addr_min) { 216 adc_feature->lst_adder_index = i; 217 break; 218 } 219 } 220 221 /* 222 * Calculate ADC sample frequencies 223 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock, 224 * which is the same as bus clock. 225 * 226 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder) 227 * SFCAdder: fixed to 6 ADCK cycles 228 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average. 229 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode 230 * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles 231 */ 232 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++) 233 info->sample_freq_avail[i] = 234 adck_rate / (6 + vf610_hw_avgs[i] * 235 (25 + vf610_lst_adder[adc_feature->lst_adder_index])); 236 } 237 238 static inline void vf610_adc_cfg_init(struct vf610_adc *info) 239 { 240 struct vf610_adc_feature *adc_feature = &info->adc_feature; 241 242 /* set default Configuration for ADC controller */ 243 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET; 244 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET; 245 246 adc_feature->calibration = true; 247 adc_feature->ovwren = true; 248 249 adc_feature->res_mode = 12; 250 adc_feature->sample_rate = 1; 251 252 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER; 253 254 vf610_adc_calculate_rates(info); 255 } 256 257 static void vf610_adc_cfg_post_set(struct vf610_adc *info) 258 { 259 struct vf610_adc_feature *adc_feature = &info->adc_feature; 260 int cfg_data = 0; 261 int gc_data = 0; 262 263 switch (adc_feature->clk_sel) { 264 case VF610_ADCIOC_ALTCLK_SET: 265 cfg_data |= VF610_ADC_ALTCLK_SEL; 266 break; 267 case VF610_ADCIOC_ADACK_SET: 268 cfg_data |= VF610_ADC_ADACK_SEL; 269 break; 270 default: 271 break; 272 } 273 274 /* low power set for calibration */ 275 cfg_data |= VF610_ADC_ADLPC_EN; 276 277 /* enable high speed for calibration */ 278 cfg_data |= VF610_ADC_ADHSC_EN; 279 280 /* voltage reference */ 281 switch (adc_feature->vol_ref) { 282 case VF610_ADCIOC_VR_VREF_SET: 283 break; 284 case VF610_ADCIOC_VR_VALT_SET: 285 cfg_data |= VF610_ADC_REFSEL_VALT; 286 break; 287 case VF610_ADCIOC_VR_VBG_SET: 288 cfg_data |= VF610_ADC_REFSEL_VBG; 289 break; 290 default: 291 dev_err(info->dev, "error voltage reference\n"); 292 } 293 294 /* data overwrite enable */ 295 if (adc_feature->ovwren) 296 cfg_data |= VF610_ADC_OVWREN; 297 298 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 299 writel(gc_data, info->regs + VF610_REG_ADC_GC); 300 } 301 302 static void vf610_adc_calibration(struct vf610_adc *info) 303 { 304 int adc_gc, hc_cfg; 305 306 if (!info->adc_feature.calibration) 307 return; 308 309 /* enable calibration interrupt */ 310 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE; 311 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 312 313 adc_gc = readl(info->regs + VF610_REG_ADC_GC); 314 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC); 315 316 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT)) 317 dev_err(info->dev, "Timeout for adc calibration\n"); 318 319 adc_gc = readl(info->regs + VF610_REG_ADC_GS); 320 if (adc_gc & VF610_ADC_CALF) 321 dev_err(info->dev, "ADC calibration failed\n"); 322 323 info->adc_feature.calibration = false; 324 } 325 326 static void vf610_adc_cfg_set(struct vf610_adc *info) 327 { 328 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 329 int cfg_data; 330 331 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 332 333 cfg_data &= ~VF610_ADC_ADLPC_EN; 334 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER) 335 cfg_data |= VF610_ADC_ADLPC_EN; 336 337 cfg_data &= ~VF610_ADC_ADHSC_EN; 338 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED) 339 cfg_data |= VF610_ADC_ADHSC_EN; 340 341 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 342 } 343 344 static void vf610_adc_sample_set(struct vf610_adc *info) 345 { 346 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 347 int cfg_data, gc_data; 348 349 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 350 gc_data = readl(info->regs + VF610_REG_ADC_GC); 351 352 /* resolution mode */ 353 cfg_data &= ~VF610_ADC_MODE_MASK; 354 switch (adc_feature->res_mode) { 355 case 8: 356 cfg_data |= VF610_ADC_MODE_BIT8; 357 break; 358 case 10: 359 cfg_data |= VF610_ADC_MODE_BIT10; 360 break; 361 case 12: 362 cfg_data |= VF610_ADC_MODE_BIT12; 363 break; 364 default: 365 dev_err(info->dev, "error resolution mode\n"); 366 break; 367 } 368 369 /* clock select and clock divider */ 370 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK); 371 switch (adc_feature->clk_div) { 372 case 1: 373 break; 374 case 2: 375 cfg_data |= VF610_ADC_CLK_DIV2; 376 break; 377 case 4: 378 cfg_data |= VF610_ADC_CLK_DIV4; 379 break; 380 case 8: 381 cfg_data |= VF610_ADC_CLK_DIV8; 382 break; 383 case 16: 384 switch (adc_feature->clk_sel) { 385 case VF610_ADCIOC_BUSCLK_SET: 386 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8; 387 break; 388 default: 389 dev_err(info->dev, "error clk divider\n"); 390 break; 391 } 392 break; 393 } 394 395 /* 396 * Set ADLSMP and ADSTS based on the Long Sample Time Adder value 397 * determined. 398 */ 399 switch (adc_feature->lst_adder_index) { 400 case VF610_ADCK_CYCLES_3: 401 break; 402 case VF610_ADCK_CYCLES_5: 403 cfg_data |= VF610_ADC_ADSTS_SHORT; 404 break; 405 case VF610_ADCK_CYCLES_7: 406 cfg_data |= VF610_ADC_ADSTS_NORMAL; 407 break; 408 case VF610_ADCK_CYCLES_9: 409 cfg_data |= VF610_ADC_ADSTS_LONG; 410 break; 411 case VF610_ADCK_CYCLES_13: 412 cfg_data |= VF610_ADC_ADLSMP_LONG; 413 break; 414 case VF610_ADCK_CYCLES_17: 415 cfg_data |= VF610_ADC_ADLSMP_LONG; 416 cfg_data |= VF610_ADC_ADSTS_SHORT; 417 break; 418 case VF610_ADCK_CYCLES_21: 419 cfg_data |= VF610_ADC_ADLSMP_LONG; 420 cfg_data |= VF610_ADC_ADSTS_NORMAL; 421 break; 422 case VF610_ADCK_CYCLES_25: 423 cfg_data |= VF610_ADC_ADLSMP_LONG; 424 cfg_data |= VF610_ADC_ADSTS_NORMAL; 425 break; 426 default: 427 dev_err(info->dev, "error in sample time select\n"); 428 } 429 430 /* update hardware average selection */ 431 cfg_data &= ~VF610_ADC_AVGS_MASK; 432 gc_data &= ~VF610_ADC_AVGEN; 433 switch (adc_feature->sample_rate) { 434 case VF610_ADC_SAMPLE_1: 435 break; 436 case VF610_ADC_SAMPLE_4: 437 gc_data |= VF610_ADC_AVGEN; 438 break; 439 case VF610_ADC_SAMPLE_8: 440 gc_data |= VF610_ADC_AVGEN; 441 cfg_data |= VF610_ADC_AVGS_8; 442 break; 443 case VF610_ADC_SAMPLE_16: 444 gc_data |= VF610_ADC_AVGEN; 445 cfg_data |= VF610_ADC_AVGS_16; 446 break; 447 case VF610_ADC_SAMPLE_32: 448 gc_data |= VF610_ADC_AVGEN; 449 cfg_data |= VF610_ADC_AVGS_32; 450 break; 451 default: 452 dev_err(info->dev, 453 "error hardware sample average select\n"); 454 } 455 456 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 457 writel(gc_data, info->regs + VF610_REG_ADC_GC); 458 } 459 460 static void vf610_adc_hw_init(struct vf610_adc *info) 461 { 462 /* CFG: Feature set */ 463 vf610_adc_cfg_post_set(info); 464 vf610_adc_sample_set(info); 465 466 /* adc calibration */ 467 vf610_adc_calibration(info); 468 469 /* CFG: power and speed set */ 470 vf610_adc_cfg_set(info); 471 } 472 473 static int vf610_set_conversion_mode(struct iio_dev *indio_dev, 474 const struct iio_chan_spec *chan, 475 unsigned int mode) 476 { 477 struct vf610_adc *info = iio_priv(indio_dev); 478 479 mutex_lock(&info->lock); 480 info->adc_feature.conv_mode = mode; 481 vf610_adc_calculate_rates(info); 482 vf610_adc_hw_init(info); 483 mutex_unlock(&info->lock); 484 485 return 0; 486 } 487 488 static int vf610_get_conversion_mode(struct iio_dev *indio_dev, 489 const struct iio_chan_spec *chan) 490 { 491 struct vf610_adc *info = iio_priv(indio_dev); 492 493 return info->adc_feature.conv_mode; 494 } 495 496 static const char * const vf610_conv_modes[] = { "normal", "high-speed", 497 "low-power" }; 498 499 static const struct iio_enum vf610_conversion_mode = { 500 .items = vf610_conv_modes, 501 .num_items = ARRAY_SIZE(vf610_conv_modes), 502 .get = vf610_get_conversion_mode, 503 .set = vf610_set_conversion_mode, 504 }; 505 506 static const struct iio_chan_spec_ext_info vf610_ext_info[] = { 507 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode), 508 { } 509 }; 510 511 #define VF610_ADC_CHAN(_idx, _chan_type) { \ 512 .type = (_chan_type), \ 513 .indexed = 1, \ 514 .channel = (_idx), \ 515 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 516 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 517 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 518 .ext_info = vf610_ext_info, \ 519 .scan_index = (_idx), \ 520 .scan_type = { \ 521 .sign = 'u', \ 522 .realbits = 12, \ 523 .storagebits = 16, \ 524 }, \ 525 } 526 527 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \ 528 .type = (_chan_type), \ 529 .channel = (_idx), \ 530 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 531 .scan_index = (_idx), \ 532 .scan_type = { \ 533 .sign = 'u', \ 534 .realbits = 12, \ 535 .storagebits = 16, \ 536 }, \ 537 } 538 539 static const struct iio_chan_spec vf610_adc_iio_channels[] = { 540 VF610_ADC_CHAN(0, IIO_VOLTAGE), 541 VF610_ADC_CHAN(1, IIO_VOLTAGE), 542 VF610_ADC_CHAN(2, IIO_VOLTAGE), 543 VF610_ADC_CHAN(3, IIO_VOLTAGE), 544 VF610_ADC_CHAN(4, IIO_VOLTAGE), 545 VF610_ADC_CHAN(5, IIO_VOLTAGE), 546 VF610_ADC_CHAN(6, IIO_VOLTAGE), 547 VF610_ADC_CHAN(7, IIO_VOLTAGE), 548 VF610_ADC_CHAN(8, IIO_VOLTAGE), 549 VF610_ADC_CHAN(9, IIO_VOLTAGE), 550 VF610_ADC_CHAN(10, IIO_VOLTAGE), 551 VF610_ADC_CHAN(11, IIO_VOLTAGE), 552 VF610_ADC_CHAN(12, IIO_VOLTAGE), 553 VF610_ADC_CHAN(13, IIO_VOLTAGE), 554 VF610_ADC_CHAN(14, IIO_VOLTAGE), 555 VF610_ADC_CHAN(15, IIO_VOLTAGE), 556 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP), 557 IIO_CHAN_SOFT_TIMESTAMP(32), 558 /* sentinel */ 559 }; 560 561 static int vf610_adc_read_data(struct vf610_adc *info) 562 { 563 int result; 564 565 result = readl(info->regs + VF610_REG_ADC_R0); 566 567 switch (info->adc_feature.res_mode) { 568 case 8: 569 result &= 0xFF; 570 break; 571 case 10: 572 result &= 0x3FF; 573 break; 574 case 12: 575 result &= 0xFFF; 576 break; 577 default: 578 break; 579 } 580 581 return result; 582 } 583 584 static irqreturn_t vf610_adc_isr(int irq, void *dev_id) 585 { 586 struct iio_dev *indio_dev = dev_id; 587 struct vf610_adc *info = iio_priv(indio_dev); 588 int coco; 589 590 coco = readl(info->regs + VF610_REG_ADC_HS); 591 if (coco & VF610_ADC_HS_COCO0) { 592 info->value = vf610_adc_read_data(info); 593 if (iio_buffer_enabled(indio_dev)) { 594 info->scan.chan = info->value; 595 iio_push_to_buffers_with_ts(indio_dev, &info->scan, 596 sizeof(info->scan), 597 iio_get_time_ns(indio_dev)); 598 iio_trigger_notify_done(indio_dev->trig); 599 } else 600 complete(&info->completion); 601 } 602 603 return IRQ_HANDLED; 604 } 605 606 static ssize_t vf610_show_samp_freq_avail(struct device *dev, 607 struct device_attribute *attr, char *buf) 608 { 609 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev)); 610 size_t len = 0; 611 int i; 612 613 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++) 614 len += scnprintf(buf + len, PAGE_SIZE - len, 615 "%u ", info->sample_freq_avail[i]); 616 617 /* replace trailing space by newline */ 618 buf[len - 1] = '\n'; 619 620 return len; 621 } 622 623 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail); 624 625 static struct attribute *vf610_attributes[] = { 626 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 627 NULL 628 }; 629 630 static const struct attribute_group vf610_attribute_group = { 631 .attrs = vf610_attributes, 632 }; 633 634 static int vf610_read_sample(struct vf610_adc *info, 635 struct iio_chan_spec const *chan, int *val) 636 { 637 unsigned int hc_cfg; 638 int ret; 639 640 guard(mutex)(&info->lock); 641 reinit_completion(&info->completion); 642 hc_cfg = VF610_ADC_ADCHC(chan->channel); 643 hc_cfg |= VF610_ADC_AIEN; 644 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 645 ret = wait_for_completion_interruptible_timeout(&info->completion, 646 VF610_ADC_TIMEOUT); 647 if (ret == 0) 648 return -ETIMEDOUT; 649 650 if (ret < 0) 651 return ret; 652 653 switch (chan->type) { 654 case IIO_VOLTAGE: 655 *val = info->value; 656 return 0; 657 case IIO_TEMP: 658 /* 659 * Calculate in degree Celsius times 1000 660 * Using the typical sensor slope of 1.84 mV/°C 661 * and VREFH_ADC at 3.3V, V at 25°C of 699 mV 662 */ 663 *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) * 664 1000000 / VF610_TEMP_SLOPE_COEFF; 665 666 return 0; 667 default: 668 return -EINVAL; 669 } 670 } 671 672 static int vf610_read_raw(struct iio_dev *indio_dev, 673 struct iio_chan_spec const *chan, 674 int *val, 675 int *val2, 676 long mask) 677 { 678 struct vf610_adc *info = iio_priv(indio_dev); 679 long ret; 680 681 switch (mask) { 682 case IIO_CHAN_INFO_RAW: 683 case IIO_CHAN_INFO_PROCESSED: 684 if (!iio_device_claim_direct(indio_dev)) 685 return -EBUSY; 686 ret = vf610_read_sample(info, chan, val); 687 iio_device_release_direct(indio_dev); 688 if (ret < 0) 689 return ret; 690 691 return IIO_VAL_INT; 692 693 case IIO_CHAN_INFO_SCALE: 694 *val = info->vref_uv / 1000; 695 *val2 = info->adc_feature.res_mode; 696 return IIO_VAL_FRACTIONAL_LOG2; 697 698 case IIO_CHAN_INFO_SAMP_FREQ: 699 *val = info->sample_freq_avail[info->adc_feature.sample_rate]; 700 *val2 = 0; 701 return IIO_VAL_INT; 702 703 default: 704 break; 705 } 706 707 return -EINVAL; 708 } 709 710 static int vf610_write_raw(struct iio_dev *indio_dev, 711 struct iio_chan_spec const *chan, 712 int val, 713 int val2, 714 long mask) 715 { 716 struct vf610_adc *info = iio_priv(indio_dev); 717 int i; 718 719 switch (mask) { 720 case IIO_CHAN_INFO_SAMP_FREQ: 721 for (i = 0; 722 i < ARRAY_SIZE(info->sample_freq_avail); 723 i++) 724 if (val == info->sample_freq_avail[i]) { 725 info->adc_feature.sample_rate = i; 726 vf610_adc_sample_set(info); 727 return 0; 728 } 729 break; 730 731 default: 732 break; 733 } 734 735 return -EINVAL; 736 } 737 738 static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev) 739 { 740 struct vf610_adc *info = iio_priv(indio_dev); 741 unsigned int channel; 742 int val; 743 744 val = readl(info->regs + VF610_REG_ADC_GC); 745 val |= VF610_ADC_ADCON; 746 writel(val, info->regs + VF610_REG_ADC_GC); 747 748 channel = find_first_bit(indio_dev->active_scan_mask, 749 iio_get_masklength(indio_dev)); 750 751 val = VF610_ADC_ADCHC(channel); 752 val |= VF610_ADC_AIEN; 753 754 writel(val, info->regs + VF610_REG_ADC_HC0); 755 756 return 0; 757 } 758 759 static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev) 760 { 761 struct vf610_adc *info = iio_priv(indio_dev); 762 unsigned int hc_cfg = 0; 763 int val; 764 765 val = readl(info->regs + VF610_REG_ADC_GC); 766 val &= ~VF610_ADC_ADCON; 767 writel(val, info->regs + VF610_REG_ADC_GC); 768 769 hc_cfg |= VF610_ADC_CONV_DISABLE; 770 hc_cfg &= ~VF610_ADC_AIEN; 771 772 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 773 774 return 0; 775 } 776 777 static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = { 778 .postenable = &vf610_adc_buffer_postenable, 779 .predisable = &vf610_adc_buffer_predisable, 780 .validate_scan_mask = &iio_validate_scan_mask_onehot, 781 }; 782 783 static int vf610_adc_reg_access(struct iio_dev *indio_dev, 784 unsigned reg, unsigned writeval, 785 unsigned *readval) 786 { 787 struct vf610_adc *info = iio_priv(indio_dev); 788 789 if ((readval == NULL) || 790 ((reg % 4) || (reg > VF610_REG_ADC_PCTL))) 791 return -EINVAL; 792 793 *readval = readl(info->regs + reg); 794 795 return 0; 796 } 797 798 static const struct iio_info vf610_adc_iio_info = { 799 .read_raw = &vf610_read_raw, 800 .write_raw = &vf610_write_raw, 801 .debugfs_reg_access = &vf610_adc_reg_access, 802 .attrs = &vf610_attribute_group, 803 }; 804 805 static const struct vf610_chip_info vf610_chip_info = { 806 .num_channels = ARRAY_SIZE(vf610_adc_iio_channels), 807 }; 808 809 static const struct vf610_chip_info imx6sx_chip_info = { 810 .num_channels = 4, 811 }; 812 813 static const struct of_device_id vf610_adc_match[] = { 814 { .compatible = "fsl,imx6sx-adc", .data = &imx6sx_chip_info}, 815 { .compatible = "fsl,vf610-adc", .data = &vf610_chip_info}, 816 { } 817 }; 818 MODULE_DEVICE_TABLE(of, vf610_adc_match); 819 820 static void vf610_adc_action_remove(void *d) 821 { 822 struct vf610_adc *info = d; 823 824 regulator_disable(info->vref); 825 } 826 827 static int vf610_adc_probe(struct platform_device *pdev) 828 { 829 const struct vf610_chip_info *chip_info; 830 struct device *dev = &pdev->dev; 831 struct vf610_adc *info; 832 struct iio_dev *indio_dev; 833 int irq; 834 int ret; 835 836 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc)); 837 if (!indio_dev) 838 return dev_err_probe(&pdev->dev, -ENOMEM, "Failed allocating iio device\n"); 839 840 info = iio_priv(indio_dev); 841 info->dev = &pdev->dev; 842 843 info->regs = devm_platform_ioremap_resource(pdev, 0); 844 if (IS_ERR(info->regs)) 845 return PTR_ERR(info->regs); 846 847 chip_info = device_get_match_data(dev); 848 849 irq = platform_get_irq(pdev, 0); 850 if (irq < 0) 851 return irq; 852 853 ret = devm_request_irq(info->dev, irq, 854 vf610_adc_isr, 0, 855 dev_name(&pdev->dev), indio_dev); 856 if (ret < 0) 857 return dev_err_probe(&pdev->dev, ret, "failed requesting irq, irq = %d\n", irq); 858 859 info->clk = devm_clk_get_enabled(&pdev->dev, "adc"); 860 if (IS_ERR(info->clk)) 861 return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), "failed getting clock\n"); 862 863 info->vref = devm_regulator_get(&pdev->dev, "vref"); 864 if (IS_ERR(info->vref)) 865 return PTR_ERR(info->vref); 866 867 ret = regulator_enable(info->vref); 868 if (ret) 869 return ret; 870 871 ret = devm_add_action_or_reset(&pdev->dev, vf610_adc_action_remove, info); 872 if (ret) 873 return ret; 874 875 info->vref_uv = regulator_get_voltage(info->vref); 876 877 device_property_read_u32_array(dev, "fsl,adck-max-frequency", info->max_adck_rate, 3); 878 879 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME; 880 device_property_read_u32(dev, "min-sample-time", &info->adc_feature.default_sample_time); 881 882 platform_set_drvdata(pdev, indio_dev); 883 884 init_completion(&info->completion); 885 886 indio_dev->name = dev_name(&pdev->dev); 887 indio_dev->info = &vf610_adc_iio_info; 888 indio_dev->modes = INDIO_DIRECT_MODE; 889 indio_dev->channels = vf610_adc_iio_channels; 890 indio_dev->num_channels = chip_info->num_channels; 891 892 vf610_adc_cfg_init(info); 893 vf610_adc_hw_init(info); 894 895 ret = devm_iio_triggered_buffer_setup(&pdev->dev, indio_dev, &iio_pollfunc_store_time, 896 NULL, &iio_triggered_buffer_setup_ops); 897 if (ret < 0) 898 return dev_err_probe(&pdev->dev, ret, "Couldn't initialise the buffer\n"); 899 900 mutex_init(&info->lock); 901 902 ret = devm_iio_device_register(&pdev->dev, indio_dev); 903 if (ret) 904 return dev_err_probe(&pdev->dev, ret, "Couldn't register the device.\n"); 905 906 return 0; 907 } 908 909 static int vf610_adc_suspend(struct device *dev) 910 { 911 struct iio_dev *indio_dev = dev_get_drvdata(dev); 912 struct vf610_adc *info = iio_priv(indio_dev); 913 int hc_cfg; 914 915 /* ADC controller enters to stop mode */ 916 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0); 917 hc_cfg |= VF610_ADC_CONV_DISABLE; 918 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 919 920 clk_disable_unprepare(info->clk); 921 regulator_disable(info->vref); 922 923 return 0; 924 } 925 926 static int vf610_adc_resume(struct device *dev) 927 { 928 struct iio_dev *indio_dev = dev_get_drvdata(dev); 929 struct vf610_adc *info = iio_priv(indio_dev); 930 int ret; 931 932 ret = regulator_enable(info->vref); 933 if (ret) 934 return ret; 935 936 ret = clk_prepare_enable(info->clk); 937 if (ret) 938 goto disable_reg; 939 940 vf610_adc_hw_init(info); 941 942 return 0; 943 944 disable_reg: 945 regulator_disable(info->vref); 946 return ret; 947 } 948 949 static DEFINE_SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, 950 vf610_adc_resume); 951 952 static struct platform_driver vf610_adc_driver = { 953 .probe = vf610_adc_probe, 954 .driver = { 955 .name = DRIVER_NAME, 956 .of_match_table = vf610_adc_match, 957 .pm = pm_sleep_ptr(&vf610_adc_pm_ops), 958 }, 959 }; 960 961 module_platform_driver(vf610_adc_driver); 962 963 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>"); 964 MODULE_DESCRIPTION("Freescale VF610 ADC driver"); 965 MODULE_LICENSE("GPL v2"); 966