1 /* 2 * Freescale Vybrid vf610 ADC driver 3 * 4 * Copyright 2013 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/interrupt.h> 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/slab.h> 27 #include <linux/io.h> 28 #include <linux/clk.h> 29 #include <linux/completion.h> 30 #include <linux/of.h> 31 #include <linux/of_irq.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/of_platform.h> 34 #include <linux/err.h> 35 36 #include <linux/iio/iio.h> 37 #include <linux/iio/sysfs.h> 38 #include <linux/iio/driver.h> 39 40 /* This will be the driver name the kernel reports */ 41 #define DRIVER_NAME "vf610-adc" 42 43 /* Vybrid/IMX ADC registers */ 44 #define VF610_REG_ADC_HC0 0x00 45 #define VF610_REG_ADC_HC1 0x04 46 #define VF610_REG_ADC_HS 0x08 47 #define VF610_REG_ADC_R0 0x0c 48 #define VF610_REG_ADC_R1 0x10 49 #define VF610_REG_ADC_CFG 0x14 50 #define VF610_REG_ADC_GC 0x18 51 #define VF610_REG_ADC_GS 0x1c 52 #define VF610_REG_ADC_CV 0x20 53 #define VF610_REG_ADC_OFS 0x24 54 #define VF610_REG_ADC_CAL 0x28 55 #define VF610_REG_ADC_PCTL 0x30 56 57 /* Configuration register field define */ 58 #define VF610_ADC_MODE_BIT8 0x00 59 #define VF610_ADC_MODE_BIT10 0x04 60 #define VF610_ADC_MODE_BIT12 0x08 61 #define VF610_ADC_MODE_MASK 0x0c 62 #define VF610_ADC_BUSCLK2_SEL 0x01 63 #define VF610_ADC_ALTCLK_SEL 0x02 64 #define VF610_ADC_ADACK_SEL 0x03 65 #define VF610_ADC_ADCCLK_MASK 0x03 66 #define VF610_ADC_CLK_DIV2 0x20 67 #define VF610_ADC_CLK_DIV4 0x40 68 #define VF610_ADC_CLK_DIV8 0x60 69 #define VF610_ADC_CLK_MASK 0x60 70 #define VF610_ADC_ADLSMP_LONG 0x10 71 #define VF610_ADC_ADSTS_MASK 0x300 72 #define VF610_ADC_ADLPC_EN 0x80 73 #define VF610_ADC_ADHSC_EN 0x400 74 #define VF610_ADC_REFSEL_VALT 0x100 75 #define VF610_ADC_REFSEL_VBG 0x1000 76 #define VF610_ADC_ADTRG_HARD 0x2000 77 #define VF610_ADC_AVGS_8 0x4000 78 #define VF610_ADC_AVGS_16 0x8000 79 #define VF610_ADC_AVGS_32 0xC000 80 #define VF610_ADC_AVGS_MASK 0xC000 81 #define VF610_ADC_OVWREN 0x10000 82 83 /* General control register field define */ 84 #define VF610_ADC_ADACKEN 0x1 85 #define VF610_ADC_DMAEN 0x2 86 #define VF610_ADC_ACREN 0x4 87 #define VF610_ADC_ACFGT 0x8 88 #define VF610_ADC_ACFE 0x10 89 #define VF610_ADC_AVGEN 0x20 90 #define VF610_ADC_ADCON 0x40 91 #define VF610_ADC_CAL 0x80 92 93 /* Other field define */ 94 #define VF610_ADC_ADCHC(x) ((x) & 0x1F) 95 #define VF610_ADC_AIEN (0x1 << 7) 96 #define VF610_ADC_CONV_DISABLE 0x1F 97 #define VF610_ADC_HS_COCO0 0x1 98 #define VF610_ADC_CALF 0x2 99 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100) 100 101 enum clk_sel { 102 VF610_ADCIOC_BUSCLK_SET, 103 VF610_ADCIOC_ALTCLK_SET, 104 VF610_ADCIOC_ADACK_SET, 105 }; 106 107 enum vol_ref { 108 VF610_ADCIOC_VR_VREF_SET, 109 VF610_ADCIOC_VR_VALT_SET, 110 VF610_ADCIOC_VR_VBG_SET, 111 }; 112 113 enum average_sel { 114 VF610_ADC_SAMPLE_1, 115 VF610_ADC_SAMPLE_4, 116 VF610_ADC_SAMPLE_8, 117 VF610_ADC_SAMPLE_16, 118 VF610_ADC_SAMPLE_32, 119 }; 120 121 enum conversion_mode_sel { 122 VF610_ADC_CONV_NORMAL, 123 VF610_ADC_CONV_HIGH_SPEED, 124 VF610_ADC_CONV_LOW_POWER, 125 }; 126 127 struct vf610_adc_feature { 128 enum clk_sel clk_sel; 129 enum vol_ref vol_ref; 130 enum conversion_mode_sel conv_mode; 131 132 int clk_div; 133 int sample_rate; 134 int res_mode; 135 136 bool calibration; 137 bool ovwren; 138 }; 139 140 struct vf610_adc { 141 struct device *dev; 142 void __iomem *regs; 143 struct clk *clk; 144 145 u32 vref_uv; 146 u32 value; 147 struct regulator *vref; 148 149 u32 max_adck_rate[3]; 150 struct vf610_adc_feature adc_feature; 151 152 u32 sample_freq_avail[5]; 153 154 struct completion completion; 155 }; 156 157 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 }; 158 159 static inline void vf610_adc_calculate_rates(struct vf610_adc *info) 160 { 161 struct vf610_adc_feature *adc_feature = &info->adc_feature; 162 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk); 163 int divisor, i; 164 165 adck_rate = info->max_adck_rate[adc_feature->conv_mode]; 166 167 if (adck_rate) { 168 /* calculate clk divider which is within specification */ 169 divisor = ipg_rate / adck_rate; 170 adc_feature->clk_div = 1 << fls(divisor + 1); 171 } else { 172 /* fall-back value using a safe divisor */ 173 adc_feature->clk_div = 8; 174 } 175 176 /* 177 * Calculate ADC sample frequencies 178 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock, 179 * which is the same as bus clock. 180 * 181 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder) 182 * SFCAdder: fixed to 6 ADCK cycles 183 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average. 184 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode 185 * LSTAdder(Long Sample Time): fixed to 3 ADCK cycles 186 */ 187 adck_rate = ipg_rate / info->adc_feature.clk_div; 188 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++) 189 info->sample_freq_avail[i] = 190 adck_rate / (6 + vf610_hw_avgs[i] * (25 + 3)); 191 } 192 193 static inline void vf610_adc_cfg_init(struct vf610_adc *info) 194 { 195 struct vf610_adc_feature *adc_feature = &info->adc_feature; 196 197 /* set default Configuration for ADC controller */ 198 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET; 199 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET; 200 201 adc_feature->calibration = true; 202 adc_feature->ovwren = true; 203 204 adc_feature->res_mode = 12; 205 adc_feature->sample_rate = 1; 206 207 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER; 208 209 vf610_adc_calculate_rates(info); 210 } 211 212 static void vf610_adc_cfg_post_set(struct vf610_adc *info) 213 { 214 struct vf610_adc_feature *adc_feature = &info->adc_feature; 215 int cfg_data = 0; 216 int gc_data = 0; 217 218 switch (adc_feature->clk_sel) { 219 case VF610_ADCIOC_ALTCLK_SET: 220 cfg_data |= VF610_ADC_ALTCLK_SEL; 221 break; 222 case VF610_ADCIOC_ADACK_SET: 223 cfg_data |= VF610_ADC_ADACK_SEL; 224 break; 225 default: 226 break; 227 } 228 229 /* low power set for calibration */ 230 cfg_data |= VF610_ADC_ADLPC_EN; 231 232 /* enable high speed for calibration */ 233 cfg_data |= VF610_ADC_ADHSC_EN; 234 235 /* voltage reference */ 236 switch (adc_feature->vol_ref) { 237 case VF610_ADCIOC_VR_VREF_SET: 238 break; 239 case VF610_ADCIOC_VR_VALT_SET: 240 cfg_data |= VF610_ADC_REFSEL_VALT; 241 break; 242 case VF610_ADCIOC_VR_VBG_SET: 243 cfg_data |= VF610_ADC_REFSEL_VBG; 244 break; 245 default: 246 dev_err(info->dev, "error voltage reference\n"); 247 } 248 249 /* data overwrite enable */ 250 if (adc_feature->ovwren) 251 cfg_data |= VF610_ADC_OVWREN; 252 253 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 254 writel(gc_data, info->regs + VF610_REG_ADC_GC); 255 } 256 257 static void vf610_adc_calibration(struct vf610_adc *info) 258 { 259 int adc_gc, hc_cfg; 260 261 if (!info->adc_feature.calibration) 262 return; 263 264 /* enable calibration interrupt */ 265 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE; 266 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 267 268 adc_gc = readl(info->regs + VF610_REG_ADC_GC); 269 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC); 270 271 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT)) 272 dev_err(info->dev, "Timeout for adc calibration\n"); 273 274 adc_gc = readl(info->regs + VF610_REG_ADC_GS); 275 if (adc_gc & VF610_ADC_CALF) 276 dev_err(info->dev, "ADC calibration failed\n"); 277 278 info->adc_feature.calibration = false; 279 } 280 281 static void vf610_adc_cfg_set(struct vf610_adc *info) 282 { 283 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 284 int cfg_data; 285 286 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 287 288 cfg_data &= ~VF610_ADC_ADLPC_EN; 289 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER) 290 cfg_data |= VF610_ADC_ADLPC_EN; 291 292 cfg_data &= ~VF610_ADC_ADHSC_EN; 293 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED) 294 cfg_data |= VF610_ADC_ADHSC_EN; 295 296 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 297 } 298 299 static void vf610_adc_sample_set(struct vf610_adc *info) 300 { 301 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 302 int cfg_data, gc_data; 303 304 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 305 gc_data = readl(info->regs + VF610_REG_ADC_GC); 306 307 /* resolution mode */ 308 cfg_data &= ~VF610_ADC_MODE_MASK; 309 switch (adc_feature->res_mode) { 310 case 8: 311 cfg_data |= VF610_ADC_MODE_BIT8; 312 break; 313 case 10: 314 cfg_data |= VF610_ADC_MODE_BIT10; 315 break; 316 case 12: 317 cfg_data |= VF610_ADC_MODE_BIT12; 318 break; 319 default: 320 dev_err(info->dev, "error resolution mode\n"); 321 break; 322 } 323 324 /* clock select and clock divider */ 325 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK); 326 switch (adc_feature->clk_div) { 327 case 1: 328 break; 329 case 2: 330 cfg_data |= VF610_ADC_CLK_DIV2; 331 break; 332 case 4: 333 cfg_data |= VF610_ADC_CLK_DIV4; 334 break; 335 case 8: 336 cfg_data |= VF610_ADC_CLK_DIV8; 337 break; 338 case 16: 339 switch (adc_feature->clk_sel) { 340 case VF610_ADCIOC_BUSCLK_SET: 341 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8; 342 break; 343 default: 344 dev_err(info->dev, "error clk divider\n"); 345 break; 346 } 347 break; 348 } 349 350 /* Use the short sample mode */ 351 cfg_data &= ~(VF610_ADC_ADLSMP_LONG | VF610_ADC_ADSTS_MASK); 352 353 /* update hardware average selection */ 354 cfg_data &= ~VF610_ADC_AVGS_MASK; 355 gc_data &= ~VF610_ADC_AVGEN; 356 switch (adc_feature->sample_rate) { 357 case VF610_ADC_SAMPLE_1: 358 break; 359 case VF610_ADC_SAMPLE_4: 360 gc_data |= VF610_ADC_AVGEN; 361 break; 362 case VF610_ADC_SAMPLE_8: 363 gc_data |= VF610_ADC_AVGEN; 364 cfg_data |= VF610_ADC_AVGS_8; 365 break; 366 case VF610_ADC_SAMPLE_16: 367 gc_data |= VF610_ADC_AVGEN; 368 cfg_data |= VF610_ADC_AVGS_16; 369 break; 370 case VF610_ADC_SAMPLE_32: 371 gc_data |= VF610_ADC_AVGEN; 372 cfg_data |= VF610_ADC_AVGS_32; 373 break; 374 default: 375 dev_err(info->dev, 376 "error hardware sample average select\n"); 377 } 378 379 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 380 writel(gc_data, info->regs + VF610_REG_ADC_GC); 381 } 382 383 static void vf610_adc_hw_init(struct vf610_adc *info) 384 { 385 /* CFG: Feature set */ 386 vf610_adc_cfg_post_set(info); 387 vf610_adc_sample_set(info); 388 389 /* adc calibration */ 390 vf610_adc_calibration(info); 391 392 /* CFG: power and speed set */ 393 vf610_adc_cfg_set(info); 394 } 395 396 static int vf610_set_conversion_mode(struct iio_dev *indio_dev, 397 const struct iio_chan_spec *chan, 398 unsigned int mode) 399 { 400 struct vf610_adc *info = iio_priv(indio_dev); 401 402 mutex_lock(&indio_dev->mlock); 403 info->adc_feature.conv_mode = mode; 404 vf610_adc_calculate_rates(info); 405 vf610_adc_hw_init(info); 406 mutex_unlock(&indio_dev->mlock); 407 408 return 0; 409 } 410 411 static int vf610_get_conversion_mode(struct iio_dev *indio_dev, 412 const struct iio_chan_spec *chan) 413 { 414 struct vf610_adc *info = iio_priv(indio_dev); 415 416 return info->adc_feature.conv_mode; 417 } 418 419 static const char * const vf610_conv_modes[] = { "normal", "high-speed", 420 "low-power" }; 421 422 static const struct iio_enum vf610_conversion_mode = { 423 .items = vf610_conv_modes, 424 .num_items = ARRAY_SIZE(vf610_conv_modes), 425 .get = vf610_get_conversion_mode, 426 .set = vf610_set_conversion_mode, 427 }; 428 429 static const struct iio_chan_spec_ext_info vf610_ext_info[] = { 430 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode), 431 {}, 432 }; 433 434 #define VF610_ADC_CHAN(_idx, _chan_type) { \ 435 .type = (_chan_type), \ 436 .indexed = 1, \ 437 .channel = (_idx), \ 438 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 439 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 440 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 441 .ext_info = vf610_ext_info, \ 442 } 443 444 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \ 445 .type = (_chan_type), \ 446 .channel = (_idx), \ 447 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 448 } 449 450 static const struct iio_chan_spec vf610_adc_iio_channels[] = { 451 VF610_ADC_CHAN(0, IIO_VOLTAGE), 452 VF610_ADC_CHAN(1, IIO_VOLTAGE), 453 VF610_ADC_CHAN(2, IIO_VOLTAGE), 454 VF610_ADC_CHAN(3, IIO_VOLTAGE), 455 VF610_ADC_CHAN(4, IIO_VOLTAGE), 456 VF610_ADC_CHAN(5, IIO_VOLTAGE), 457 VF610_ADC_CHAN(6, IIO_VOLTAGE), 458 VF610_ADC_CHAN(7, IIO_VOLTAGE), 459 VF610_ADC_CHAN(8, IIO_VOLTAGE), 460 VF610_ADC_CHAN(9, IIO_VOLTAGE), 461 VF610_ADC_CHAN(10, IIO_VOLTAGE), 462 VF610_ADC_CHAN(11, IIO_VOLTAGE), 463 VF610_ADC_CHAN(12, IIO_VOLTAGE), 464 VF610_ADC_CHAN(13, IIO_VOLTAGE), 465 VF610_ADC_CHAN(14, IIO_VOLTAGE), 466 VF610_ADC_CHAN(15, IIO_VOLTAGE), 467 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP), 468 /* sentinel */ 469 }; 470 471 static int vf610_adc_read_data(struct vf610_adc *info) 472 { 473 int result; 474 475 result = readl(info->regs + VF610_REG_ADC_R0); 476 477 switch (info->adc_feature.res_mode) { 478 case 8: 479 result &= 0xFF; 480 break; 481 case 10: 482 result &= 0x3FF; 483 break; 484 case 12: 485 result &= 0xFFF; 486 break; 487 default: 488 break; 489 } 490 491 return result; 492 } 493 494 static irqreturn_t vf610_adc_isr(int irq, void *dev_id) 495 { 496 struct vf610_adc *info = (struct vf610_adc *)dev_id; 497 int coco; 498 499 coco = readl(info->regs + VF610_REG_ADC_HS); 500 if (coco & VF610_ADC_HS_COCO0) { 501 info->value = vf610_adc_read_data(info); 502 complete(&info->completion); 503 } 504 505 return IRQ_HANDLED; 506 } 507 508 static ssize_t vf610_show_samp_freq_avail(struct device *dev, 509 struct device_attribute *attr, char *buf) 510 { 511 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev)); 512 size_t len = 0; 513 int i; 514 515 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++) 516 len += scnprintf(buf + len, PAGE_SIZE - len, 517 "%u ", info->sample_freq_avail[i]); 518 519 /* replace trailing space by newline */ 520 buf[len - 1] = '\n'; 521 522 return len; 523 } 524 525 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail); 526 527 static struct attribute *vf610_attributes[] = { 528 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 529 NULL 530 }; 531 532 static const struct attribute_group vf610_attribute_group = { 533 .attrs = vf610_attributes, 534 }; 535 536 static int vf610_read_raw(struct iio_dev *indio_dev, 537 struct iio_chan_spec const *chan, 538 int *val, 539 int *val2, 540 long mask) 541 { 542 struct vf610_adc *info = iio_priv(indio_dev); 543 unsigned int hc_cfg; 544 long ret; 545 546 switch (mask) { 547 case IIO_CHAN_INFO_RAW: 548 case IIO_CHAN_INFO_PROCESSED: 549 mutex_lock(&indio_dev->mlock); 550 reinit_completion(&info->completion); 551 552 hc_cfg = VF610_ADC_ADCHC(chan->channel); 553 hc_cfg |= VF610_ADC_AIEN; 554 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 555 ret = wait_for_completion_interruptible_timeout 556 (&info->completion, VF610_ADC_TIMEOUT); 557 if (ret == 0) { 558 mutex_unlock(&indio_dev->mlock); 559 return -ETIMEDOUT; 560 } 561 if (ret < 0) { 562 mutex_unlock(&indio_dev->mlock); 563 return ret; 564 } 565 566 switch (chan->type) { 567 case IIO_VOLTAGE: 568 *val = info->value; 569 break; 570 case IIO_TEMP: 571 /* 572 * Calculate in degree Celsius times 1000 573 * Using sensor slope of 1.84 mV/°C and 574 * V at 25°C of 696 mV 575 */ 576 *val = 25000 - ((int)info->value - 864) * 1000000 / 1840; 577 break; 578 default: 579 mutex_unlock(&indio_dev->mlock); 580 return -EINVAL; 581 } 582 583 mutex_unlock(&indio_dev->mlock); 584 return IIO_VAL_INT; 585 586 case IIO_CHAN_INFO_SCALE: 587 *val = info->vref_uv / 1000; 588 *val2 = info->adc_feature.res_mode; 589 return IIO_VAL_FRACTIONAL_LOG2; 590 591 case IIO_CHAN_INFO_SAMP_FREQ: 592 *val = info->sample_freq_avail[info->adc_feature.sample_rate]; 593 *val2 = 0; 594 return IIO_VAL_INT; 595 596 default: 597 break; 598 } 599 600 return -EINVAL; 601 } 602 603 static int vf610_write_raw(struct iio_dev *indio_dev, 604 struct iio_chan_spec const *chan, 605 int val, 606 int val2, 607 long mask) 608 { 609 struct vf610_adc *info = iio_priv(indio_dev); 610 int i; 611 612 switch (mask) { 613 case IIO_CHAN_INFO_SAMP_FREQ: 614 for (i = 0; 615 i < ARRAY_SIZE(info->sample_freq_avail); 616 i++) 617 if (val == info->sample_freq_avail[i]) { 618 info->adc_feature.sample_rate = i; 619 vf610_adc_sample_set(info); 620 return 0; 621 } 622 break; 623 624 default: 625 break; 626 } 627 628 return -EINVAL; 629 } 630 631 static int vf610_adc_reg_access(struct iio_dev *indio_dev, 632 unsigned reg, unsigned writeval, 633 unsigned *readval) 634 { 635 struct vf610_adc *info = iio_priv(indio_dev); 636 637 if ((readval == NULL) || 638 ((reg % 4) || (reg > VF610_REG_ADC_PCTL))) 639 return -EINVAL; 640 641 *readval = readl(info->regs + reg); 642 643 return 0; 644 } 645 646 static const struct iio_info vf610_adc_iio_info = { 647 .driver_module = THIS_MODULE, 648 .read_raw = &vf610_read_raw, 649 .write_raw = &vf610_write_raw, 650 .debugfs_reg_access = &vf610_adc_reg_access, 651 .attrs = &vf610_attribute_group, 652 }; 653 654 static const struct of_device_id vf610_adc_match[] = { 655 { .compatible = "fsl,vf610-adc", }, 656 { /* sentinel */ } 657 }; 658 MODULE_DEVICE_TABLE(of, vf610_adc_match); 659 660 static int vf610_adc_probe(struct platform_device *pdev) 661 { 662 struct vf610_adc *info; 663 struct iio_dev *indio_dev; 664 struct resource *mem; 665 int irq; 666 int ret; 667 668 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc)); 669 if (!indio_dev) { 670 dev_err(&pdev->dev, "Failed allocating iio device\n"); 671 return -ENOMEM; 672 } 673 674 info = iio_priv(indio_dev); 675 info->dev = &pdev->dev; 676 677 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 678 info->regs = devm_ioremap_resource(&pdev->dev, mem); 679 if (IS_ERR(info->regs)) 680 return PTR_ERR(info->regs); 681 682 irq = platform_get_irq(pdev, 0); 683 if (irq < 0) { 684 dev_err(&pdev->dev, "no irq resource?\n"); 685 return irq; 686 } 687 688 ret = devm_request_irq(info->dev, irq, 689 vf610_adc_isr, 0, 690 dev_name(&pdev->dev), info); 691 if (ret < 0) { 692 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq); 693 return ret; 694 } 695 696 info->clk = devm_clk_get(&pdev->dev, "adc"); 697 if (IS_ERR(info->clk)) { 698 dev_err(&pdev->dev, "failed getting clock, err = %ld\n", 699 PTR_ERR(info->clk)); 700 return PTR_ERR(info->clk); 701 } 702 703 info->vref = devm_regulator_get(&pdev->dev, "vref"); 704 if (IS_ERR(info->vref)) 705 return PTR_ERR(info->vref); 706 707 ret = regulator_enable(info->vref); 708 if (ret) 709 return ret; 710 711 info->vref_uv = regulator_get_voltage(info->vref); 712 713 of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency", 714 info->max_adck_rate, 3); 715 716 platform_set_drvdata(pdev, indio_dev); 717 718 init_completion(&info->completion); 719 720 indio_dev->name = dev_name(&pdev->dev); 721 indio_dev->dev.parent = &pdev->dev; 722 indio_dev->dev.of_node = pdev->dev.of_node; 723 indio_dev->info = &vf610_adc_iio_info; 724 indio_dev->modes = INDIO_DIRECT_MODE; 725 indio_dev->channels = vf610_adc_iio_channels; 726 indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels); 727 728 ret = clk_prepare_enable(info->clk); 729 if (ret) { 730 dev_err(&pdev->dev, 731 "Could not prepare or enable the clock.\n"); 732 goto error_adc_clk_enable; 733 } 734 735 vf610_adc_cfg_init(info); 736 vf610_adc_hw_init(info); 737 738 ret = iio_device_register(indio_dev); 739 if (ret) { 740 dev_err(&pdev->dev, "Couldn't register the device.\n"); 741 goto error_iio_device_register; 742 } 743 744 return 0; 745 746 747 error_iio_device_register: 748 clk_disable_unprepare(info->clk); 749 error_adc_clk_enable: 750 regulator_disable(info->vref); 751 752 return ret; 753 } 754 755 static int vf610_adc_remove(struct platform_device *pdev) 756 { 757 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 758 struct vf610_adc *info = iio_priv(indio_dev); 759 760 iio_device_unregister(indio_dev); 761 regulator_disable(info->vref); 762 clk_disable_unprepare(info->clk); 763 764 return 0; 765 } 766 767 #ifdef CONFIG_PM_SLEEP 768 static int vf610_adc_suspend(struct device *dev) 769 { 770 struct iio_dev *indio_dev = dev_get_drvdata(dev); 771 struct vf610_adc *info = iio_priv(indio_dev); 772 int hc_cfg; 773 774 /* ADC controller enters to stop mode */ 775 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0); 776 hc_cfg |= VF610_ADC_CONV_DISABLE; 777 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 778 779 clk_disable_unprepare(info->clk); 780 regulator_disable(info->vref); 781 782 return 0; 783 } 784 785 static int vf610_adc_resume(struct device *dev) 786 { 787 struct iio_dev *indio_dev = dev_get_drvdata(dev); 788 struct vf610_adc *info = iio_priv(indio_dev); 789 int ret; 790 791 ret = regulator_enable(info->vref); 792 if (ret) 793 return ret; 794 795 ret = clk_prepare_enable(info->clk); 796 if (ret) 797 goto disable_reg; 798 799 vf610_adc_hw_init(info); 800 801 return 0; 802 803 disable_reg: 804 regulator_disable(info->vref); 805 return ret; 806 } 807 #endif 808 809 static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume); 810 811 static struct platform_driver vf610_adc_driver = { 812 .probe = vf610_adc_probe, 813 .remove = vf610_adc_remove, 814 .driver = { 815 .name = DRIVER_NAME, 816 .of_match_table = vf610_adc_match, 817 .pm = &vf610_adc_pm_ops, 818 }, 819 }; 820 821 module_platform_driver(vf610_adc_driver); 822 823 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>"); 824 MODULE_DESCRIPTION("Freescale VF610 ADC driver"); 825 MODULE_LICENSE("GPL v2"); 826