1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale Vybrid vf610 ADC driver 4 * 5 * Copyright 2013 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/mutex.h> 11 #include <linux/property.h> 12 #include <linux/platform_device.h> 13 #include <linux/interrupt.h> 14 #include <linux/cleanup.h> 15 #include <linux/delay.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/io.h> 19 #include <linux/clk.h> 20 #include <linux/completion.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/err.h> 23 24 #include <linux/iio/iio.h> 25 #include <linux/iio/buffer.h> 26 #include <linux/iio/sysfs.h> 27 #include <linux/iio/trigger.h> 28 #include <linux/iio/trigger_consumer.h> 29 #include <linux/iio/triggered_buffer.h> 30 31 /* Vybrid/IMX ADC registers */ 32 #define VF610_REG_ADC_HC0 0x00 33 #define VF610_REG_ADC_HC1 0x04 34 #define VF610_REG_ADC_HS 0x08 35 #define VF610_REG_ADC_R0 0x0c 36 #define VF610_REG_ADC_R1 0x10 37 #define VF610_REG_ADC_CFG 0x14 38 #define VF610_REG_ADC_GC 0x18 39 #define VF610_REG_ADC_GS 0x1c 40 #define VF610_REG_ADC_CV 0x20 41 #define VF610_REG_ADC_OFS 0x24 42 #define VF610_REG_ADC_CAL 0x28 43 #define VF610_REG_ADC_PCTL 0x30 44 45 /* Configuration register field define */ 46 #define VF610_ADC_MODE_BIT8 0x00 47 #define VF610_ADC_MODE_BIT10 0x04 48 #define VF610_ADC_MODE_BIT12 0x08 49 #define VF610_ADC_MODE_MASK 0x0c 50 #define VF610_ADC_BUSCLK2_SEL 0x01 51 #define VF610_ADC_ALTCLK_SEL 0x02 52 #define VF610_ADC_ADACK_SEL 0x03 53 #define VF610_ADC_ADCCLK_MASK 0x03 54 #define VF610_ADC_CLK_DIV2 0x20 55 #define VF610_ADC_CLK_DIV4 0x40 56 #define VF610_ADC_CLK_DIV8 0x60 57 #define VF610_ADC_CLK_MASK 0x60 58 #define VF610_ADC_ADLSMP_LONG 0x10 59 #define VF610_ADC_ADSTS_SHORT 0x100 60 #define VF610_ADC_ADSTS_NORMAL 0x200 61 #define VF610_ADC_ADSTS_LONG 0x300 62 #define VF610_ADC_ADSTS_MASK 0x300 63 #define VF610_ADC_ADLPC_EN 0x80 64 #define VF610_ADC_ADHSC_EN 0x400 65 #define VF610_ADC_REFSEL_VALT 0x800 66 #define VF610_ADC_REFSEL_VBG 0x1000 67 #define VF610_ADC_ADTRG_HARD 0x2000 68 #define VF610_ADC_AVGS_8 0x4000 69 #define VF610_ADC_AVGS_16 0x8000 70 #define VF610_ADC_AVGS_32 0xC000 71 #define VF610_ADC_AVGS_MASK 0xC000 72 #define VF610_ADC_OVWREN 0x10000 73 74 /* General control register field define */ 75 #define VF610_ADC_ADACKEN 0x1 76 #define VF610_ADC_DMAEN 0x2 77 #define VF610_ADC_ACREN 0x4 78 #define VF610_ADC_ACFGT 0x8 79 #define VF610_ADC_ACFE 0x10 80 #define VF610_ADC_AVGEN 0x20 81 #define VF610_ADC_ADCON 0x40 82 #define VF610_ADC_CAL 0x80 83 84 /* Other field define */ 85 #define VF610_ADC_ADCHC(x) ((x) & 0x1F) 86 #define VF610_ADC_AIEN (0x1 << 7) 87 #define VF610_ADC_CONV_DISABLE 0x1F 88 #define VF610_ADC_HS_COCO0 0x1 89 #define VF610_ADC_CALF 0x2 90 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100) 91 92 #define DEFAULT_SAMPLE_TIME 1000 93 94 /* V at 25°C of 696 mV */ 95 #define VF610_VTEMP25_3V0 950 96 /* V at 25°C of 699 mV */ 97 #define VF610_VTEMP25_3V3 867 98 /* Typical sensor slope coefficient at all temperatures */ 99 #define VF610_TEMP_SLOPE_COEFF 1840 100 101 enum clk_sel { 102 VF610_ADCIOC_BUSCLK_SET, 103 VF610_ADCIOC_ALTCLK_SET, 104 VF610_ADCIOC_ADACK_SET, 105 }; 106 107 enum vol_ref { 108 VF610_ADCIOC_VR_VREF_SET, 109 VF610_ADCIOC_VR_VALT_SET, 110 VF610_ADCIOC_VR_VBG_SET, 111 }; 112 113 enum average_sel { 114 VF610_ADC_SAMPLE_1, 115 VF610_ADC_SAMPLE_4, 116 VF610_ADC_SAMPLE_8, 117 VF610_ADC_SAMPLE_16, 118 VF610_ADC_SAMPLE_32, 119 }; 120 121 enum conversion_mode_sel { 122 VF610_ADC_CONV_NORMAL, 123 VF610_ADC_CONV_HIGH_SPEED, 124 VF610_ADC_CONV_LOW_POWER, 125 }; 126 127 enum lst_adder_sel { 128 VF610_ADCK_CYCLES_3, 129 VF610_ADCK_CYCLES_5, 130 VF610_ADCK_CYCLES_7, 131 VF610_ADCK_CYCLES_9, 132 VF610_ADCK_CYCLES_13, 133 VF610_ADCK_CYCLES_17, 134 VF610_ADCK_CYCLES_21, 135 VF610_ADCK_CYCLES_25, 136 }; 137 138 struct vf610_adc_feature { 139 enum clk_sel clk_sel; 140 enum vol_ref vol_ref; 141 enum conversion_mode_sel conv_mode; 142 143 int clk_div; 144 int sample_rate; 145 int res_mode; 146 u32 lst_adder_index; 147 u32 default_sample_time; 148 149 bool calibration; 150 bool ovwren; 151 }; 152 153 struct vf610_adc { 154 struct device *dev; 155 void __iomem *regs; 156 struct clk *clk; 157 158 /* lock to protect against multiple access to the device */ 159 struct mutex lock; 160 161 u32 vref_uv; 162 u32 value; 163 struct regulator *vref; 164 165 u32 max_adck_rate[3]; 166 struct vf610_adc_feature adc_feature; 167 168 u32 sample_freq_avail[5]; 169 170 struct completion completion; 171 /* Ensure the timestamp is naturally aligned */ 172 struct { 173 u16 chan; 174 aligned_s64 timestamp; 175 } scan; 176 }; 177 178 struct vf610_chip_info { 179 u8 num_channels; 180 }; 181 182 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 }; 183 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 }; 184 185 static inline void vf610_adc_calculate_rates(struct vf610_adc *info) 186 { 187 struct vf610_adc_feature *adc_feature = &info->adc_feature; 188 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk); 189 u32 adck_period, lst_addr_min; 190 int divisor, i; 191 192 adck_rate = info->max_adck_rate[adc_feature->conv_mode]; 193 194 if (adck_rate) { 195 /* calculate clk divider which is within specification */ 196 divisor = ipg_rate / adck_rate; 197 adc_feature->clk_div = 1 << fls(divisor + 1); 198 } else { 199 /* fall-back value using a safe divisor */ 200 adc_feature->clk_div = 8; 201 } 202 203 adck_rate = ipg_rate / adc_feature->clk_div; 204 205 /* 206 * Determine the long sample time adder value to be used based 207 * on the default minimum sample time provided. 208 */ 209 adck_period = NSEC_PER_SEC / adck_rate; 210 lst_addr_min = adc_feature->default_sample_time / adck_period; 211 for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) { 212 if (vf610_lst_adder[i] > lst_addr_min) { 213 adc_feature->lst_adder_index = i; 214 break; 215 } 216 } 217 218 /* 219 * Calculate ADC sample frequencies 220 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock, 221 * which is the same as bus clock. 222 * 223 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder) 224 * SFCAdder: fixed to 6 ADCK cycles 225 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average. 226 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode 227 * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles 228 */ 229 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++) 230 info->sample_freq_avail[i] = 231 adck_rate / (6 + vf610_hw_avgs[i] * 232 (25 + vf610_lst_adder[adc_feature->lst_adder_index])); 233 } 234 235 static inline void vf610_adc_cfg_init(struct vf610_adc *info) 236 { 237 struct vf610_adc_feature *adc_feature = &info->adc_feature; 238 239 /* set default Configuration for ADC controller */ 240 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET; 241 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET; 242 243 adc_feature->calibration = true; 244 adc_feature->ovwren = true; 245 246 adc_feature->res_mode = 12; 247 adc_feature->sample_rate = 1; 248 249 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER; 250 251 vf610_adc_calculate_rates(info); 252 } 253 254 static void vf610_adc_cfg_post_set(struct vf610_adc *info) 255 { 256 struct vf610_adc_feature *adc_feature = &info->adc_feature; 257 int cfg_data = 0; 258 int gc_data = 0; 259 260 switch (adc_feature->clk_sel) { 261 case VF610_ADCIOC_ALTCLK_SET: 262 cfg_data |= VF610_ADC_ALTCLK_SEL; 263 break; 264 case VF610_ADCIOC_ADACK_SET: 265 cfg_data |= VF610_ADC_ADACK_SEL; 266 break; 267 default: 268 break; 269 } 270 271 /* low power set for calibration */ 272 cfg_data |= VF610_ADC_ADLPC_EN; 273 274 /* enable high speed for calibration */ 275 cfg_data |= VF610_ADC_ADHSC_EN; 276 277 /* voltage reference */ 278 switch (adc_feature->vol_ref) { 279 case VF610_ADCIOC_VR_VREF_SET: 280 break; 281 case VF610_ADCIOC_VR_VALT_SET: 282 cfg_data |= VF610_ADC_REFSEL_VALT; 283 break; 284 case VF610_ADCIOC_VR_VBG_SET: 285 cfg_data |= VF610_ADC_REFSEL_VBG; 286 break; 287 default: 288 dev_err(info->dev, "error voltage reference\n"); 289 } 290 291 /* data overwrite enable */ 292 if (adc_feature->ovwren) 293 cfg_data |= VF610_ADC_OVWREN; 294 295 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 296 writel(gc_data, info->regs + VF610_REG_ADC_GC); 297 } 298 299 static void vf610_adc_calibration(struct vf610_adc *info) 300 { 301 int adc_gc, hc_cfg; 302 303 if (!info->adc_feature.calibration) 304 return; 305 306 /* enable calibration interrupt */ 307 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE; 308 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 309 310 adc_gc = readl(info->regs + VF610_REG_ADC_GC); 311 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC); 312 313 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT)) 314 dev_err(info->dev, "Timeout for adc calibration\n"); 315 316 adc_gc = readl(info->regs + VF610_REG_ADC_GS); 317 if (adc_gc & VF610_ADC_CALF) 318 dev_err(info->dev, "ADC calibration failed\n"); 319 320 info->adc_feature.calibration = false; 321 } 322 323 static void vf610_adc_cfg_set(struct vf610_adc *info) 324 { 325 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 326 int cfg_data; 327 328 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 329 330 cfg_data &= ~VF610_ADC_ADLPC_EN; 331 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER) 332 cfg_data |= VF610_ADC_ADLPC_EN; 333 334 cfg_data &= ~VF610_ADC_ADHSC_EN; 335 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED) 336 cfg_data |= VF610_ADC_ADHSC_EN; 337 338 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 339 } 340 341 static void vf610_adc_sample_set(struct vf610_adc *info) 342 { 343 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 344 int cfg_data, gc_data; 345 346 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 347 gc_data = readl(info->regs + VF610_REG_ADC_GC); 348 349 /* resolution mode */ 350 cfg_data &= ~VF610_ADC_MODE_MASK; 351 switch (adc_feature->res_mode) { 352 case 8: 353 cfg_data |= VF610_ADC_MODE_BIT8; 354 break; 355 case 10: 356 cfg_data |= VF610_ADC_MODE_BIT10; 357 break; 358 case 12: 359 cfg_data |= VF610_ADC_MODE_BIT12; 360 break; 361 default: 362 dev_err(info->dev, "error resolution mode\n"); 363 break; 364 } 365 366 /* clock select and clock divider */ 367 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK); 368 switch (adc_feature->clk_div) { 369 case 1: 370 break; 371 case 2: 372 cfg_data |= VF610_ADC_CLK_DIV2; 373 break; 374 case 4: 375 cfg_data |= VF610_ADC_CLK_DIV4; 376 break; 377 case 8: 378 cfg_data |= VF610_ADC_CLK_DIV8; 379 break; 380 case 16: 381 switch (adc_feature->clk_sel) { 382 case VF610_ADCIOC_BUSCLK_SET: 383 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8; 384 break; 385 default: 386 dev_err(info->dev, "error clk divider\n"); 387 break; 388 } 389 break; 390 } 391 392 /* 393 * Set ADLSMP and ADSTS based on the Long Sample Time Adder value 394 * determined. 395 */ 396 switch (adc_feature->lst_adder_index) { 397 case VF610_ADCK_CYCLES_3: 398 break; 399 case VF610_ADCK_CYCLES_5: 400 cfg_data |= VF610_ADC_ADSTS_SHORT; 401 break; 402 case VF610_ADCK_CYCLES_7: 403 cfg_data |= VF610_ADC_ADSTS_NORMAL; 404 break; 405 case VF610_ADCK_CYCLES_9: 406 cfg_data |= VF610_ADC_ADSTS_LONG; 407 break; 408 case VF610_ADCK_CYCLES_13: 409 cfg_data |= VF610_ADC_ADLSMP_LONG; 410 break; 411 case VF610_ADCK_CYCLES_17: 412 cfg_data |= VF610_ADC_ADLSMP_LONG; 413 cfg_data |= VF610_ADC_ADSTS_SHORT; 414 break; 415 case VF610_ADCK_CYCLES_21: 416 cfg_data |= VF610_ADC_ADLSMP_LONG; 417 cfg_data |= VF610_ADC_ADSTS_NORMAL; 418 break; 419 case VF610_ADCK_CYCLES_25: 420 cfg_data |= VF610_ADC_ADLSMP_LONG; 421 cfg_data |= VF610_ADC_ADSTS_NORMAL; 422 break; 423 default: 424 dev_err(info->dev, "error in sample time select\n"); 425 } 426 427 /* update hardware average selection */ 428 cfg_data &= ~VF610_ADC_AVGS_MASK; 429 gc_data &= ~VF610_ADC_AVGEN; 430 switch (adc_feature->sample_rate) { 431 case VF610_ADC_SAMPLE_1: 432 break; 433 case VF610_ADC_SAMPLE_4: 434 gc_data |= VF610_ADC_AVGEN; 435 break; 436 case VF610_ADC_SAMPLE_8: 437 gc_data |= VF610_ADC_AVGEN; 438 cfg_data |= VF610_ADC_AVGS_8; 439 break; 440 case VF610_ADC_SAMPLE_16: 441 gc_data |= VF610_ADC_AVGEN; 442 cfg_data |= VF610_ADC_AVGS_16; 443 break; 444 case VF610_ADC_SAMPLE_32: 445 gc_data |= VF610_ADC_AVGEN; 446 cfg_data |= VF610_ADC_AVGS_32; 447 break; 448 default: 449 dev_err(info->dev, 450 "error hardware sample average select\n"); 451 } 452 453 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 454 writel(gc_data, info->regs + VF610_REG_ADC_GC); 455 } 456 457 static void vf610_adc_hw_init(struct vf610_adc *info) 458 { 459 /* CFG: Feature set */ 460 vf610_adc_cfg_post_set(info); 461 vf610_adc_sample_set(info); 462 463 /* adc calibration */ 464 vf610_adc_calibration(info); 465 466 /* CFG: power and speed set */ 467 vf610_adc_cfg_set(info); 468 } 469 470 static int vf610_set_conversion_mode(struct iio_dev *indio_dev, 471 const struct iio_chan_spec *chan, 472 unsigned int mode) 473 { 474 struct vf610_adc *info = iio_priv(indio_dev); 475 476 mutex_lock(&info->lock); 477 info->adc_feature.conv_mode = mode; 478 vf610_adc_calculate_rates(info); 479 vf610_adc_hw_init(info); 480 mutex_unlock(&info->lock); 481 482 return 0; 483 } 484 485 static int vf610_get_conversion_mode(struct iio_dev *indio_dev, 486 const struct iio_chan_spec *chan) 487 { 488 struct vf610_adc *info = iio_priv(indio_dev); 489 490 return info->adc_feature.conv_mode; 491 } 492 493 static const char * const vf610_conv_modes[] = { "normal", "high-speed", 494 "low-power" }; 495 496 static const struct iio_enum vf610_conversion_mode = { 497 .items = vf610_conv_modes, 498 .num_items = ARRAY_SIZE(vf610_conv_modes), 499 .get = vf610_get_conversion_mode, 500 .set = vf610_set_conversion_mode, 501 }; 502 503 static const struct iio_chan_spec_ext_info vf610_ext_info[] = { 504 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode), 505 { } 506 }; 507 508 #define VF610_ADC_CHAN(_idx, _chan_type) { \ 509 .type = (_chan_type), \ 510 .indexed = 1, \ 511 .channel = (_idx), \ 512 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 513 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 514 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 515 .ext_info = vf610_ext_info, \ 516 .scan_index = (_idx), \ 517 .scan_type = { \ 518 .sign = 'u', \ 519 .realbits = 12, \ 520 .storagebits = 16, \ 521 }, \ 522 } 523 524 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \ 525 .type = (_chan_type), \ 526 .channel = (_idx), \ 527 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 528 .scan_index = (_idx), \ 529 .scan_type = { \ 530 .sign = 'u', \ 531 .realbits = 12, \ 532 .storagebits = 16, \ 533 }, \ 534 } 535 536 static const struct iio_chan_spec vf610_adc_iio_channels[] = { 537 VF610_ADC_CHAN(0, IIO_VOLTAGE), 538 VF610_ADC_CHAN(1, IIO_VOLTAGE), 539 VF610_ADC_CHAN(2, IIO_VOLTAGE), 540 VF610_ADC_CHAN(3, IIO_VOLTAGE), 541 VF610_ADC_CHAN(4, IIO_VOLTAGE), 542 VF610_ADC_CHAN(5, IIO_VOLTAGE), 543 VF610_ADC_CHAN(6, IIO_VOLTAGE), 544 VF610_ADC_CHAN(7, IIO_VOLTAGE), 545 VF610_ADC_CHAN(8, IIO_VOLTAGE), 546 VF610_ADC_CHAN(9, IIO_VOLTAGE), 547 VF610_ADC_CHAN(10, IIO_VOLTAGE), 548 VF610_ADC_CHAN(11, IIO_VOLTAGE), 549 VF610_ADC_CHAN(12, IIO_VOLTAGE), 550 VF610_ADC_CHAN(13, IIO_VOLTAGE), 551 VF610_ADC_CHAN(14, IIO_VOLTAGE), 552 VF610_ADC_CHAN(15, IIO_VOLTAGE), 553 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP), 554 IIO_CHAN_SOFT_TIMESTAMP(32), 555 /* sentinel */ 556 }; 557 558 static int vf610_adc_read_data(struct vf610_adc *info) 559 { 560 int result; 561 562 result = readl(info->regs + VF610_REG_ADC_R0); 563 564 switch (info->adc_feature.res_mode) { 565 case 8: 566 result &= 0xFF; 567 break; 568 case 10: 569 result &= 0x3FF; 570 break; 571 case 12: 572 result &= 0xFFF; 573 break; 574 default: 575 break; 576 } 577 578 return result; 579 } 580 581 static irqreturn_t vf610_adc_isr(int irq, void *dev_id) 582 { 583 struct iio_dev *indio_dev = dev_id; 584 struct vf610_adc *info = iio_priv(indio_dev); 585 int coco; 586 587 coco = readl(info->regs + VF610_REG_ADC_HS); 588 if (coco & VF610_ADC_HS_COCO0) { 589 info->value = vf610_adc_read_data(info); 590 if (iio_buffer_enabled(indio_dev)) { 591 info->scan.chan = info->value; 592 iio_push_to_buffers_with_ts(indio_dev, &info->scan, 593 sizeof(info->scan), 594 iio_get_time_ns(indio_dev)); 595 iio_trigger_notify_done(indio_dev->trig); 596 } else 597 complete(&info->completion); 598 } 599 600 return IRQ_HANDLED; 601 } 602 603 static ssize_t vf610_show_samp_freq_avail(struct device *dev, 604 struct device_attribute *attr, char *buf) 605 { 606 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev)); 607 size_t len = 0; 608 int i; 609 610 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++) 611 len += scnprintf(buf + len, PAGE_SIZE - len, 612 "%u ", info->sample_freq_avail[i]); 613 614 /* replace trailing space by newline */ 615 buf[len - 1] = '\n'; 616 617 return len; 618 } 619 620 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail); 621 622 static struct attribute *vf610_attributes[] = { 623 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 624 NULL 625 }; 626 627 static const struct attribute_group vf610_attribute_group = { 628 .attrs = vf610_attributes, 629 }; 630 631 static int vf610_read_sample(struct vf610_adc *info, 632 struct iio_chan_spec const *chan, int *val) 633 { 634 unsigned int hc_cfg; 635 int ret; 636 637 guard(mutex)(&info->lock); 638 reinit_completion(&info->completion); 639 hc_cfg = VF610_ADC_ADCHC(chan->channel); 640 hc_cfg |= VF610_ADC_AIEN; 641 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 642 ret = wait_for_completion_interruptible_timeout(&info->completion, 643 VF610_ADC_TIMEOUT); 644 if (ret == 0) 645 return -ETIMEDOUT; 646 647 if (ret < 0) 648 return ret; 649 650 switch (chan->type) { 651 case IIO_VOLTAGE: 652 *val = info->value; 653 return 0; 654 case IIO_TEMP: 655 /* 656 * Calculate in degree Celsius times 1000 657 * Using the typical sensor slope of 1.84 mV/°C 658 * and VREFH_ADC at 3.3V, V at 25°C of 699 mV 659 */ 660 *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) * 661 1000000 / VF610_TEMP_SLOPE_COEFF; 662 663 return 0; 664 default: 665 return -EINVAL; 666 } 667 } 668 669 static int vf610_read_raw(struct iio_dev *indio_dev, 670 struct iio_chan_spec const *chan, 671 int *val, 672 int *val2, 673 long mask) 674 { 675 struct vf610_adc *info = iio_priv(indio_dev); 676 long ret; 677 678 switch (mask) { 679 case IIO_CHAN_INFO_RAW: 680 case IIO_CHAN_INFO_PROCESSED: 681 if (!iio_device_claim_direct(indio_dev)) 682 return -EBUSY; 683 ret = vf610_read_sample(info, chan, val); 684 iio_device_release_direct(indio_dev); 685 if (ret < 0) 686 return ret; 687 688 return IIO_VAL_INT; 689 690 case IIO_CHAN_INFO_SCALE: 691 *val = info->vref_uv / 1000; 692 *val2 = info->adc_feature.res_mode; 693 return IIO_VAL_FRACTIONAL_LOG2; 694 695 case IIO_CHAN_INFO_SAMP_FREQ: 696 *val = info->sample_freq_avail[info->adc_feature.sample_rate]; 697 *val2 = 0; 698 return IIO_VAL_INT; 699 700 default: 701 break; 702 } 703 704 return -EINVAL; 705 } 706 707 static int vf610_write_raw(struct iio_dev *indio_dev, 708 struct iio_chan_spec const *chan, 709 int val, 710 int val2, 711 long mask) 712 { 713 struct vf610_adc *info = iio_priv(indio_dev); 714 int i; 715 716 switch (mask) { 717 case IIO_CHAN_INFO_SAMP_FREQ: 718 for (i = 0; 719 i < ARRAY_SIZE(info->sample_freq_avail); 720 i++) 721 if (val == info->sample_freq_avail[i]) { 722 info->adc_feature.sample_rate = i; 723 vf610_adc_sample_set(info); 724 return 0; 725 } 726 break; 727 728 default: 729 break; 730 } 731 732 return -EINVAL; 733 } 734 735 static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev) 736 { 737 struct vf610_adc *info = iio_priv(indio_dev); 738 unsigned int channel; 739 int val; 740 741 val = readl(info->regs + VF610_REG_ADC_GC); 742 val |= VF610_ADC_ADCON; 743 writel(val, info->regs + VF610_REG_ADC_GC); 744 745 channel = find_first_bit(indio_dev->active_scan_mask, 746 iio_get_masklength(indio_dev)); 747 748 val = VF610_ADC_ADCHC(channel); 749 val |= VF610_ADC_AIEN; 750 751 writel(val, info->regs + VF610_REG_ADC_HC0); 752 753 return 0; 754 } 755 756 static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev) 757 { 758 struct vf610_adc *info = iio_priv(indio_dev); 759 unsigned int hc_cfg = 0; 760 int val; 761 762 val = readl(info->regs + VF610_REG_ADC_GC); 763 val &= ~VF610_ADC_ADCON; 764 writel(val, info->regs + VF610_REG_ADC_GC); 765 766 hc_cfg |= VF610_ADC_CONV_DISABLE; 767 hc_cfg &= ~VF610_ADC_AIEN; 768 769 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 770 771 return 0; 772 } 773 774 static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = { 775 .postenable = &vf610_adc_buffer_postenable, 776 .predisable = &vf610_adc_buffer_predisable, 777 .validate_scan_mask = &iio_validate_scan_mask_onehot, 778 }; 779 780 static int vf610_adc_reg_access(struct iio_dev *indio_dev, 781 unsigned reg, unsigned writeval, 782 unsigned *readval) 783 { 784 struct vf610_adc *info = iio_priv(indio_dev); 785 786 if ((readval == NULL) || 787 ((reg % 4) || (reg > VF610_REG_ADC_PCTL))) 788 return -EINVAL; 789 790 *readval = readl(info->regs + reg); 791 792 return 0; 793 } 794 795 static const struct iio_info vf610_adc_iio_info = { 796 .read_raw = &vf610_read_raw, 797 .write_raw = &vf610_write_raw, 798 .debugfs_reg_access = &vf610_adc_reg_access, 799 .attrs = &vf610_attribute_group, 800 }; 801 802 static const struct vf610_chip_info vf610_chip_info = { 803 .num_channels = ARRAY_SIZE(vf610_adc_iio_channels), 804 }; 805 806 static const struct vf610_chip_info imx6sx_chip_info = { 807 .num_channels = 4, 808 }; 809 810 static const struct of_device_id vf610_adc_match[] = { 811 { .compatible = "fsl,imx6sx-adc", .data = &imx6sx_chip_info}, 812 { .compatible = "fsl,vf610-adc", .data = &vf610_chip_info}, 813 { } 814 }; 815 MODULE_DEVICE_TABLE(of, vf610_adc_match); 816 817 static void vf610_adc_action_remove(void *d) 818 { 819 struct vf610_adc *info = d; 820 821 regulator_disable(info->vref); 822 } 823 824 static int vf610_adc_probe(struct platform_device *pdev) 825 { 826 const struct vf610_chip_info *chip_info; 827 struct device *dev = &pdev->dev; 828 struct vf610_adc *info; 829 struct iio_dev *indio_dev; 830 int irq; 831 int ret; 832 833 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc)); 834 if (!indio_dev) 835 return dev_err_probe(&pdev->dev, -ENOMEM, "Failed allocating iio device\n"); 836 837 info = iio_priv(indio_dev); 838 info->dev = &pdev->dev; 839 840 info->regs = devm_platform_ioremap_resource(pdev, 0); 841 if (IS_ERR(info->regs)) 842 return PTR_ERR(info->regs); 843 844 chip_info = device_get_match_data(dev); 845 846 irq = platform_get_irq(pdev, 0); 847 if (irq < 0) 848 return irq; 849 850 ret = devm_request_irq(info->dev, irq, 851 vf610_adc_isr, 0, 852 dev_name(&pdev->dev), indio_dev); 853 if (ret < 0) 854 return dev_err_probe(&pdev->dev, ret, "failed requesting irq, irq = %d\n", irq); 855 856 info->clk = devm_clk_get_enabled(&pdev->dev, "adc"); 857 if (IS_ERR(info->clk)) 858 return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), "failed getting clock\n"); 859 860 info->vref = devm_regulator_get(&pdev->dev, "vref"); 861 if (IS_ERR(info->vref)) 862 return PTR_ERR(info->vref); 863 864 ret = regulator_enable(info->vref); 865 if (ret) 866 return ret; 867 868 ret = devm_add_action_or_reset(&pdev->dev, vf610_adc_action_remove, info); 869 if (ret) 870 return ret; 871 872 info->vref_uv = regulator_get_voltage(info->vref); 873 874 device_property_read_u32_array(dev, "fsl,adck-max-frequency", info->max_adck_rate, 3); 875 876 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME; 877 device_property_read_u32(dev, "min-sample-time", &info->adc_feature.default_sample_time); 878 879 platform_set_drvdata(pdev, indio_dev); 880 881 init_completion(&info->completion); 882 883 indio_dev->name = dev_name(&pdev->dev); 884 indio_dev->info = &vf610_adc_iio_info; 885 indio_dev->modes = INDIO_DIRECT_MODE; 886 indio_dev->channels = vf610_adc_iio_channels; 887 indio_dev->num_channels = chip_info->num_channels; 888 889 vf610_adc_cfg_init(info); 890 vf610_adc_hw_init(info); 891 892 ret = devm_iio_triggered_buffer_setup(&pdev->dev, indio_dev, &iio_pollfunc_store_time, 893 NULL, &iio_triggered_buffer_setup_ops); 894 if (ret < 0) 895 return dev_err_probe(&pdev->dev, ret, "Couldn't initialise the buffer\n"); 896 897 mutex_init(&info->lock); 898 899 ret = devm_iio_device_register(&pdev->dev, indio_dev); 900 if (ret) 901 return dev_err_probe(&pdev->dev, ret, "Couldn't register the device.\n"); 902 903 return 0; 904 } 905 906 static int vf610_adc_suspend(struct device *dev) 907 { 908 struct iio_dev *indio_dev = dev_get_drvdata(dev); 909 struct vf610_adc *info = iio_priv(indio_dev); 910 int hc_cfg; 911 912 /* ADC controller enters to stop mode */ 913 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0); 914 hc_cfg |= VF610_ADC_CONV_DISABLE; 915 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 916 917 clk_disable_unprepare(info->clk); 918 regulator_disable(info->vref); 919 920 return 0; 921 } 922 923 static int vf610_adc_resume(struct device *dev) 924 { 925 struct iio_dev *indio_dev = dev_get_drvdata(dev); 926 struct vf610_adc *info = iio_priv(indio_dev); 927 int ret; 928 929 ret = regulator_enable(info->vref); 930 if (ret) 931 return ret; 932 933 ret = clk_prepare_enable(info->clk); 934 if (ret) 935 goto disable_reg; 936 937 vf610_adc_hw_init(info); 938 939 return 0; 940 941 disable_reg: 942 regulator_disable(info->vref); 943 return ret; 944 } 945 946 static DEFINE_SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, 947 vf610_adc_resume); 948 949 static struct platform_driver vf610_adc_driver = { 950 .probe = vf610_adc_probe, 951 .driver = { 952 .name = "vf610-adc", 953 .of_match_table = vf610_adc_match, 954 .pm = pm_sleep_ptr(&vf610_adc_pm_ops), 955 }, 956 }; 957 958 module_platform_driver(vf610_adc_driver); 959 960 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>"); 961 MODULE_DESCRIPTION("Freescale VF610 ADC driver"); 962 MODULE_LICENSE("GPL v2"); 963