1 /* 2 * Copyright (C) 2015 Prevas A/S 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/device.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/sysfs.h> 13 #include <linux/spi/spi.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/err.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 19 #include <linux/iio/iio.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/trigger_consumer.h> 22 #include <linux/iio/triggered_buffer.h> 23 #include <linux/iio/sysfs.h> 24 25 #define ADS8688_CMD_REG(x) (x << 8) 26 #define ADS8688_CMD_REG_NOOP 0x00 27 #define ADS8688_CMD_REG_RST 0x85 28 #define ADS8688_CMD_REG_MAN_CH(chan) (0xC0 | (4 * chan)) 29 #define ADS8688_CMD_DONT_CARE_BITS 16 30 31 #define ADS8688_PROG_REG(x) (x << 9) 32 #define ADS8688_PROG_REG_RANGE_CH(chan) (0x05 + chan) 33 #define ADS8688_PROG_WR_BIT BIT(8) 34 #define ADS8688_PROG_DONT_CARE_BITS 8 35 36 #define ADS8688_REG_PLUSMINUS25VREF 0 37 #define ADS8688_REG_PLUSMINUS125VREF 1 38 #define ADS8688_REG_PLUSMINUS0625VREF 2 39 #define ADS8688_REG_PLUS25VREF 5 40 #define ADS8688_REG_PLUS125VREF 6 41 42 #define ADS8688_VREF_MV 4096 43 #define ADS8688_REALBITS 16 44 45 /* 46 * enum ads8688_range - ADS8688 reference voltage range 47 * @ADS8688_PLUSMINUS25VREF: Device is configured for input range ±2.5 * VREF 48 * @ADS8688_PLUSMINUS125VREF: Device is configured for input range ±1.25 * VREF 49 * @ADS8688_PLUSMINUS0625VREF: Device is configured for input range ±0.625 * VREF 50 * @ADS8688_PLUS25VREF: Device is configured for input range 0 - 2.5 * VREF 51 * @ADS8688_PLUS125VREF: Device is configured for input range 0 - 1.25 * VREF 52 */ 53 enum ads8688_range { 54 ADS8688_PLUSMINUS25VREF, 55 ADS8688_PLUSMINUS125VREF, 56 ADS8688_PLUSMINUS0625VREF, 57 ADS8688_PLUS25VREF, 58 ADS8688_PLUS125VREF, 59 }; 60 61 struct ads8688_chip_info { 62 const struct iio_chan_spec *channels; 63 unsigned int num_channels; 64 }; 65 66 struct ads8688_state { 67 struct mutex lock; 68 const struct ads8688_chip_info *chip_info; 69 struct spi_device *spi; 70 struct regulator *reg; 71 unsigned int vref_mv; 72 enum ads8688_range range[8]; 73 union { 74 __be32 d32; 75 u8 d8[4]; 76 } data[2] ____cacheline_aligned; 77 }; 78 79 enum ads8688_id { 80 ID_ADS8684, 81 ID_ADS8688, 82 }; 83 84 struct ads8688_ranges { 85 enum ads8688_range range; 86 unsigned int scale; 87 int offset; 88 u8 reg; 89 }; 90 91 static const struct ads8688_ranges ads8688_range_def[5] = { 92 { 93 .range = ADS8688_PLUSMINUS25VREF, 94 .scale = 76295, 95 .offset = -(1 << (ADS8688_REALBITS - 1)), 96 .reg = ADS8688_REG_PLUSMINUS25VREF, 97 }, { 98 .range = ADS8688_PLUSMINUS125VREF, 99 .scale = 38148, 100 .offset = -(1 << (ADS8688_REALBITS - 1)), 101 .reg = ADS8688_REG_PLUSMINUS125VREF, 102 }, { 103 .range = ADS8688_PLUSMINUS0625VREF, 104 .scale = 19074, 105 .offset = -(1 << (ADS8688_REALBITS - 1)), 106 .reg = ADS8688_REG_PLUSMINUS0625VREF, 107 }, { 108 .range = ADS8688_PLUS25VREF, 109 .scale = 38148, 110 .offset = 0, 111 .reg = ADS8688_REG_PLUS25VREF, 112 }, { 113 .range = ADS8688_PLUS125VREF, 114 .scale = 19074, 115 .offset = 0, 116 .reg = ADS8688_REG_PLUS125VREF, 117 } 118 }; 119 120 static ssize_t ads8688_show_scales(struct device *dev, 121 struct device_attribute *attr, char *buf) 122 { 123 struct ads8688_state *st = iio_priv(dev_to_iio_dev(dev)); 124 125 return sprintf(buf, "0.%09u 0.%09u 0.%09u\n", 126 ads8688_range_def[0].scale * st->vref_mv, 127 ads8688_range_def[1].scale * st->vref_mv, 128 ads8688_range_def[2].scale * st->vref_mv); 129 } 130 131 static ssize_t ads8688_show_offsets(struct device *dev, 132 struct device_attribute *attr, char *buf) 133 { 134 return sprintf(buf, "%d %d\n", ads8688_range_def[0].offset, 135 ads8688_range_def[3].offset); 136 } 137 138 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, 139 ads8688_show_scales, NULL, 0); 140 static IIO_DEVICE_ATTR(in_voltage_offset_available, S_IRUGO, 141 ads8688_show_offsets, NULL, 0); 142 143 static struct attribute *ads8688_attributes[] = { 144 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, 145 &iio_dev_attr_in_voltage_offset_available.dev_attr.attr, 146 NULL, 147 }; 148 149 static const struct attribute_group ads8688_attribute_group = { 150 .attrs = ads8688_attributes, 151 }; 152 153 #define ADS8688_CHAN(index) \ 154 { \ 155 .type = IIO_VOLTAGE, \ 156 .indexed = 1, \ 157 .channel = index, \ 158 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 159 | BIT(IIO_CHAN_INFO_SCALE) \ 160 | BIT(IIO_CHAN_INFO_OFFSET), \ 161 .scan_index = index, \ 162 .scan_type = { \ 163 .sign = 'u', \ 164 .realbits = 16, \ 165 .storagebits = 16, \ 166 .endianness = IIO_BE, \ 167 }, \ 168 } 169 170 static const struct iio_chan_spec ads8684_channels[] = { 171 ADS8688_CHAN(0), 172 ADS8688_CHAN(1), 173 ADS8688_CHAN(2), 174 ADS8688_CHAN(3), 175 }; 176 177 static const struct iio_chan_spec ads8688_channels[] = { 178 ADS8688_CHAN(0), 179 ADS8688_CHAN(1), 180 ADS8688_CHAN(2), 181 ADS8688_CHAN(3), 182 ADS8688_CHAN(4), 183 ADS8688_CHAN(5), 184 ADS8688_CHAN(6), 185 ADS8688_CHAN(7), 186 }; 187 188 static int ads8688_prog_write(struct iio_dev *indio_dev, unsigned int addr, 189 unsigned int val) 190 { 191 struct ads8688_state *st = iio_priv(indio_dev); 192 u32 tmp; 193 194 tmp = ADS8688_PROG_REG(addr) | ADS8688_PROG_WR_BIT | val; 195 tmp <<= ADS8688_PROG_DONT_CARE_BITS; 196 st->data[0].d32 = cpu_to_be32(tmp); 197 198 return spi_write(st->spi, &st->data[0].d8[1], 3); 199 } 200 201 static int ads8688_reset(struct iio_dev *indio_dev) 202 { 203 struct ads8688_state *st = iio_priv(indio_dev); 204 u32 tmp; 205 206 tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_RST); 207 tmp <<= ADS8688_CMD_DONT_CARE_BITS; 208 st->data[0].d32 = cpu_to_be32(tmp); 209 210 return spi_write(st->spi, &st->data[0].d8[0], 4); 211 } 212 213 static int ads8688_read(struct iio_dev *indio_dev, unsigned int chan) 214 { 215 struct ads8688_state *st = iio_priv(indio_dev); 216 int ret; 217 u32 tmp; 218 struct spi_transfer t[] = { 219 { 220 .tx_buf = &st->data[0].d8[0], 221 .len = 4, 222 .cs_change = 1, 223 }, { 224 .tx_buf = &st->data[1].d8[0], 225 .rx_buf = &st->data[1].d8[0], 226 .len = 4, 227 }, 228 }; 229 230 tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_MAN_CH(chan)); 231 tmp <<= ADS8688_CMD_DONT_CARE_BITS; 232 st->data[0].d32 = cpu_to_be32(tmp); 233 234 tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_NOOP); 235 tmp <<= ADS8688_CMD_DONT_CARE_BITS; 236 st->data[1].d32 = cpu_to_be32(tmp); 237 238 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); 239 if (ret < 0) 240 return ret; 241 242 return be32_to_cpu(st->data[1].d32) & 0xffff; 243 } 244 245 static int ads8688_read_raw(struct iio_dev *indio_dev, 246 struct iio_chan_spec const *chan, 247 int *val, int *val2, long m) 248 { 249 int ret, offset; 250 unsigned long scale_mv; 251 252 struct ads8688_state *st = iio_priv(indio_dev); 253 254 mutex_lock(&st->lock); 255 switch (m) { 256 case IIO_CHAN_INFO_RAW: 257 ret = ads8688_read(indio_dev, chan->channel); 258 mutex_unlock(&st->lock); 259 if (ret < 0) 260 return ret; 261 *val = ret; 262 return IIO_VAL_INT; 263 case IIO_CHAN_INFO_SCALE: 264 scale_mv = st->vref_mv; 265 scale_mv *= ads8688_range_def[st->range[chan->channel]].scale; 266 *val = 0; 267 *val2 = scale_mv; 268 mutex_unlock(&st->lock); 269 return IIO_VAL_INT_PLUS_NANO; 270 case IIO_CHAN_INFO_OFFSET: 271 offset = ads8688_range_def[st->range[chan->channel]].offset; 272 *val = offset; 273 mutex_unlock(&st->lock); 274 return IIO_VAL_INT; 275 } 276 mutex_unlock(&st->lock); 277 278 return -EINVAL; 279 } 280 281 static int ads8688_write_reg_range(struct iio_dev *indio_dev, 282 struct iio_chan_spec const *chan, 283 enum ads8688_range range) 284 { 285 unsigned int tmp; 286 int ret; 287 288 tmp = ADS8688_PROG_REG_RANGE_CH(chan->channel); 289 ret = ads8688_prog_write(indio_dev, tmp, range); 290 291 return ret; 292 } 293 294 static int ads8688_write_raw(struct iio_dev *indio_dev, 295 struct iio_chan_spec const *chan, 296 int val, int val2, long mask) 297 { 298 struct ads8688_state *st = iio_priv(indio_dev); 299 unsigned int scale = 0; 300 int ret = -EINVAL, i, offset = 0; 301 302 mutex_lock(&st->lock); 303 switch (mask) { 304 case IIO_CHAN_INFO_SCALE: 305 /* If the offset is 0 the ±2.5 * VREF mode is not available */ 306 offset = ads8688_range_def[st->range[chan->channel]].offset; 307 if (offset == 0 && val2 == ads8688_range_def[0].scale * st->vref_mv) { 308 mutex_unlock(&st->lock); 309 return -EINVAL; 310 } 311 312 /* Lookup new mode */ 313 for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++) 314 if (val2 == ads8688_range_def[i].scale * st->vref_mv && 315 offset == ads8688_range_def[i].offset) { 316 ret = ads8688_write_reg_range(indio_dev, chan, 317 ads8688_range_def[i].reg); 318 break; 319 } 320 break; 321 case IIO_CHAN_INFO_OFFSET: 322 /* 323 * There are only two available offsets: 324 * 0 and -(1 << (ADS8688_REALBITS - 1)) 325 */ 326 if (!(ads8688_range_def[0].offset == val || 327 ads8688_range_def[3].offset == val)) { 328 mutex_unlock(&st->lock); 329 return -EINVAL; 330 } 331 332 /* 333 * If the device are in ±2.5 * VREF mode, it's not allowed to 334 * switch to a mode where the offset is 0 335 */ 336 if (val == 0 && 337 st->range[chan->channel] == ADS8688_PLUSMINUS25VREF) { 338 mutex_unlock(&st->lock); 339 return -EINVAL; 340 } 341 342 scale = ads8688_range_def[st->range[chan->channel]].scale; 343 344 /* Lookup new mode */ 345 for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++) 346 if (val == ads8688_range_def[i].offset && 347 scale == ads8688_range_def[i].scale) { 348 ret = ads8688_write_reg_range(indio_dev, chan, 349 ads8688_range_def[i].reg); 350 break; 351 } 352 break; 353 } 354 355 if (!ret) 356 st->range[chan->channel] = ads8688_range_def[i].range; 357 358 mutex_unlock(&st->lock); 359 360 return ret; 361 } 362 363 static int ads8688_write_raw_get_fmt(struct iio_dev *indio_dev, 364 struct iio_chan_spec const *chan, 365 long mask) 366 { 367 switch (mask) { 368 case IIO_CHAN_INFO_SCALE: 369 return IIO_VAL_INT_PLUS_NANO; 370 case IIO_CHAN_INFO_OFFSET: 371 return IIO_VAL_INT; 372 } 373 374 return -EINVAL; 375 } 376 377 static const struct iio_info ads8688_info = { 378 .read_raw = &ads8688_read_raw, 379 .write_raw = &ads8688_write_raw, 380 .write_raw_get_fmt = &ads8688_write_raw_get_fmt, 381 .attrs = &ads8688_attribute_group, 382 }; 383 384 static irqreturn_t ads8688_trigger_handler(int irq, void *p) 385 { 386 struct iio_poll_func *pf = p; 387 struct iio_dev *indio_dev = pf->indio_dev; 388 u16 buffer[8]; 389 int i, j = 0; 390 391 for (i = 0; i < indio_dev->masklength; i++) { 392 if (!test_bit(i, indio_dev->active_scan_mask)) 393 continue; 394 buffer[j] = ads8688_read(indio_dev, i); 395 j++; 396 } 397 398 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 399 pf->timestamp); 400 401 iio_trigger_notify_done(indio_dev->trig); 402 403 return IRQ_HANDLED; 404 } 405 406 static const struct ads8688_chip_info ads8688_chip_info_tbl[] = { 407 [ID_ADS8684] = { 408 .channels = ads8684_channels, 409 .num_channels = ARRAY_SIZE(ads8684_channels), 410 }, 411 [ID_ADS8688] = { 412 .channels = ads8688_channels, 413 .num_channels = ARRAY_SIZE(ads8688_channels), 414 }, 415 }; 416 417 static int ads8688_probe(struct spi_device *spi) 418 { 419 struct ads8688_state *st; 420 struct iio_dev *indio_dev; 421 int ret; 422 423 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 424 if (indio_dev == NULL) 425 return -ENOMEM; 426 427 st = iio_priv(indio_dev); 428 429 st->reg = devm_regulator_get_optional(&spi->dev, "vref"); 430 if (!IS_ERR(st->reg)) { 431 ret = regulator_enable(st->reg); 432 if (ret) 433 return ret; 434 435 ret = regulator_get_voltage(st->reg); 436 if (ret < 0) 437 goto err_regulator_disable; 438 439 st->vref_mv = ret / 1000; 440 } else { 441 /* Use internal reference */ 442 st->vref_mv = ADS8688_VREF_MV; 443 } 444 445 st->chip_info = &ads8688_chip_info_tbl[spi_get_device_id(spi)->driver_data]; 446 447 spi->mode = SPI_MODE_1; 448 449 spi_set_drvdata(spi, indio_dev); 450 451 st->spi = spi; 452 453 indio_dev->name = spi_get_device_id(spi)->name; 454 indio_dev->dev.parent = &spi->dev; 455 indio_dev->dev.of_node = spi->dev.of_node; 456 indio_dev->modes = INDIO_DIRECT_MODE; 457 indio_dev->channels = st->chip_info->channels; 458 indio_dev->num_channels = st->chip_info->num_channels; 459 indio_dev->info = &ads8688_info; 460 461 ads8688_reset(indio_dev); 462 463 mutex_init(&st->lock); 464 465 ret = iio_triggered_buffer_setup(indio_dev, NULL, ads8688_trigger_handler, NULL); 466 if (ret < 0) { 467 dev_err(&spi->dev, "iio triggered buffer setup failed\n"); 468 goto err_regulator_disable; 469 } 470 471 ret = iio_device_register(indio_dev); 472 if (ret) 473 goto err_buffer_cleanup; 474 475 return 0; 476 477 err_buffer_cleanup: 478 iio_triggered_buffer_cleanup(indio_dev); 479 480 err_regulator_disable: 481 if (!IS_ERR(st->reg)) 482 regulator_disable(st->reg); 483 484 return ret; 485 } 486 487 static int ads8688_remove(struct spi_device *spi) 488 { 489 struct iio_dev *indio_dev = spi_get_drvdata(spi); 490 struct ads8688_state *st = iio_priv(indio_dev); 491 492 iio_device_unregister(indio_dev); 493 iio_triggered_buffer_cleanup(indio_dev); 494 495 if (!IS_ERR(st->reg)) 496 regulator_disable(st->reg); 497 498 return 0; 499 } 500 501 static const struct spi_device_id ads8688_id[] = { 502 {"ads8684", ID_ADS8684}, 503 {"ads8688", ID_ADS8688}, 504 {} 505 }; 506 MODULE_DEVICE_TABLE(spi, ads8688_id); 507 508 static const struct of_device_id ads8688_of_match[] = { 509 { .compatible = "ti,ads8684" }, 510 { .compatible = "ti,ads8688" }, 511 { } 512 }; 513 MODULE_DEVICE_TABLE(of, ads8688_of_match); 514 515 static struct spi_driver ads8688_driver = { 516 .driver = { 517 .name = "ads8688", 518 }, 519 .probe = ads8688_probe, 520 .remove = ads8688_remove, 521 .id_table = ads8688_id, 522 }; 523 module_spi_driver(ads8688_driver); 524 525 MODULE_AUTHOR("Sean Nyekjaer <sean.nyekjaer@prevas.dk>"); 526 MODULE_DESCRIPTION("Texas Instruments ADS8688 driver"); 527 MODULE_LICENSE("GPL v2"); 528