1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Texas Instruments ADS1018 ADC driver 4 * 5 * Copyright (C) 2025 Kurt Borja <kuurtb@gmail.com> 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bitmap.h> 11 #include <linux/dev_printk.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/interrupt.h> 14 #include <linux/math.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/spi/spi.h> 18 #include <linux/types.h> 19 #include <linux/units.h> 20 21 #include <asm/byteorder.h> 22 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/iio.h> 25 #include <linux/iio/trigger.h> 26 #include <linux/iio/trigger_consumer.h> 27 #include <linux/iio/triggered_buffer.h> 28 29 #define ADS1018_CFG_OS_TRIG BIT(15) 30 #define ADS1018_CFG_TS_MODE_EN BIT(4) 31 #define ADS1018_CFG_PULL_UP BIT(3) 32 #define ADS1018_CFG_NOP BIT(1) 33 #define ADS1018_CFG_VALID (ADS1018_CFG_PULL_UP | ADS1018_CFG_NOP) 34 35 #define ADS1018_CFG_MUX_MASK GENMASK(14, 12) 36 37 #define ADS1018_CFG_PGA_MASK GENMASK(11, 9) 38 #define ADS1018_PGA_DEFAULT 2 39 40 #define ADS1018_CFG_MODE_MASK BIT(8) 41 #define ADS1018_MODE_CONTINUOUS 0 42 #define ADS1018_MODE_ONESHOT 1 43 44 #define ADS1018_CFG_DRATE_MASK GENMASK(7, 5) 45 #define ADS1018_DRATE_DEFAULT 4 46 47 #define ADS1018_NUM_PGA_MODES 6 48 #define ADS1018_CHANNELS_MAX 10 49 50 struct ads1018_chan_data { 51 u8 pga_mode; 52 u8 data_rate_mode; 53 }; 54 55 struct ads1018_chip_info { 56 const char *name; 57 const struct iio_chan_spec *channels; 58 unsigned long num_channels; 59 60 /* IIO_VAL_INT */ 61 const u32 *data_rate_mode_to_hz; 62 unsigned long num_data_rate_mode_to_hz; 63 64 /* 65 * Let `res` be the chip's resolution and `fsr` (millivolts) be the 66 * full-scale range corresponding to the PGA mode given by the array 67 * index. Then, the gain is calculated using the following formula: 68 * 69 * gain = |fsr| / 2^(res - 1) 70 * 71 * This value then has to be represented in IIO_VAL_INT_PLUS_NANO 72 * format. For example if: 73 * 74 * gain = 6144 / 2^(16 - 1) = 0.1875 75 * 76 * ...then the formatted value is: 77 * 78 * { 0, 187500000 } 79 */ 80 const u32 pga_mode_to_gain[ADS1018_NUM_PGA_MODES][2]; 81 82 /* IIO_VAL_INT_PLUS_MICRO */ 83 const u32 temp_scale[2]; 84 }; 85 86 struct ads1018 { 87 struct spi_device *spi; 88 struct iio_trigger *indio_trig; 89 90 struct gpio_desc *drdy_gpiod; 91 int drdy_irq; 92 93 struct ads1018_chan_data chan_data[ADS1018_CHANNELS_MAX]; 94 const struct ads1018_chip_info *chip_info; 95 96 struct spi_message msg_read; 97 struct spi_transfer xfer; 98 __be16 tx_buf[2] __aligned(IIO_DMA_MINALIGN); 99 __be16 rx_buf[2]; 100 }; 101 102 #define ADS1018_VOLT_DIFF_CHAN(_index, _chan, _chan2, _realbits) { \ 103 .type = IIO_VOLTAGE, \ 104 .channel = _chan, \ 105 .channel2 = _chan2, \ 106 .scan_index = _index, \ 107 .scan_type = { \ 108 .sign = 's', \ 109 .realbits = _realbits, \ 110 .storagebits = 16, \ 111 .shift = 16 - _realbits, \ 112 .endianness = IIO_BE, \ 113 }, \ 114 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 115 BIT(IIO_CHAN_INFO_SCALE) | \ 116 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 117 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 118 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 119 .indexed = true, \ 120 .differential = true, \ 121 } 122 123 #define ADS1018_VOLT_CHAN(_index, _chan, _realbits) { \ 124 .type = IIO_VOLTAGE, \ 125 .channel = _chan, \ 126 .scan_index = _index, \ 127 .scan_type = { \ 128 .sign = 's', \ 129 .realbits = _realbits, \ 130 .storagebits = 16, \ 131 .shift = 16 - _realbits, \ 132 .endianness = IIO_BE, \ 133 }, \ 134 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 135 BIT(IIO_CHAN_INFO_SCALE) | \ 136 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 137 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 138 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 139 .indexed = true, \ 140 } 141 142 #define ADS1018_TEMP_CHAN(_index, _realbits) { \ 143 .type = IIO_TEMP, \ 144 .scan_index = _index, \ 145 .scan_type = { \ 146 .sign = 's', \ 147 .realbits = _realbits, \ 148 .storagebits = 16, \ 149 .shift = 16 - _realbits, \ 150 .endianness = IIO_BE, \ 151 }, \ 152 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 153 BIT(IIO_CHAN_INFO_SCALE) | \ 154 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 155 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 156 } 157 158 static const struct iio_chan_spec ads1118_iio_channels[] = { 159 ADS1018_VOLT_DIFF_CHAN(0, 0, 1, 16), 160 ADS1018_VOLT_DIFF_CHAN(1, 0, 3, 16), 161 ADS1018_VOLT_DIFF_CHAN(2, 1, 3, 16), 162 ADS1018_VOLT_DIFF_CHAN(3, 2, 3, 16), 163 ADS1018_VOLT_CHAN(4, 0, 16), 164 ADS1018_VOLT_CHAN(5, 1, 16), 165 ADS1018_VOLT_CHAN(6, 2, 16), 166 ADS1018_VOLT_CHAN(7, 3, 16), 167 ADS1018_TEMP_CHAN(8, 14), 168 IIO_CHAN_SOFT_TIMESTAMP(9), 169 }; 170 171 static const struct iio_chan_spec ads1018_iio_channels[] = { 172 ADS1018_VOLT_DIFF_CHAN(0, 0, 1, 12), 173 ADS1018_VOLT_DIFF_CHAN(1, 0, 3, 12), 174 ADS1018_VOLT_DIFF_CHAN(2, 1, 3, 12), 175 ADS1018_VOLT_DIFF_CHAN(3, 2, 3, 12), 176 ADS1018_VOLT_CHAN(4, 0, 12), 177 ADS1018_VOLT_CHAN(5, 1, 12), 178 ADS1018_VOLT_CHAN(6, 2, 12), 179 ADS1018_VOLT_CHAN(7, 3, 12), 180 ADS1018_TEMP_CHAN(8, 12), 181 IIO_CHAN_SOFT_TIMESTAMP(9), 182 }; 183 184 /** 185 * ads1018_calc_delay - Calculates a suitable delay for a single-shot reading 186 * @hz: Sampling frequency 187 * 188 * Calculates an appropriate delay for a single shot reading given a sampling 189 * frequency. 190 * 191 * Return: Delay in microseconds (Always greater than 0). 192 */ 193 static u32 ads1018_calc_delay(unsigned int hz) 194 { 195 /* 196 * Calculate the worst-case sampling rate by subtracting 10% error 197 * specified in the datasheet... 198 */ 199 hz -= DIV_ROUND_UP(hz, 10); 200 201 /* ...Then calculate time per sample in microseconds. */ 202 return DIV_ROUND_UP(HZ_PER_MHZ, hz); 203 } 204 205 /** 206 * ads1018_spi_read_exclusive - Reads a conversion value from the device 207 * @ads1018: Device data 208 * @cnv: ADC Conversion value (optional) 209 * @hold_cs: Keep CS line asserted after the SPI transfer 210 * 211 * Reads the most recent ADC conversion value, without updating the 212 * device's configuration. 213 * 214 * Context: Expects SPI bus *exclusive* use. 215 * 216 * Return: 0 on success, negative errno on error. 217 */ 218 static int ads1018_spi_read_exclusive(struct ads1018 *ads1018, __be16 *cnv, 219 bool hold_cs) 220 { 221 int ret; 222 223 ads1018->xfer.cs_change = hold_cs; 224 225 ret = spi_sync_locked(ads1018->spi, &ads1018->msg_read); 226 if (ret) 227 return ret; 228 229 if (cnv) 230 *cnv = ads1018->rx_buf[0]; 231 232 return 0; 233 } 234 235 /** 236 * ads1018_single_shot - Performs a one-shot reading sequence 237 * @ads1018: Device data 238 * @chan: Channel specification 239 * @cnv: Conversion value 240 * 241 * Writes a new configuration, waits an appropriate delay, then reads the most 242 * recent conversion. 243 * 244 * Context: Expects iio_device_claim_direct() is held. 245 * 246 * Return: 0 on success, negative errno on error. 247 */ 248 static int ads1018_single_shot(struct ads1018 *ads1018, 249 struct iio_chan_spec const *chan, u16 *cnv) 250 { 251 u8 max_drate_mode = ads1018->chip_info->num_data_rate_mode_to_hz - 1; 252 u8 drate = ads1018->chip_info->data_rate_mode_to_hz[max_drate_mode]; 253 u8 pga_mode = ads1018->chan_data[chan->scan_index].pga_mode; 254 struct spi_transfer xfer[2] = { 255 { 256 .tx_buf = ads1018->tx_buf, 257 .len = sizeof(ads1018->tx_buf[0]), 258 .delay = { 259 .value = ads1018_calc_delay(drate), 260 .unit = SPI_DELAY_UNIT_USECS, 261 }, 262 .cs_change = 1, /* 16-bit mode requires CS de-assert */ 263 }, 264 { 265 .rx_buf = ads1018->rx_buf, 266 .len = sizeof(ads1018->rx_buf[0]), 267 }, 268 }; 269 u16 cfg; 270 int ret; 271 272 cfg = ADS1018_CFG_VALID | ADS1018_CFG_OS_TRIG; 273 cfg |= FIELD_PREP(ADS1018_CFG_MUX_MASK, chan->scan_index); 274 cfg |= FIELD_PREP(ADS1018_CFG_PGA_MASK, pga_mode); 275 cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_ONESHOT); 276 cfg |= FIELD_PREP(ADS1018_CFG_DRATE_MASK, max_drate_mode); 277 278 if (chan->type == IIO_TEMP) 279 cfg |= ADS1018_CFG_TS_MODE_EN; 280 281 ads1018->tx_buf[0] = cpu_to_be16(cfg); 282 ret = spi_sync_transfer(ads1018->spi, xfer, ARRAY_SIZE(xfer)); 283 if (ret) 284 return ret; 285 286 *cnv = be16_to_cpu(ads1018->rx_buf[0]); 287 288 return 0; 289 } 290 291 static int 292 ads1018_read_raw_direct_mode(struct iio_dev *indio_dev, 293 struct iio_chan_spec const *chan, int *val, int *val2, 294 long mask) 295 { 296 struct ads1018 *ads1018 = iio_priv(indio_dev); 297 const struct ads1018_chip_info *chip_info = ads1018->chip_info; 298 u8 addr = chan->scan_index; 299 u8 pga_mode, drate_mode; 300 u16 cnv; 301 int ret; 302 303 switch (mask) { 304 case IIO_CHAN_INFO_RAW: 305 ret = ads1018_single_shot(ads1018, chan, &cnv); 306 if (ret) 307 return ret; 308 309 cnv >>= chan->scan_type.shift; 310 *val = sign_extend32(cnv, chan->scan_type.realbits - 1); 311 312 return IIO_VAL_INT; 313 314 case IIO_CHAN_INFO_SCALE: 315 switch (chan->type) { 316 case IIO_VOLTAGE: 317 pga_mode = ads1018->chan_data[addr].pga_mode; 318 *val = chip_info->pga_mode_to_gain[pga_mode][0]; 319 *val2 = chip_info->pga_mode_to_gain[pga_mode][1]; 320 return IIO_VAL_INT_PLUS_NANO; 321 322 case IIO_TEMP: 323 *val = chip_info->temp_scale[0]; 324 *val2 = chip_info->temp_scale[1]; 325 return IIO_VAL_INT_PLUS_MICRO; 326 327 default: 328 return -EOPNOTSUPP; 329 } 330 331 case IIO_CHAN_INFO_SAMP_FREQ: 332 drate_mode = ads1018->chan_data[addr].data_rate_mode; 333 *val = chip_info->data_rate_mode_to_hz[drate_mode]; 334 return IIO_VAL_INT; 335 336 default: 337 return -EOPNOTSUPP; 338 } 339 } 340 341 static int 342 ads1018_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, 343 int *val, int *val2, long mask) 344 { 345 int ret; 346 347 if (!iio_device_claim_direct(indio_dev)) 348 return -EBUSY; 349 ret = ads1018_read_raw_direct_mode(indio_dev, chan, val, val2, mask); 350 iio_device_release_direct(indio_dev); 351 352 return ret; 353 } 354 355 static int 356 ads1018_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, 357 const int **vals, int *type, int *length, long mask) 358 { 359 struct ads1018 *ads1018 = iio_priv(indio_dev); 360 361 switch (mask) { 362 case IIO_CHAN_INFO_SCALE: 363 *type = IIO_VAL_INT_PLUS_NANO; 364 *vals = (const int *)ads1018->chip_info->pga_mode_to_gain; 365 *length = ADS1018_NUM_PGA_MODES * 2; 366 return IIO_AVAIL_LIST; 367 368 case IIO_CHAN_INFO_SAMP_FREQ: 369 *type = IIO_VAL_INT; 370 *vals = ads1018->chip_info->data_rate_mode_to_hz; 371 *length = ads1018->chip_info->num_data_rate_mode_to_hz; 372 return IIO_AVAIL_LIST; 373 374 default: 375 return -EOPNOTSUPP; 376 } 377 } 378 379 static int 380 ads1018_write_raw_direct_mode(struct iio_dev *indio_dev, 381 struct iio_chan_spec const *chan, int val, int val2, 382 long mask) 383 { 384 struct ads1018 *ads1018 = iio_priv(indio_dev); 385 const struct ads1018_chip_info *info = ads1018->chip_info; 386 unsigned int i; 387 388 switch (mask) { 389 case IIO_CHAN_INFO_SCALE: 390 for (i = 0; i < ADS1018_NUM_PGA_MODES; i++) { 391 if (val == info->pga_mode_to_gain[i][0] && 392 val2 == info->pga_mode_to_gain[i][1]) 393 break; 394 } 395 if (i == ADS1018_NUM_PGA_MODES) 396 return -EINVAL; 397 398 ads1018->chan_data[chan->scan_index].pga_mode = i; 399 return 0; 400 401 case IIO_CHAN_INFO_SAMP_FREQ: 402 for (i = 0; i < info->num_data_rate_mode_to_hz; i++) { 403 if (val == info->data_rate_mode_to_hz[i]) 404 break; 405 } 406 if (i == info->num_data_rate_mode_to_hz) 407 return -EINVAL; 408 409 ads1018->chan_data[chan->scan_index].data_rate_mode = i; 410 return 0; 411 412 default: 413 return -EOPNOTSUPP; 414 } 415 } 416 417 static int 418 ads1018_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, 419 int val, int val2, long mask) 420 { 421 int ret; 422 423 if (!iio_device_claim_direct(indio_dev)) 424 return -EBUSY; 425 ret = ads1018_write_raw_direct_mode(indio_dev, chan, val, val2, mask); 426 iio_device_release_direct(indio_dev); 427 428 return ret; 429 } 430 431 static int 432 ads1018_write_raw_get_fmt(struct iio_dev *indio_dev, 433 struct iio_chan_spec const *chan, long mask) 434 { 435 switch (mask) { 436 case IIO_CHAN_INFO_SCALE: 437 return IIO_VAL_INT_PLUS_NANO; 438 default: 439 return IIO_VAL_INT_PLUS_MICRO; 440 } 441 } 442 443 static const struct iio_info ads1018_iio_info = { 444 .read_raw = ads1018_read_raw, 445 .read_avail = ads1018_read_avail, 446 .write_raw = ads1018_write_raw, 447 .write_raw_get_fmt = ads1018_write_raw_get_fmt, 448 }; 449 450 static void ads1018_set_trigger_enable(struct ads1018 *ads1018) 451 { 452 spi_bus_lock(ads1018->spi->controller); 453 ads1018_spi_read_exclusive(ads1018, NULL, true); 454 enable_irq(ads1018->drdy_irq); 455 } 456 457 static void ads1018_set_trigger_disable(struct ads1018 *ads1018) 458 { 459 disable_irq(ads1018->drdy_irq); 460 ads1018_spi_read_exclusive(ads1018, NULL, false); 461 spi_bus_unlock(ads1018->spi->controller); 462 } 463 464 static int ads1018_set_trigger_state(struct iio_trigger *trig, bool state) 465 { 466 struct ads1018 *ads1018 = iio_trigger_get_drvdata(trig); 467 468 /* 469 * We need to lock the SPI bus and tie CS low (hold_cs) to catch 470 * data-ready interrupts, otherwise the MISO line enters a Hi-Z state. 471 */ 472 473 if (state) 474 ads1018_set_trigger_enable(ads1018); 475 else 476 ads1018_set_trigger_disable(ads1018); 477 478 return 0; 479 } 480 481 static const struct iio_trigger_ops ads1018_trigger_ops = { 482 .set_trigger_state = ads1018_set_trigger_state, 483 .validate_device = iio_trigger_validate_own_device, 484 }; 485 486 static int ads1018_buffer_preenable(struct iio_dev *indio_dev) 487 { 488 struct ads1018 *ads1018 = iio_priv(indio_dev); 489 const struct ads1018_chip_info *chip_info = ads1018->chip_info; 490 unsigned int pga, drate, addr; 491 u16 cfg; 492 493 addr = find_first_bit(indio_dev->active_scan_mask, 494 iio_get_masklength(indio_dev)); 495 pga = ads1018->chan_data[addr].pga_mode; 496 drate = ads1018->chan_data[addr].data_rate_mode; 497 498 cfg = ADS1018_CFG_VALID; 499 cfg |= FIELD_PREP(ADS1018_CFG_MUX_MASK, addr); 500 cfg |= FIELD_PREP(ADS1018_CFG_PGA_MASK, pga); 501 cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_CONTINUOUS); 502 cfg |= FIELD_PREP(ADS1018_CFG_DRATE_MASK, drate); 503 504 if (chip_info->channels[addr].type == IIO_TEMP) 505 cfg |= ADS1018_CFG_TS_MODE_EN; 506 507 ads1018->tx_buf[0] = cpu_to_be16(cfg); 508 ads1018->tx_buf[1] = 0; 509 510 return spi_write(ads1018->spi, ads1018->tx_buf, sizeof(ads1018->tx_buf)); 511 } 512 513 static int ads1018_buffer_postdisable(struct iio_dev *indio_dev) 514 { 515 struct ads1018 *ads1018 = iio_priv(indio_dev); 516 u16 cfg; 517 518 cfg = ADS1018_CFG_VALID; 519 cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_ONESHOT); 520 521 ads1018->tx_buf[0] = cpu_to_be16(cfg); 522 ads1018->tx_buf[1] = 0; 523 524 return spi_write(ads1018->spi, ads1018->tx_buf, sizeof(ads1018->tx_buf)); 525 } 526 527 static const struct iio_buffer_setup_ops ads1018_buffer_ops = { 528 .preenable = ads1018_buffer_preenable, 529 .postdisable = ads1018_buffer_postdisable, 530 .validate_scan_mask = iio_validate_scan_mask_onehot, 531 }; 532 533 static irqreturn_t ads1018_irq_handler(int irq, void *dev_id) 534 { 535 struct ads1018 *ads1018 = dev_id; 536 537 /* 538 * We need to check if the "drdy" pin is actually active or if it's a 539 * pending interrupt triggered by the SPI transfer. 540 */ 541 if (!gpiod_get_value(ads1018->drdy_gpiod)) 542 return IRQ_HANDLED; 543 544 iio_trigger_poll(ads1018->indio_trig); 545 546 return IRQ_HANDLED; 547 } 548 549 static irqreturn_t ads1018_trigger_handler(int irq, void *p) 550 { 551 struct iio_poll_func *pf = p; 552 struct iio_dev *indio_dev = pf->indio_dev; 553 struct ads1018 *ads1018 = iio_priv(indio_dev); 554 struct { 555 __be16 conv; 556 aligned_s64 ts; 557 } scan = {}; 558 int ret; 559 560 if (iio_trigger_using_own(indio_dev)) { 561 disable_irq(ads1018->drdy_irq); 562 ret = ads1018_spi_read_exclusive(ads1018, &scan.conv, true); 563 enable_irq(ads1018->drdy_irq); 564 } else { 565 ret = spi_read(ads1018->spi, ads1018->rx_buf, sizeof(ads1018->rx_buf)); 566 scan.conv = ads1018->rx_buf[0]; 567 } 568 569 if (!ret) 570 iio_push_to_buffers_with_ts(indio_dev, &scan, sizeof(scan), 571 pf->timestamp); 572 573 iio_trigger_notify_done(indio_dev->trig); 574 575 return IRQ_HANDLED; 576 } 577 578 static int ads1018_trigger_setup(struct iio_dev *indio_dev) 579 { 580 struct ads1018 *ads1018 = iio_priv(indio_dev); 581 struct spi_device *spi = ads1018->spi; 582 struct device *dev = &spi->dev; 583 const char *con_id = "drdy"; 584 int ret; 585 586 ads1018->drdy_gpiod = devm_gpiod_get_optional(dev, con_id, GPIOD_IN); 587 if (IS_ERR(ads1018->drdy_gpiod)) 588 return dev_err_probe(dev, PTR_ERR(ads1018->drdy_gpiod), 589 "Failed to get %s GPIO.\n", con_id); 590 591 /* First try to get IRQ from SPI core, then from GPIO */ 592 if (spi->irq > 0) 593 ads1018->drdy_irq = spi->irq; 594 else if (ads1018->drdy_gpiod) 595 ads1018->drdy_irq = gpiod_to_irq(ads1018->drdy_gpiod); 596 if (ads1018->drdy_irq < 0) 597 return dev_err_probe(dev, ads1018->drdy_irq, 598 "Failed to get IRQ from %s GPIO.\n", con_id); 599 600 /* An IRQ line is only an optional requirement for the IIO trigger */ 601 if (ads1018->drdy_irq == 0) 602 return 0; 603 604 ads1018->indio_trig = devm_iio_trigger_alloc(dev, "%s-dev%d-%s", 605 indio_dev->name, 606 iio_device_id(indio_dev), 607 con_id); 608 if (!ads1018->indio_trig) 609 return -ENOMEM; 610 611 iio_trigger_set_drvdata(ads1018->indio_trig, ads1018); 612 ads1018->indio_trig->ops = &ads1018_trigger_ops; 613 614 ret = devm_iio_trigger_register(dev, ads1018->indio_trig); 615 if (ret) 616 return ret; 617 618 /* 619 * The "data-ready" IRQ line is shared with the MOSI pin, thus we need 620 * to keep it disabled until we actually request data. 621 */ 622 return devm_request_irq(dev, ads1018->drdy_irq, ads1018_irq_handler, 623 IRQF_NO_AUTOEN, ads1018->chip_info->name, ads1018); 624 } 625 626 static int ads1018_spi_probe(struct spi_device *spi) 627 { 628 const struct ads1018_chip_info *info = spi_get_device_match_data(spi); 629 struct device *dev = &spi->dev; 630 struct iio_dev *indio_dev; 631 struct ads1018 *ads1018; 632 int ret; 633 634 indio_dev = devm_iio_device_alloc(dev, sizeof(*ads1018)); 635 if (!indio_dev) 636 return -ENOMEM; 637 638 ads1018 = iio_priv(indio_dev); 639 ads1018->spi = spi; 640 ads1018->chip_info = info; 641 642 indio_dev->modes = INDIO_DIRECT_MODE; 643 indio_dev->name = info->name; 644 indio_dev->info = &ads1018_iio_info; 645 indio_dev->channels = info->channels; 646 indio_dev->num_channels = info->num_channels; 647 648 for (unsigned int i = 0; i < ADS1018_CHANNELS_MAX; i++) { 649 ads1018->chan_data[i].data_rate_mode = ADS1018_DRATE_DEFAULT; 650 ads1018->chan_data[i].pga_mode = ADS1018_PGA_DEFAULT; 651 } 652 653 ads1018->xfer.rx_buf = ads1018->rx_buf; 654 ads1018->xfer.len = sizeof(ads1018->rx_buf); 655 spi_message_init_with_transfers(&ads1018->msg_read, &ads1018->xfer, 1); 656 657 ret = ads1018_trigger_setup(indio_dev); 658 if (ret) 659 return ret; 660 661 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 662 iio_pollfunc_store_time, 663 ads1018_trigger_handler, 664 &ads1018_buffer_ops); 665 if (ret) 666 return ret; 667 668 return devm_iio_device_register(&spi->dev, indio_dev); 669 } 670 671 static const unsigned int ads1018_data_rate_table[] = { 672 128, 250, 490, 920, 1600, 2400, 3300, 673 }; 674 675 static const unsigned int ads1118_data_rate_table[] = { 676 8, 16, 32, 64, 128, 250, 475, 860, 677 }; 678 679 static const struct ads1018_chip_info ads1018_chip_info = { 680 .name = "ads1018", 681 .channels = ads1018_iio_channels, 682 .num_channels = ARRAY_SIZE(ads1018_iio_channels), 683 .data_rate_mode_to_hz = ads1018_data_rate_table, 684 .num_data_rate_mode_to_hz = ARRAY_SIZE(ads1018_data_rate_table), 685 .pga_mode_to_gain = { 686 { 3, 0 }, /* fsr = 6144 mV */ 687 { 2, 0 }, /* fsr = 4096 mV */ 688 { 1, 0 }, /* fsr = 2048 mV */ 689 { 0, 500000000 }, /* fsr = 1024 mV */ 690 { 0, 250000000 }, /* fsr = 512 mV */ 691 { 0, 125000000 }, /* fsr = 256 mV */ 692 }, 693 .temp_scale = { 125, 0 }, 694 }; 695 696 static const struct ads1018_chip_info ads1118_chip_info = { 697 .name = "ads1118", 698 .channels = ads1118_iio_channels, 699 .num_channels = ARRAY_SIZE(ads1118_iio_channels), 700 .data_rate_mode_to_hz = ads1118_data_rate_table, 701 .num_data_rate_mode_to_hz = ARRAY_SIZE(ads1118_data_rate_table), 702 .pga_mode_to_gain = { 703 { 0, 187500000 }, /* fsr = 6144 mV */ 704 { 0, 125000000 }, /* fsr = 4096 mV */ 705 { 0, 62500000 }, /* fsr = 2048 mV */ 706 { 0, 31250000 }, /* fsr = 1024 mV */ 707 { 0, 15625000 }, /* fsr = 512 mV */ 708 { 0, 7812500 }, /* fsr = 256 mV */ 709 }, 710 .temp_scale = { 31, 250000 }, 711 }; 712 713 static const struct of_device_id ads1018_of_match[] = { 714 { .compatible = "ti,ads1018", .data = &ads1018_chip_info }, 715 { .compatible = "ti,ads1118", .data = &ads1118_chip_info }, 716 { } 717 }; 718 MODULE_DEVICE_TABLE(of, ads1018_of_match); 719 720 static const struct spi_device_id ads1018_spi_match[] = { 721 { "ads1018", (kernel_ulong_t)&ads1018_chip_info }, 722 { "ads1118", (kernel_ulong_t)&ads1118_chip_info }, 723 { } 724 }; 725 MODULE_DEVICE_TABLE(spi, ads1018_spi_match); 726 727 static struct spi_driver ads1018_spi_driver = { 728 .driver = { 729 .name = "ads1018", 730 .of_match_table = ads1018_of_match, 731 }, 732 .probe = ads1018_spi_probe, 733 .id_table = ads1018_spi_match, 734 }; 735 module_spi_driver(ads1018_spi_driver); 736 737 MODULE_DESCRIPTION("Texas Instruments ADS1018 ADC Driver"); 738 MODULE_LICENSE("GPL"); 739 MODULE_AUTHOR("Kurt Borja <kuurtb@gmail.com>"); 740