1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADS1015 - Texas Instruments Analog-to-Digital Converter 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * 7 * IIO driver for ADS1015 ADC 7-bit I2C slave address: 8 * * 0x48 - ADDR connected to Ground 9 * * 0x49 - ADDR connected to Vdd 10 * * 0x4A - ADDR connected to SDA 11 * * 0x4B - ADDR connected to SCL 12 */ 13 14 #include <linux/module.h> 15 #include <linux/cleanup.h> 16 #include <linux/init.h> 17 #include <linux/irq.h> 18 #include <linux/i2c.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/mutex.h> 23 #include <linux/delay.h> 24 25 #include <linux/iio/iio.h> 26 #include <linux/iio/types.h> 27 #include <linux/iio/sysfs.h> 28 #include <linux/iio/events.h> 29 #include <linux/iio/buffer.h> 30 #include <linux/iio/triggered_buffer.h> 31 #include <linux/iio/trigger_consumer.h> 32 33 #define ADS1015_DRV_NAME "ads1015" 34 35 #define ADS1015_CHANNELS 8 36 37 #define ADS1015_CONV_REG 0x00 38 #define ADS1015_CFG_REG 0x01 39 #define ADS1015_LO_THRESH_REG 0x02 40 #define ADS1015_HI_THRESH_REG 0x03 41 42 #define ADS1015_CFG_COMP_QUE_SHIFT 0 43 #define ADS1015_CFG_COMP_LAT_SHIFT 2 44 #define ADS1015_CFG_COMP_POL_SHIFT 3 45 #define ADS1015_CFG_COMP_MODE_SHIFT 4 46 #define ADS1015_CFG_DR_SHIFT 5 47 #define ADS1015_CFG_MOD_SHIFT 8 48 #define ADS1015_CFG_PGA_SHIFT 9 49 #define ADS1015_CFG_MUX_SHIFT 12 50 51 #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0) 52 #define ADS1015_CFG_COMP_LAT_MASK BIT(2) 53 #define ADS1015_CFG_COMP_POL_MASK BIT(3) 54 #define ADS1015_CFG_COMP_MODE_MASK BIT(4) 55 #define ADS1015_CFG_DR_MASK GENMASK(7, 5) 56 #define ADS1015_CFG_MOD_MASK BIT(8) 57 #define ADS1015_CFG_PGA_MASK GENMASK(11, 9) 58 #define ADS1015_CFG_MUX_MASK GENMASK(14, 12) 59 60 /* Comparator queue and disable field */ 61 #define ADS1015_CFG_COMP_DISABLE 3 62 63 /* Comparator polarity field */ 64 #define ADS1015_CFG_COMP_POL_LOW 0 65 #define ADS1015_CFG_COMP_POL_HIGH 1 66 67 /* Comparator mode field */ 68 #define ADS1015_CFG_COMP_MODE_TRAD 0 69 #define ADS1015_CFG_COMP_MODE_WINDOW 1 70 71 /* device operating modes */ 72 #define ADS1015_CONTINUOUS 0 73 #define ADS1015_SINGLESHOT 1 74 75 #define ADS1015_SLEEP_DELAY_MS 2000 76 #define ADS1015_DEFAULT_PGA 2 77 #define ADS1015_DEFAULT_DATA_RATE 4 78 #define ADS1015_DEFAULT_CHAN 0 79 80 struct ads1015_chip_data { 81 struct iio_chan_spec const *channels; 82 int num_channels; 83 const struct iio_info *info; 84 const int *data_rate; 85 const int data_rate_len; 86 const int *scale; 87 const int scale_len; 88 bool has_comparator; 89 }; 90 91 enum ads1015_channels { 92 ADS1015_AIN0_AIN1 = 0, 93 ADS1015_AIN0_AIN3, 94 ADS1015_AIN1_AIN3, 95 ADS1015_AIN2_AIN3, 96 ADS1015_AIN0, 97 ADS1015_AIN1, 98 ADS1015_AIN2, 99 ADS1015_AIN3, 100 ADS1015_TIMESTAMP, 101 }; 102 103 static const int ads1015_data_rate[] = { 104 128, 250, 490, 920, 1600, 2400, 3300, 3300 105 }; 106 107 static const int ads1115_data_rate[] = { 108 8, 16, 32, 64, 128, 250, 475, 860 109 }; 110 111 /* 112 * Translation from PGA bits to full-scale positive and negative input voltage 113 * range in mV 114 */ 115 static const int ads1015_fullscale_range[] = { 116 6144, 4096, 2048, 1024, 512, 256, 256, 256 117 }; 118 119 static const int ads1015_scale[] = { /* 12bit ADC */ 120 256, 11, 121 512, 11, 122 1024, 11, 123 2048, 11, 124 4096, 11, 125 6144, 11 126 }; 127 128 static const int ads1115_scale[] = { /* 16bit ADC */ 129 256, 15, 130 512, 15, 131 1024, 15, 132 2048, 15, 133 4096, 15, 134 6144, 15 135 }; 136 137 /* 138 * Translation from COMP_QUE field value to the number of successive readings 139 * exceed the threshold values before an interrupt is generated 140 */ 141 static const int ads1015_comp_queue[] = { 1, 2, 4 }; 142 143 static const struct iio_event_spec ads1015_events[] = { 144 { 145 .type = IIO_EV_TYPE_THRESH, 146 .dir = IIO_EV_DIR_RISING, 147 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 148 BIT(IIO_EV_INFO_ENABLE), 149 }, { 150 .type = IIO_EV_TYPE_THRESH, 151 .dir = IIO_EV_DIR_FALLING, 152 .mask_separate = BIT(IIO_EV_INFO_VALUE), 153 }, { 154 .type = IIO_EV_TYPE_THRESH, 155 .dir = IIO_EV_DIR_EITHER, 156 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | 157 BIT(IIO_EV_INFO_PERIOD), 158 }, 159 }; 160 161 /* 162 * Compile-time check whether _fitbits can accommodate up to _testbits 163 * bits. Returns _fitbits on success, fails to compile otherwise. 164 * 165 * The test works such that it multiplies constant _fitbits by constant 166 * double-negation of size of a non-empty structure, i.e. it multiplies 167 * constant _fitbits by constant 1 in each successful compilation case. 168 * The non-empty structure may contain C11 _Static_assert(), make use of 169 * this and place the kernel variant of static assert in there, so that 170 * it performs the compile-time check for _testbits <= _fitbits. Note 171 * that it is not possible to directly use static_assert in compound 172 * statements, hence this convoluted construct. 173 */ 174 #define FIT_CHECK(_testbits, _fitbits) \ 175 ( \ 176 (_fitbits) * \ 177 !!sizeof(struct { \ 178 static_assert((_testbits) <= (_fitbits)); \ 179 int pad; \ 180 }) \ 181 ) 182 183 #define ADS1015_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \ 184 .type = IIO_VOLTAGE, \ 185 .indexed = 1, \ 186 .address = _addr, \ 187 .channel = _chan, \ 188 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 189 BIT(IIO_CHAN_INFO_SCALE) | \ 190 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 191 .info_mask_shared_by_all_available = \ 192 BIT(IIO_CHAN_INFO_SCALE) | \ 193 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 194 .scan_index = _addr, \ 195 .scan_type = { \ 196 .sign = 's', \ 197 .realbits = (_realbits), \ 198 .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \ 199 .shift = (_shift), \ 200 .endianness = IIO_CPU, \ 201 }, \ 202 .event_spec = (_event_spec), \ 203 .num_event_specs = (_num_event_specs), \ 204 .datasheet_name = "AIN"#_chan, \ 205 } 206 207 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \ 208 .type = IIO_VOLTAGE, \ 209 .differential = 1, \ 210 .indexed = 1, \ 211 .address = _addr, \ 212 .channel = _chan, \ 213 .channel2 = _chan2, \ 214 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 215 BIT(IIO_CHAN_INFO_SCALE) | \ 216 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 217 .info_mask_shared_by_all_available = \ 218 BIT(IIO_CHAN_INFO_SCALE) | \ 219 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 220 .scan_index = _addr, \ 221 .scan_type = { \ 222 .sign = 's', \ 223 .realbits = (_realbits), \ 224 .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \ 225 .shift = (_shift), \ 226 .endianness = IIO_CPU, \ 227 }, \ 228 .event_spec = (_event_spec), \ 229 .num_event_specs = (_num_event_specs), \ 230 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \ 231 } 232 233 struct ads1015_channel_data { 234 bool enabled; 235 unsigned int pga; 236 unsigned int data_rate; 237 }; 238 239 struct ads1015_thresh_data { 240 unsigned int comp_queue; 241 int high_thresh; 242 int low_thresh; 243 }; 244 245 struct ads1015_data { 246 struct regmap *regmap; 247 /* 248 * Protects ADC ops, e.g: concurrent sysfs/buffered 249 * data reads, configuration updates 250 */ 251 struct mutex lock; 252 struct ads1015_channel_data channel_data[ADS1015_CHANNELS]; 253 254 unsigned int event_channel; 255 unsigned int comp_mode; 256 struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS]; 257 258 const struct ads1015_chip_data *chip; 259 /* 260 * Set to true when the ADC is switched to the continuous-conversion 261 * mode and exits from a power-down state. This flag is used to avoid 262 * getting the stale result from the conversion register. 263 */ 264 bool conv_invalid; 265 }; 266 267 static bool ads1015_event_channel_enabled(struct ads1015_data *data) 268 { 269 return (data->event_channel != ADS1015_CHANNELS); 270 } 271 272 static void ads1015_event_channel_enable(struct ads1015_data *data, int chan, 273 int comp_mode) 274 { 275 WARN_ON(ads1015_event_channel_enabled(data)); 276 277 data->event_channel = chan; 278 data->comp_mode = comp_mode; 279 } 280 281 static void ads1015_event_channel_disable(struct ads1015_data *data, int chan) 282 { 283 data->event_channel = ADS1015_CHANNELS; 284 } 285 286 static const struct regmap_range ads1015_writeable_ranges[] = { 287 regmap_reg_range(ADS1015_CFG_REG, ADS1015_HI_THRESH_REG), 288 }; 289 290 static const struct regmap_access_table ads1015_writeable_table = { 291 .yes_ranges = ads1015_writeable_ranges, 292 .n_yes_ranges = ARRAY_SIZE(ads1015_writeable_ranges), 293 }; 294 295 static const struct regmap_config ads1015_regmap_config = { 296 .reg_bits = 8, 297 .val_bits = 16, 298 .max_register = ADS1015_HI_THRESH_REG, 299 .wr_table = &ads1015_writeable_table, 300 }; 301 302 static const struct regmap_range tla2024_writeable_ranges[] = { 303 regmap_reg_range(ADS1015_CFG_REG, ADS1015_CFG_REG), 304 }; 305 306 static const struct regmap_access_table tla2024_writeable_table = { 307 .yes_ranges = tla2024_writeable_ranges, 308 .n_yes_ranges = ARRAY_SIZE(tla2024_writeable_ranges), 309 }; 310 311 static const struct regmap_config tla2024_regmap_config = { 312 .reg_bits = 8, 313 .val_bits = 16, 314 .max_register = ADS1015_CFG_REG, 315 .wr_table = &tla2024_writeable_table, 316 }; 317 318 static const struct iio_chan_spec ads1015_channels[] = { 319 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4, 320 ads1015_events, ARRAY_SIZE(ads1015_events)), 321 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4, 322 ads1015_events, ARRAY_SIZE(ads1015_events)), 323 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4, 324 ads1015_events, ARRAY_SIZE(ads1015_events)), 325 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4, 326 ads1015_events, ARRAY_SIZE(ads1015_events)), 327 ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4, 328 ads1015_events, ARRAY_SIZE(ads1015_events)), 329 ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4, 330 ads1015_events, ARRAY_SIZE(ads1015_events)), 331 ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4, 332 ads1015_events, ARRAY_SIZE(ads1015_events)), 333 ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4, 334 ads1015_events, ARRAY_SIZE(ads1015_events)), 335 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP), 336 }; 337 338 static const struct iio_chan_spec ads1115_channels[] = { 339 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 16, 0, 340 ads1015_events, ARRAY_SIZE(ads1015_events)), 341 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 16, 0, 342 ads1015_events, ARRAY_SIZE(ads1015_events)), 343 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 16, 0, 344 ads1015_events, ARRAY_SIZE(ads1015_events)), 345 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 16, 0, 346 ads1015_events, ARRAY_SIZE(ads1015_events)), 347 ADS1015_V_CHAN(0, ADS1015_AIN0, 16, 0, 348 ads1015_events, ARRAY_SIZE(ads1015_events)), 349 ADS1015_V_CHAN(1, ADS1015_AIN1, 16, 0, 350 ads1015_events, ARRAY_SIZE(ads1015_events)), 351 ADS1015_V_CHAN(2, ADS1015_AIN2, 16, 0, 352 ads1015_events, ARRAY_SIZE(ads1015_events)), 353 ADS1015_V_CHAN(3, ADS1015_AIN3, 16, 0, 354 ads1015_events, ARRAY_SIZE(ads1015_events)), 355 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP), 356 }; 357 358 static const struct iio_chan_spec tla2024_channels[] = { 359 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4, NULL, 0), 360 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4, NULL, 0), 361 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4, NULL, 0), 362 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4, NULL, 0), 363 ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4, NULL, 0), 364 ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4, NULL, 0), 365 ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4, NULL, 0), 366 ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4, NULL, 0), 367 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP), 368 }; 369 370 371 #ifdef CONFIG_PM 372 static int ads1015_set_power_state(struct ads1015_data *data, bool on) 373 { 374 int ret; 375 struct device *dev = regmap_get_device(data->regmap); 376 377 if (on) { 378 ret = pm_runtime_resume_and_get(dev); 379 } else { 380 pm_runtime_mark_last_busy(dev); 381 ret = pm_runtime_put_autosuspend(dev); 382 } 383 384 return ret < 0 ? ret : 0; 385 } 386 387 #else /* !CONFIG_PM */ 388 389 static int ads1015_set_power_state(struct ads1015_data *data, bool on) 390 { 391 return 0; 392 } 393 394 #endif /* !CONFIG_PM */ 395 396 static 397 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val) 398 { 399 const int *data_rate = data->chip->data_rate; 400 int ret, pga, dr, dr_old, conv_time; 401 unsigned int old, mask, cfg; 402 403 if (chan < 0 || chan >= ADS1015_CHANNELS) 404 return -EINVAL; 405 406 ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old); 407 if (ret) 408 return ret; 409 410 pga = data->channel_data[chan].pga; 411 dr = data->channel_data[chan].data_rate; 412 mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK | 413 ADS1015_CFG_DR_MASK; 414 cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT | 415 dr << ADS1015_CFG_DR_SHIFT; 416 417 if (ads1015_event_channel_enabled(data)) { 418 mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK; 419 cfg |= data->thresh_data[chan].comp_queue << 420 ADS1015_CFG_COMP_QUE_SHIFT | 421 data->comp_mode << 422 ADS1015_CFG_COMP_MODE_SHIFT; 423 } 424 425 cfg = (old & ~mask) | (cfg & mask); 426 if (old != cfg) { 427 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg); 428 if (ret) 429 return ret; 430 data->conv_invalid = true; 431 } 432 if (data->conv_invalid) { 433 dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT; 434 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr_old]); 435 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr]); 436 conv_time += conv_time / 10; /* 10% internal clock inaccuracy */ 437 usleep_range(conv_time, conv_time + 1); 438 data->conv_invalid = false; 439 } 440 441 return regmap_read(data->regmap, ADS1015_CONV_REG, val); 442 } 443 444 static irqreturn_t ads1015_trigger_handler(int irq, void *p) 445 { 446 struct iio_poll_func *pf = p; 447 struct iio_dev *indio_dev = pf->indio_dev; 448 struct ads1015_data *data = iio_priv(indio_dev); 449 /* Ensure natural alignment of timestamp */ 450 struct { 451 s16 chan; 452 aligned_s64 timestamp; 453 } scan = { }; 454 int chan, ret, res; 455 456 mutex_lock(&data->lock); 457 chan = find_first_bit(indio_dev->active_scan_mask, 458 iio_get_masklength(indio_dev)); 459 ret = ads1015_get_adc_result(data, chan, &res); 460 if (ret < 0) { 461 mutex_unlock(&data->lock); 462 goto err; 463 } 464 465 scan.chan = res; 466 mutex_unlock(&data->lock); 467 468 iio_push_to_buffers_with_ts(indio_dev, &scan, sizeof(scan), 469 iio_get_time_ns(indio_dev)); 470 471 err: 472 iio_trigger_notify_done(indio_dev->trig); 473 474 return IRQ_HANDLED; 475 } 476 477 static int ads1015_set_scale(struct ads1015_data *data, 478 struct iio_chan_spec const *chan, 479 int scale, int uscale) 480 { 481 int i; 482 int fullscale = div_s64((scale * 1000000LL + uscale) << 483 (chan->scan_type.realbits - 1), 1000000); 484 485 for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) { 486 if (ads1015_fullscale_range[i] == fullscale) { 487 data->channel_data[chan->address].pga = i; 488 return 0; 489 } 490 } 491 492 return -EINVAL; 493 } 494 495 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate) 496 { 497 int i; 498 499 for (i = 0; i < data->chip->data_rate_len; i++) { 500 if (data->chip->data_rate[i] == rate) { 501 data->channel_data[chan].data_rate = i; 502 return 0; 503 } 504 } 505 506 return -EINVAL; 507 } 508 509 static int ads1015_read_avail(struct iio_dev *indio_dev, 510 struct iio_chan_spec const *chan, 511 const int **vals, int *type, int *length, 512 long mask) 513 { 514 struct ads1015_data *data = iio_priv(indio_dev); 515 516 if (chan->type != IIO_VOLTAGE) 517 return -EINVAL; 518 519 switch (mask) { 520 case IIO_CHAN_INFO_SCALE: 521 *type = IIO_VAL_FRACTIONAL_LOG2; 522 *vals = data->chip->scale; 523 *length = data->chip->scale_len; 524 return IIO_AVAIL_LIST; 525 case IIO_CHAN_INFO_SAMP_FREQ: 526 *type = IIO_VAL_INT; 527 *vals = data->chip->data_rate; 528 *length = data->chip->data_rate_len; 529 return IIO_AVAIL_LIST; 530 default: 531 return -EINVAL; 532 } 533 } 534 535 static int __ads1015_read_info_raw(struct ads1015_data *data, 536 struct iio_chan_spec const *chan, int *val) 537 { 538 int ret; 539 540 if (ads1015_event_channel_enabled(data) && 541 data->event_channel != chan->address) 542 return -EBUSY; 543 544 ret = ads1015_set_power_state(data, true); 545 if (ret < 0) 546 return ret; 547 548 ret = ads1015_get_adc_result(data, chan->address, val); 549 if (ret < 0) { 550 ads1015_set_power_state(data, false); 551 return ret; 552 } 553 554 *val = sign_extend32(*val >> chan->scan_type.shift, 555 chan->scan_type.realbits - 1); 556 557 return ads1015_set_power_state(data, false); 558 } 559 560 static int ads1015_read_raw(struct iio_dev *indio_dev, 561 struct iio_chan_spec const *chan, int *val, 562 int *val2, long mask) 563 { 564 int ret, idx; 565 struct ads1015_data *data = iio_priv(indio_dev); 566 567 guard(mutex)(&data->lock); 568 switch (mask) { 569 case IIO_CHAN_INFO_RAW: 570 if (!iio_device_claim_direct(indio_dev)) 571 return -EBUSY; 572 ret = __ads1015_read_info_raw(data, chan, val); 573 iio_device_release_direct(indio_dev); 574 if (ret) 575 return ret; 576 577 return IIO_VAL_INT; 578 case IIO_CHAN_INFO_SCALE: 579 idx = data->channel_data[chan->address].pga; 580 *val = ads1015_fullscale_range[idx]; 581 *val2 = chan->scan_type.realbits - 1; 582 return IIO_VAL_FRACTIONAL_LOG2; 583 case IIO_CHAN_INFO_SAMP_FREQ: 584 idx = data->channel_data[chan->address].data_rate; 585 *val = data->chip->data_rate[idx]; 586 return IIO_VAL_INT; 587 default: 588 return -EINVAL; 589 } 590 } 591 592 static int ads1015_write_raw(struct iio_dev *indio_dev, 593 struct iio_chan_spec const *chan, int val, 594 int val2, long mask) 595 { 596 struct ads1015_data *data = iio_priv(indio_dev); 597 598 guard(mutex)(&data->lock); 599 switch (mask) { 600 case IIO_CHAN_INFO_SCALE: 601 return ads1015_set_scale(data, chan, val, val2); 602 case IIO_CHAN_INFO_SAMP_FREQ: 603 return ads1015_set_data_rate(data, chan->address, val); 604 default: 605 return -EINVAL; 606 } 607 } 608 609 static int ads1015_read_event(struct iio_dev *indio_dev, 610 const struct iio_chan_spec *chan, enum iio_event_type type, 611 enum iio_event_direction dir, enum iio_event_info info, int *val, 612 int *val2) 613 { 614 struct ads1015_data *data = iio_priv(indio_dev); 615 unsigned int comp_queue; 616 int period; 617 int dr; 618 619 guard(mutex)(&data->lock); 620 621 switch (info) { 622 case IIO_EV_INFO_VALUE: 623 *val = (dir == IIO_EV_DIR_RISING) ? 624 data->thresh_data[chan->address].high_thresh : 625 data->thresh_data[chan->address].low_thresh; 626 return IIO_VAL_INT; 627 case IIO_EV_INFO_PERIOD: 628 dr = data->channel_data[chan->address].data_rate; 629 comp_queue = data->thresh_data[chan->address].comp_queue; 630 period = ads1015_comp_queue[comp_queue] * 631 USEC_PER_SEC / data->chip->data_rate[dr]; 632 633 *val = period / USEC_PER_SEC; 634 *val2 = period % USEC_PER_SEC; 635 return IIO_VAL_INT_PLUS_MICRO; 636 default: 637 return -EINVAL; 638 } 639 } 640 641 static int ads1015_write_event(struct iio_dev *indio_dev, 642 const struct iio_chan_spec *chan, enum iio_event_type type, 643 enum iio_event_direction dir, enum iio_event_info info, int val, 644 int val2) 645 { 646 struct ads1015_data *data = iio_priv(indio_dev); 647 const int *data_rate = data->chip->data_rate; 648 int realbits = chan->scan_type.realbits; 649 long long period; 650 int i; 651 int dr; 652 653 guard(mutex)(&data->lock); 654 655 switch (info) { 656 case IIO_EV_INFO_VALUE: 657 if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) 658 return -EINVAL; 659 660 if (dir == IIO_EV_DIR_RISING) 661 data->thresh_data[chan->address].high_thresh = val; 662 else 663 data->thresh_data[chan->address].low_thresh = val; 664 return 0; 665 case IIO_EV_INFO_PERIOD: 666 dr = data->channel_data[chan->address].data_rate; 667 period = val * USEC_PER_SEC + val2; 668 669 for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) { 670 if (period <= ads1015_comp_queue[i] * 671 USEC_PER_SEC / data_rate[dr]) 672 break; 673 } 674 data->thresh_data[chan->address].comp_queue = i; 675 return 0; 676 default: 677 return -EINVAL; 678 } 679 } 680 681 static int ads1015_read_event_config(struct iio_dev *indio_dev, 682 const struct iio_chan_spec *chan, enum iio_event_type type, 683 enum iio_event_direction dir) 684 { 685 struct ads1015_data *data = iio_priv(indio_dev); 686 687 guard(mutex)(&data->lock); 688 if (data->event_channel != chan->address) 689 return 0; 690 691 switch (dir) { 692 case IIO_EV_DIR_RISING: 693 return 1; 694 case IIO_EV_DIR_EITHER: 695 return (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW); 696 default: 697 return -EINVAL; 698 } 699 } 700 701 static int ads1015_enable_event_config(struct ads1015_data *data, 702 const struct iio_chan_spec *chan, int comp_mode) 703 { 704 int low_thresh = data->thresh_data[chan->address].low_thresh; 705 int high_thresh = data->thresh_data[chan->address].high_thresh; 706 int ret; 707 unsigned int val; 708 709 if (ads1015_event_channel_enabled(data)) { 710 if (data->event_channel != chan->address || 711 (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD && 712 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)) 713 return -EBUSY; 714 715 return 0; 716 } 717 718 if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) { 719 low_thresh = max(-1 << (chan->scan_type.realbits - 1), 720 high_thresh - 1); 721 } 722 ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG, 723 low_thresh << chan->scan_type.shift); 724 if (ret) 725 return ret; 726 727 ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG, 728 high_thresh << chan->scan_type.shift); 729 if (ret) 730 return ret; 731 732 ret = ads1015_set_power_state(data, true); 733 if (ret < 0) 734 return ret; 735 736 ads1015_event_channel_enable(data, chan->address, comp_mode); 737 738 ret = ads1015_get_adc_result(data, chan->address, &val); 739 if (ret) { 740 ads1015_event_channel_disable(data, chan->address); 741 ads1015_set_power_state(data, false); 742 } 743 744 return ret; 745 } 746 747 static int ads1015_disable_event_config(struct ads1015_data *data, 748 const struct iio_chan_spec *chan, int comp_mode) 749 { 750 int ret; 751 752 if (!ads1015_event_channel_enabled(data)) 753 return 0; 754 755 if (data->event_channel != chan->address) 756 return 0; 757 758 if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD && 759 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW) 760 return 0; 761 762 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG, 763 ADS1015_CFG_COMP_QUE_MASK, 764 ADS1015_CFG_COMP_DISABLE << 765 ADS1015_CFG_COMP_QUE_SHIFT); 766 if (ret) 767 return ret; 768 769 ads1015_event_channel_disable(data, chan->address); 770 771 return ads1015_set_power_state(data, false); 772 } 773 774 static int ads1015_write_event_config(struct iio_dev *indio_dev, 775 const struct iio_chan_spec *chan, enum iio_event_type type, 776 enum iio_event_direction dir, bool state) 777 { 778 struct ads1015_data *data = iio_priv(indio_dev); 779 int ret; 780 int comp_mode = (dir == IIO_EV_DIR_EITHER) ? 781 ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD; 782 783 guard(mutex)(&data->lock); 784 785 /* Prevent from enabling both buffer and event at a time */ 786 if (!iio_device_claim_direct(indio_dev)) 787 return -EBUSY; 788 789 if (state) 790 ret = ads1015_enable_event_config(data, chan, comp_mode); 791 else 792 ret = ads1015_disable_event_config(data, chan, comp_mode); 793 794 iio_device_release_direct(indio_dev); 795 return ret; 796 } 797 798 static irqreturn_t ads1015_event_handler(int irq, void *priv) 799 { 800 struct iio_dev *indio_dev = priv; 801 struct ads1015_data *data = iio_priv(indio_dev); 802 int val; 803 int ret; 804 805 /* Clear the latched ALERT/RDY pin */ 806 ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val); 807 if (ret) 808 return IRQ_HANDLED; 809 810 if (ads1015_event_channel_enabled(data)) { 811 enum iio_event_direction dir; 812 u64 code; 813 814 dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ? 815 IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER; 816 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel, 817 IIO_EV_TYPE_THRESH, dir); 818 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev)); 819 } 820 821 return IRQ_HANDLED; 822 } 823 824 static int ads1015_buffer_preenable(struct iio_dev *indio_dev) 825 { 826 struct ads1015_data *data = iio_priv(indio_dev); 827 828 /* Prevent from enabling both buffer and event at a time */ 829 if (ads1015_event_channel_enabled(data)) 830 return -EBUSY; 831 832 return ads1015_set_power_state(iio_priv(indio_dev), true); 833 } 834 835 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev) 836 { 837 return ads1015_set_power_state(iio_priv(indio_dev), false); 838 } 839 840 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = { 841 .preenable = ads1015_buffer_preenable, 842 .postdisable = ads1015_buffer_postdisable, 843 .validate_scan_mask = &iio_validate_scan_mask_onehot, 844 }; 845 846 static const struct iio_info ads1015_info = { 847 .read_avail = ads1015_read_avail, 848 .read_raw = ads1015_read_raw, 849 .write_raw = ads1015_write_raw, 850 .read_event_value = ads1015_read_event, 851 .write_event_value = ads1015_write_event, 852 .read_event_config = ads1015_read_event_config, 853 .write_event_config = ads1015_write_event_config, 854 }; 855 856 static const struct iio_info tla2024_info = { 857 .read_avail = ads1015_read_avail, 858 .read_raw = ads1015_read_raw, 859 .write_raw = ads1015_write_raw, 860 }; 861 862 static int ads1015_client_get_channels_config(struct i2c_client *client) 863 { 864 struct iio_dev *indio_dev = i2c_get_clientdata(client); 865 struct ads1015_data *data = iio_priv(indio_dev); 866 struct device *dev = &client->dev; 867 int i = -1; 868 869 device_for_each_child_node_scoped(dev, node) { 870 u32 pval; 871 unsigned int channel; 872 unsigned int pga = ADS1015_DEFAULT_PGA; 873 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE; 874 875 if (fwnode_property_read_u32(node, "reg", &pval)) { 876 dev_err(dev, "invalid reg on %pfw\n", node); 877 continue; 878 } 879 880 channel = pval; 881 if (channel >= ADS1015_CHANNELS) { 882 dev_err(dev, "invalid channel index %d on %pfw\n", 883 channel, node); 884 continue; 885 } 886 887 if (!fwnode_property_read_u32(node, "ti,gain", &pval)) { 888 pga = pval; 889 if (pga > 5) { 890 dev_err(dev, "invalid gain on %pfw\n", node); 891 return -EINVAL; 892 } 893 } 894 895 if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) { 896 data_rate = pval; 897 if (data_rate > 7) { 898 dev_err(dev, "invalid data_rate on %pfw\n", node); 899 return -EINVAL; 900 } 901 } 902 903 data->channel_data[channel].pga = pga; 904 data->channel_data[channel].data_rate = data_rate; 905 906 i++; 907 } 908 909 return i < 0 ? -EINVAL : 0; 910 } 911 912 static void ads1015_get_channels_config(struct i2c_client *client) 913 { 914 unsigned int k; 915 916 struct iio_dev *indio_dev = i2c_get_clientdata(client); 917 struct ads1015_data *data = iio_priv(indio_dev); 918 919 if (!ads1015_client_get_channels_config(client)) 920 return; 921 922 /* fallback on default configuration */ 923 for (k = 0; k < ADS1015_CHANNELS; ++k) { 924 data->channel_data[k].pga = ADS1015_DEFAULT_PGA; 925 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE; 926 } 927 } 928 929 static int ads1015_set_conv_mode(struct ads1015_data *data, int mode) 930 { 931 return regmap_update_bits(data->regmap, ADS1015_CFG_REG, 932 ADS1015_CFG_MOD_MASK, 933 mode << ADS1015_CFG_MOD_SHIFT); 934 } 935 936 static int ads1015_probe(struct i2c_client *client) 937 { 938 const struct ads1015_chip_data *chip; 939 struct iio_dev *indio_dev; 940 struct ads1015_data *data; 941 int ret; 942 int i; 943 944 chip = i2c_get_match_data(client); 945 if (!chip) 946 return dev_err_probe(&client->dev, -EINVAL, "Unknown chip\n"); 947 948 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 949 if (!indio_dev) 950 return -ENOMEM; 951 952 data = iio_priv(indio_dev); 953 i2c_set_clientdata(client, indio_dev); 954 955 mutex_init(&data->lock); 956 957 indio_dev->name = ADS1015_DRV_NAME; 958 indio_dev->modes = INDIO_DIRECT_MODE; 959 960 indio_dev->channels = chip->channels; 961 indio_dev->num_channels = chip->num_channels; 962 indio_dev->info = chip->info; 963 data->chip = chip; 964 data->event_channel = ADS1015_CHANNELS; 965 966 /* 967 * Set default lower and upper threshold to min and max value 968 * respectively. 969 */ 970 for (i = 0; i < ADS1015_CHANNELS; i++) { 971 int realbits = indio_dev->channels[i].scan_type.realbits; 972 973 data->thresh_data[i].low_thresh = -1 << (realbits - 1); 974 data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1; 975 } 976 977 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */ 978 ads1015_get_channels_config(client); 979 980 data->regmap = devm_regmap_init_i2c(client, chip->has_comparator ? 981 &ads1015_regmap_config : 982 &tla2024_regmap_config); 983 if (IS_ERR(data->regmap)) { 984 dev_err(&client->dev, "Failed to allocate register map\n"); 985 return PTR_ERR(data->regmap); 986 } 987 988 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL, 989 ads1015_trigger_handler, 990 &ads1015_buffer_setup_ops); 991 if (ret < 0) { 992 dev_err(&client->dev, "iio triggered buffer setup failed\n"); 993 return ret; 994 } 995 996 if (client->irq && chip->has_comparator) { 997 unsigned long irq_trig = irq_get_trigger_type(client->irq); 998 unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK | 999 ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK; 1000 unsigned int cfg_comp = 1001 ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT | 1002 1 << ADS1015_CFG_COMP_LAT_SHIFT; 1003 1004 switch (irq_trig) { 1005 case IRQF_TRIGGER_FALLING: 1006 case IRQF_TRIGGER_LOW: 1007 cfg_comp |= ADS1015_CFG_COMP_POL_LOW << 1008 ADS1015_CFG_COMP_POL_SHIFT; 1009 break; 1010 case IRQF_TRIGGER_HIGH: 1011 case IRQF_TRIGGER_RISING: 1012 cfg_comp |= ADS1015_CFG_COMP_POL_HIGH << 1013 ADS1015_CFG_COMP_POL_SHIFT; 1014 break; 1015 default: 1016 return -EINVAL; 1017 } 1018 1019 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG, 1020 cfg_comp_mask, cfg_comp); 1021 if (ret) 1022 return ret; 1023 1024 ret = devm_request_threaded_irq(&client->dev, client->irq, 1025 NULL, ads1015_event_handler, 1026 irq_trig | IRQF_ONESHOT, 1027 client->name, indio_dev); 1028 if (ret) 1029 return ret; 1030 } 1031 1032 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS); 1033 if (ret) 1034 return ret; 1035 1036 data->conv_invalid = true; 1037 1038 ret = pm_runtime_set_active(&client->dev); 1039 if (ret) 1040 return ret; 1041 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS); 1042 pm_runtime_use_autosuspend(&client->dev); 1043 pm_runtime_enable(&client->dev); 1044 1045 ret = iio_device_register(indio_dev); 1046 if (ret < 0) { 1047 dev_err(&client->dev, "Failed to register IIO device\n"); 1048 return ret; 1049 } 1050 1051 return 0; 1052 } 1053 1054 static void ads1015_remove(struct i2c_client *client) 1055 { 1056 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1057 struct ads1015_data *data = iio_priv(indio_dev); 1058 int ret; 1059 1060 iio_device_unregister(indio_dev); 1061 1062 pm_runtime_disable(&client->dev); 1063 pm_runtime_set_suspended(&client->dev); 1064 1065 /* power down single shot mode */ 1066 ret = ads1015_set_conv_mode(data, ADS1015_SINGLESHOT); 1067 if (ret) 1068 dev_warn(&client->dev, "Failed to power down (%pe)\n", 1069 ERR_PTR(ret)); 1070 } 1071 1072 #ifdef CONFIG_PM 1073 static int ads1015_runtime_suspend(struct device *dev) 1074 { 1075 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1076 struct ads1015_data *data = iio_priv(indio_dev); 1077 1078 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT); 1079 } 1080 1081 static int ads1015_runtime_resume(struct device *dev) 1082 { 1083 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1084 struct ads1015_data *data = iio_priv(indio_dev); 1085 int ret; 1086 1087 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS); 1088 if (!ret) 1089 data->conv_invalid = true; 1090 1091 return ret; 1092 } 1093 #endif 1094 1095 static const struct dev_pm_ops ads1015_pm_ops = { 1096 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend, 1097 ads1015_runtime_resume, NULL) 1098 }; 1099 1100 static const struct ads1015_chip_data ads1015_data = { 1101 .channels = ads1015_channels, 1102 .num_channels = ARRAY_SIZE(ads1015_channels), 1103 .info = &ads1015_info, 1104 .data_rate = ads1015_data_rate, 1105 .data_rate_len = ARRAY_SIZE(ads1015_data_rate), 1106 .scale = ads1015_scale, 1107 .scale_len = ARRAY_SIZE(ads1015_scale), 1108 .has_comparator = true, 1109 }; 1110 1111 static const struct ads1015_chip_data ads1115_data = { 1112 .channels = ads1115_channels, 1113 .num_channels = ARRAY_SIZE(ads1115_channels), 1114 .info = &ads1015_info, 1115 .data_rate = ads1115_data_rate, 1116 .data_rate_len = ARRAY_SIZE(ads1115_data_rate), 1117 .scale = ads1115_scale, 1118 .scale_len = ARRAY_SIZE(ads1115_scale), 1119 .has_comparator = true, 1120 }; 1121 1122 static const struct ads1015_chip_data tla2024_data = { 1123 .channels = tla2024_channels, 1124 .num_channels = ARRAY_SIZE(tla2024_channels), 1125 .info = &tla2024_info, 1126 .data_rate = ads1015_data_rate, 1127 .data_rate_len = ARRAY_SIZE(ads1015_data_rate), 1128 .scale = ads1015_scale, 1129 .scale_len = ARRAY_SIZE(ads1015_scale), 1130 .has_comparator = false, 1131 }; 1132 1133 static const struct i2c_device_id ads1015_id[] = { 1134 { "ads1015", (kernel_ulong_t)&ads1015_data }, 1135 { "ads1115", (kernel_ulong_t)&ads1115_data }, 1136 { "tla2024", (kernel_ulong_t)&tla2024_data }, 1137 { } 1138 }; 1139 MODULE_DEVICE_TABLE(i2c, ads1015_id); 1140 1141 static const struct of_device_id ads1015_of_match[] = { 1142 { .compatible = "ti,ads1015", .data = &ads1015_data }, 1143 { .compatible = "ti,ads1115", .data = &ads1115_data }, 1144 { .compatible = "ti,tla2024", .data = &tla2024_data }, 1145 { } 1146 }; 1147 MODULE_DEVICE_TABLE(of, ads1015_of_match); 1148 1149 static struct i2c_driver ads1015_driver = { 1150 .driver = { 1151 .name = ADS1015_DRV_NAME, 1152 .of_match_table = ads1015_of_match, 1153 .pm = &ads1015_pm_ops, 1154 }, 1155 .probe = ads1015_probe, 1156 .remove = ads1015_remove, 1157 .id_table = ads1015_id, 1158 }; 1159 1160 module_i2c_driver(ads1015_driver); 1161 1162 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>"); 1163 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver"); 1164 MODULE_LICENSE("GPL v2"); 1165