1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADS1015 - Texas Instruments Analog-to-Digital Converter 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * 7 * IIO driver for ADS1015 ADC 7-bit I2C slave address: 8 * * 0x48 - ADDR connected to Ground 9 * * 0x49 - ADDR connected to Vdd 10 * * 0x4A - ADDR connected to SDA 11 * * 0x4B - ADDR connected to SCL 12 */ 13 14 #include <linux/module.h> 15 #include <linux/cleanup.h> 16 #include <linux/init.h> 17 #include <linux/irq.h> 18 #include <linux/i2c.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/mutex.h> 23 #include <linux/delay.h> 24 25 #include <linux/iio/iio.h> 26 #include <linux/iio/types.h> 27 #include <linux/iio/sysfs.h> 28 #include <linux/iio/events.h> 29 #include <linux/iio/buffer.h> 30 #include <linux/iio/triggered_buffer.h> 31 #include <linux/iio/trigger_consumer.h> 32 33 #define ADS1015_DRV_NAME "ads1015" 34 35 #define ADS1015_CHANNELS 8 36 37 #define ADS1015_CONV_REG 0x00 38 #define ADS1015_CFG_REG 0x01 39 #define ADS1015_LO_THRESH_REG 0x02 40 #define ADS1015_HI_THRESH_REG 0x03 41 42 #define ADS1015_CFG_COMP_QUE_SHIFT 0 43 #define ADS1015_CFG_COMP_LAT_SHIFT 2 44 #define ADS1015_CFG_COMP_POL_SHIFT 3 45 #define ADS1015_CFG_COMP_MODE_SHIFT 4 46 #define ADS1015_CFG_DR_SHIFT 5 47 #define ADS1015_CFG_MOD_SHIFT 8 48 #define ADS1015_CFG_PGA_SHIFT 9 49 #define ADS1015_CFG_MUX_SHIFT 12 50 51 #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0) 52 #define ADS1015_CFG_COMP_LAT_MASK BIT(2) 53 #define ADS1015_CFG_COMP_POL_MASK BIT(3) 54 #define ADS1015_CFG_COMP_MODE_MASK BIT(4) 55 #define ADS1015_CFG_DR_MASK GENMASK(7, 5) 56 #define ADS1015_CFG_MOD_MASK BIT(8) 57 #define ADS1015_CFG_PGA_MASK GENMASK(11, 9) 58 #define ADS1015_CFG_MUX_MASK GENMASK(14, 12) 59 60 /* Comparator queue and disable field */ 61 #define ADS1015_CFG_COMP_DISABLE 3 62 63 /* Comparator polarity field */ 64 #define ADS1015_CFG_COMP_POL_LOW 0 65 #define ADS1015_CFG_COMP_POL_HIGH 1 66 67 /* Comparator mode field */ 68 #define ADS1015_CFG_COMP_MODE_TRAD 0 69 #define ADS1015_CFG_COMP_MODE_WINDOW 1 70 71 /* device operating modes */ 72 #define ADS1015_CONTINUOUS 0 73 #define ADS1015_SINGLESHOT 1 74 75 #define ADS1015_SLEEP_DELAY_MS 2000 76 #define ADS1015_DEFAULT_PGA 2 77 #define ADS1015_DEFAULT_DATA_RATE 4 78 #define ADS1015_DEFAULT_CHAN 0 79 80 struct ads1015_chip_data { 81 struct iio_chan_spec const *channels; 82 int num_channels; 83 const struct iio_info *info; 84 const int *data_rate; 85 const int data_rate_len; 86 const int *scale; 87 const int scale_len; 88 bool has_comparator; 89 }; 90 91 enum ads1015_channels { 92 ADS1015_AIN0_AIN1 = 0, 93 ADS1015_AIN0_AIN3, 94 ADS1015_AIN1_AIN3, 95 ADS1015_AIN2_AIN3, 96 ADS1015_AIN0, 97 ADS1015_AIN1, 98 ADS1015_AIN2, 99 ADS1015_AIN3, 100 ADS1015_TIMESTAMP, 101 }; 102 103 static const int ads1015_data_rate[] = { 104 128, 250, 490, 920, 1600, 2400, 3300, 3300 105 }; 106 107 static const int ads1115_data_rate[] = { 108 8, 16, 32, 64, 128, 250, 475, 860 109 }; 110 111 /* 112 * Translation from PGA bits to full-scale positive and negative input voltage 113 * range in mV 114 */ 115 static const int ads1015_fullscale_range[] = { 116 6144, 4096, 2048, 1024, 512, 256, 256, 256 117 }; 118 119 static const int ads1015_scale[] = { /* 12bit ADC */ 120 256, 11, 121 512, 11, 122 1024, 11, 123 2048, 11, 124 4096, 11, 125 6144, 11 126 }; 127 128 static const int ads1115_scale[] = { /* 16bit ADC */ 129 256, 15, 130 512, 15, 131 1024, 15, 132 2048, 15, 133 4096, 15, 134 6144, 15 135 }; 136 137 /* 138 * Translation from COMP_QUE field value to the number of successive readings 139 * exceed the threshold values before an interrupt is generated 140 */ 141 static const int ads1015_comp_queue[] = { 1, 2, 4 }; 142 143 static const struct iio_event_spec ads1015_events[] = { 144 { 145 .type = IIO_EV_TYPE_THRESH, 146 .dir = IIO_EV_DIR_RISING, 147 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 148 BIT(IIO_EV_INFO_ENABLE), 149 }, { 150 .type = IIO_EV_TYPE_THRESH, 151 .dir = IIO_EV_DIR_FALLING, 152 .mask_separate = BIT(IIO_EV_INFO_VALUE), 153 }, { 154 .type = IIO_EV_TYPE_THRESH, 155 .dir = IIO_EV_DIR_EITHER, 156 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | 157 BIT(IIO_EV_INFO_PERIOD), 158 }, 159 }; 160 161 /* 162 * Compile-time check whether _fitbits can accommodate up to _testbits 163 * bits. Returns _fitbits on success, fails to compile otherwise. 164 * 165 * The test works such that it multiplies constant _fitbits by constant 166 * double-negation of size of a non-empty structure, i.e. it multiplies 167 * constant _fitbits by constant 1 in each successful compilation case. 168 * The non-empty structure may contain C11 _Static_assert(), make use of 169 * this and place the kernel variant of static assert in there, so that 170 * it performs the compile-time check for _testbits <= _fitbits. Note 171 * that it is not possible to directly use static_assert in compound 172 * statements, hence this convoluted construct. 173 */ 174 #define FIT_CHECK(_testbits, _fitbits) \ 175 ( \ 176 (_fitbits) * \ 177 !!sizeof(struct { \ 178 static_assert((_testbits) <= (_fitbits)); \ 179 int pad; \ 180 }) \ 181 ) 182 183 #define ADS1015_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \ 184 .type = IIO_VOLTAGE, \ 185 .indexed = 1, \ 186 .address = _addr, \ 187 .channel = _chan, \ 188 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 189 BIT(IIO_CHAN_INFO_SCALE) | \ 190 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 191 .info_mask_shared_by_all_available = \ 192 BIT(IIO_CHAN_INFO_SCALE) | \ 193 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 194 .scan_index = _addr, \ 195 .scan_type = { \ 196 .sign = 's', \ 197 .realbits = (_realbits), \ 198 .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \ 199 .shift = (_shift), \ 200 .endianness = IIO_CPU, \ 201 }, \ 202 .event_spec = (_event_spec), \ 203 .num_event_specs = (_num_event_specs), \ 204 .datasheet_name = "AIN"#_chan, \ 205 } 206 207 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \ 208 .type = IIO_VOLTAGE, \ 209 .differential = 1, \ 210 .indexed = 1, \ 211 .address = _addr, \ 212 .channel = _chan, \ 213 .channel2 = _chan2, \ 214 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 215 BIT(IIO_CHAN_INFO_SCALE) | \ 216 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 217 .info_mask_shared_by_all_available = \ 218 BIT(IIO_CHAN_INFO_SCALE) | \ 219 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 220 .scan_index = _addr, \ 221 .scan_type = { \ 222 .sign = 's', \ 223 .realbits = (_realbits), \ 224 .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \ 225 .shift = (_shift), \ 226 .endianness = IIO_CPU, \ 227 }, \ 228 .event_spec = (_event_spec), \ 229 .num_event_specs = (_num_event_specs), \ 230 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \ 231 } 232 233 struct ads1015_channel_data { 234 bool enabled; 235 unsigned int pga; 236 unsigned int data_rate; 237 }; 238 239 struct ads1015_thresh_data { 240 unsigned int comp_queue; 241 int high_thresh; 242 int low_thresh; 243 }; 244 245 struct ads1015_data { 246 struct regmap *regmap; 247 /* 248 * Protects ADC ops, e.g: concurrent sysfs/buffered 249 * data reads, configuration updates 250 */ 251 struct mutex lock; 252 struct ads1015_channel_data channel_data[ADS1015_CHANNELS]; 253 254 unsigned int event_channel; 255 unsigned int comp_mode; 256 struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS]; 257 258 const struct ads1015_chip_data *chip; 259 /* 260 * Set to true when the ADC is switched to the continuous-conversion 261 * mode and exits from a power-down state. This flag is used to avoid 262 * getting the stale result from the conversion register. 263 */ 264 bool conv_invalid; 265 }; 266 267 static bool ads1015_event_channel_enabled(struct ads1015_data *data) 268 { 269 return (data->event_channel != ADS1015_CHANNELS); 270 } 271 272 static void ads1015_event_channel_enable(struct ads1015_data *data, int chan, 273 int comp_mode) 274 { 275 WARN_ON(ads1015_event_channel_enabled(data)); 276 277 data->event_channel = chan; 278 data->comp_mode = comp_mode; 279 } 280 281 static void ads1015_event_channel_disable(struct ads1015_data *data, int chan) 282 { 283 data->event_channel = ADS1015_CHANNELS; 284 } 285 286 static const struct regmap_range ads1015_writeable_ranges[] = { 287 regmap_reg_range(ADS1015_CFG_REG, ADS1015_HI_THRESH_REG), 288 }; 289 290 static const struct regmap_access_table ads1015_writeable_table = { 291 .yes_ranges = ads1015_writeable_ranges, 292 .n_yes_ranges = ARRAY_SIZE(ads1015_writeable_ranges), 293 }; 294 295 static const struct regmap_config ads1015_regmap_config = { 296 .reg_bits = 8, 297 .val_bits = 16, 298 .max_register = ADS1015_HI_THRESH_REG, 299 .wr_table = &ads1015_writeable_table, 300 }; 301 302 static const struct regmap_range tla2024_writeable_ranges[] = { 303 regmap_reg_range(ADS1015_CFG_REG, ADS1015_CFG_REG), 304 }; 305 306 static const struct regmap_access_table tla2024_writeable_table = { 307 .yes_ranges = tla2024_writeable_ranges, 308 .n_yes_ranges = ARRAY_SIZE(tla2024_writeable_ranges), 309 }; 310 311 static const struct regmap_config tla2024_regmap_config = { 312 .reg_bits = 8, 313 .val_bits = 16, 314 .max_register = ADS1015_CFG_REG, 315 .wr_table = &tla2024_writeable_table, 316 }; 317 318 static const struct iio_chan_spec ads1015_channels[] = { 319 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4, 320 ads1015_events, ARRAY_SIZE(ads1015_events)), 321 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4, 322 ads1015_events, ARRAY_SIZE(ads1015_events)), 323 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4, 324 ads1015_events, ARRAY_SIZE(ads1015_events)), 325 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4, 326 ads1015_events, ARRAY_SIZE(ads1015_events)), 327 ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4, 328 ads1015_events, ARRAY_SIZE(ads1015_events)), 329 ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4, 330 ads1015_events, ARRAY_SIZE(ads1015_events)), 331 ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4, 332 ads1015_events, ARRAY_SIZE(ads1015_events)), 333 ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4, 334 ads1015_events, ARRAY_SIZE(ads1015_events)), 335 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP), 336 }; 337 338 static const struct iio_chan_spec ads1115_channels[] = { 339 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 16, 0, 340 ads1015_events, ARRAY_SIZE(ads1015_events)), 341 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 16, 0, 342 ads1015_events, ARRAY_SIZE(ads1015_events)), 343 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 16, 0, 344 ads1015_events, ARRAY_SIZE(ads1015_events)), 345 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 16, 0, 346 ads1015_events, ARRAY_SIZE(ads1015_events)), 347 ADS1015_V_CHAN(0, ADS1015_AIN0, 16, 0, 348 ads1015_events, ARRAY_SIZE(ads1015_events)), 349 ADS1015_V_CHAN(1, ADS1015_AIN1, 16, 0, 350 ads1015_events, ARRAY_SIZE(ads1015_events)), 351 ADS1015_V_CHAN(2, ADS1015_AIN2, 16, 0, 352 ads1015_events, ARRAY_SIZE(ads1015_events)), 353 ADS1015_V_CHAN(3, ADS1015_AIN3, 16, 0, 354 ads1015_events, ARRAY_SIZE(ads1015_events)), 355 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP), 356 }; 357 358 static const struct iio_chan_spec tla2024_channels[] = { 359 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4, NULL, 0), 360 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4, NULL, 0), 361 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4, NULL, 0), 362 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4, NULL, 0), 363 ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4, NULL, 0), 364 ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4, NULL, 0), 365 ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4, NULL, 0), 366 ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4, NULL, 0), 367 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP), 368 }; 369 370 371 #ifdef CONFIG_PM 372 static int ads1015_set_power_state(struct ads1015_data *data, bool on) 373 { 374 int ret; 375 struct device *dev = regmap_get_device(data->regmap); 376 377 if (on) 378 ret = pm_runtime_resume_and_get(dev); 379 else 380 ret = pm_runtime_put_autosuspend(dev); 381 382 return ret < 0 ? ret : 0; 383 } 384 385 #else /* !CONFIG_PM */ 386 387 static int ads1015_set_power_state(struct ads1015_data *data, bool on) 388 { 389 return 0; 390 } 391 392 #endif /* !CONFIG_PM */ 393 394 static 395 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val) 396 { 397 const int *data_rate = data->chip->data_rate; 398 int ret, pga, dr, dr_old, conv_time; 399 unsigned int old, mask, cfg; 400 401 if (chan < 0 || chan >= ADS1015_CHANNELS) 402 return -EINVAL; 403 404 ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old); 405 if (ret) 406 return ret; 407 408 pga = data->channel_data[chan].pga; 409 dr = data->channel_data[chan].data_rate; 410 mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK | 411 ADS1015_CFG_DR_MASK; 412 cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT | 413 dr << ADS1015_CFG_DR_SHIFT; 414 415 if (ads1015_event_channel_enabled(data)) { 416 mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK; 417 cfg |= data->thresh_data[chan].comp_queue << 418 ADS1015_CFG_COMP_QUE_SHIFT | 419 data->comp_mode << 420 ADS1015_CFG_COMP_MODE_SHIFT; 421 } 422 423 cfg = (old & ~mask) | (cfg & mask); 424 if (old != cfg) { 425 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg); 426 if (ret) 427 return ret; 428 data->conv_invalid = true; 429 } 430 if (data->conv_invalid) { 431 dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT; 432 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr_old]); 433 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr]); 434 conv_time += conv_time / 10; /* 10% internal clock inaccuracy */ 435 usleep_range(conv_time, conv_time + 1); 436 data->conv_invalid = false; 437 } 438 439 return regmap_read(data->regmap, ADS1015_CONV_REG, val); 440 } 441 442 static irqreturn_t ads1015_trigger_handler(int irq, void *p) 443 { 444 struct iio_poll_func *pf = p; 445 struct iio_dev *indio_dev = pf->indio_dev; 446 struct ads1015_data *data = iio_priv(indio_dev); 447 /* Ensure natural alignment of timestamp */ 448 struct { 449 s16 chan; 450 aligned_s64 timestamp; 451 } scan = { }; 452 int chan, ret, res; 453 454 mutex_lock(&data->lock); 455 chan = find_first_bit(indio_dev->active_scan_mask, 456 iio_get_masklength(indio_dev)); 457 ret = ads1015_get_adc_result(data, chan, &res); 458 if (ret < 0) { 459 mutex_unlock(&data->lock); 460 goto err; 461 } 462 463 scan.chan = res; 464 mutex_unlock(&data->lock); 465 466 iio_push_to_buffers_with_ts(indio_dev, &scan, sizeof(scan), 467 iio_get_time_ns(indio_dev)); 468 469 err: 470 iio_trigger_notify_done(indio_dev->trig); 471 472 return IRQ_HANDLED; 473 } 474 475 static int ads1015_set_scale(struct ads1015_data *data, 476 struct iio_chan_spec const *chan, 477 int scale, int uscale) 478 { 479 int i; 480 int fullscale = div_s64((scale * 1000000LL + uscale) << 481 (chan->scan_type.realbits - 1), 1000000); 482 483 for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) { 484 if (ads1015_fullscale_range[i] == fullscale) { 485 data->channel_data[chan->address].pga = i; 486 return 0; 487 } 488 } 489 490 return -EINVAL; 491 } 492 493 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate) 494 { 495 int i; 496 497 for (i = 0; i < data->chip->data_rate_len; i++) { 498 if (data->chip->data_rate[i] == rate) { 499 data->channel_data[chan].data_rate = i; 500 return 0; 501 } 502 } 503 504 return -EINVAL; 505 } 506 507 static int ads1015_read_avail(struct iio_dev *indio_dev, 508 struct iio_chan_spec const *chan, 509 const int **vals, int *type, int *length, 510 long mask) 511 { 512 struct ads1015_data *data = iio_priv(indio_dev); 513 514 if (chan->type != IIO_VOLTAGE) 515 return -EINVAL; 516 517 switch (mask) { 518 case IIO_CHAN_INFO_SCALE: 519 *type = IIO_VAL_FRACTIONAL_LOG2; 520 *vals = data->chip->scale; 521 *length = data->chip->scale_len; 522 return IIO_AVAIL_LIST; 523 case IIO_CHAN_INFO_SAMP_FREQ: 524 *type = IIO_VAL_INT; 525 *vals = data->chip->data_rate; 526 *length = data->chip->data_rate_len; 527 return IIO_AVAIL_LIST; 528 default: 529 return -EINVAL; 530 } 531 } 532 533 static int __ads1015_read_info_raw(struct ads1015_data *data, 534 struct iio_chan_spec const *chan, int *val) 535 { 536 int ret; 537 538 if (ads1015_event_channel_enabled(data) && 539 data->event_channel != chan->address) 540 return -EBUSY; 541 542 ret = ads1015_set_power_state(data, true); 543 if (ret < 0) 544 return ret; 545 546 ret = ads1015_get_adc_result(data, chan->address, val); 547 if (ret < 0) { 548 ads1015_set_power_state(data, false); 549 return ret; 550 } 551 552 *val = sign_extend32(*val >> chan->scan_type.shift, 553 chan->scan_type.realbits - 1); 554 555 return ads1015_set_power_state(data, false); 556 } 557 558 static int ads1015_read_raw(struct iio_dev *indio_dev, 559 struct iio_chan_spec const *chan, int *val, 560 int *val2, long mask) 561 { 562 int ret, idx; 563 struct ads1015_data *data = iio_priv(indio_dev); 564 565 guard(mutex)(&data->lock); 566 switch (mask) { 567 case IIO_CHAN_INFO_RAW: 568 if (!iio_device_claim_direct(indio_dev)) 569 return -EBUSY; 570 ret = __ads1015_read_info_raw(data, chan, val); 571 iio_device_release_direct(indio_dev); 572 if (ret) 573 return ret; 574 575 return IIO_VAL_INT; 576 case IIO_CHAN_INFO_SCALE: 577 idx = data->channel_data[chan->address].pga; 578 *val = ads1015_fullscale_range[idx]; 579 *val2 = chan->scan_type.realbits - 1; 580 return IIO_VAL_FRACTIONAL_LOG2; 581 case IIO_CHAN_INFO_SAMP_FREQ: 582 idx = data->channel_data[chan->address].data_rate; 583 *val = data->chip->data_rate[idx]; 584 return IIO_VAL_INT; 585 default: 586 return -EINVAL; 587 } 588 } 589 590 static int ads1015_write_raw(struct iio_dev *indio_dev, 591 struct iio_chan_spec const *chan, int val, 592 int val2, long mask) 593 { 594 struct ads1015_data *data = iio_priv(indio_dev); 595 596 guard(mutex)(&data->lock); 597 switch (mask) { 598 case IIO_CHAN_INFO_SCALE: 599 return ads1015_set_scale(data, chan, val, val2); 600 case IIO_CHAN_INFO_SAMP_FREQ: 601 return ads1015_set_data_rate(data, chan->address, val); 602 default: 603 return -EINVAL; 604 } 605 } 606 607 static int ads1015_read_event(struct iio_dev *indio_dev, 608 const struct iio_chan_spec *chan, enum iio_event_type type, 609 enum iio_event_direction dir, enum iio_event_info info, int *val, 610 int *val2) 611 { 612 struct ads1015_data *data = iio_priv(indio_dev); 613 unsigned int comp_queue; 614 int period; 615 int dr; 616 617 guard(mutex)(&data->lock); 618 619 switch (info) { 620 case IIO_EV_INFO_VALUE: 621 *val = (dir == IIO_EV_DIR_RISING) ? 622 data->thresh_data[chan->address].high_thresh : 623 data->thresh_data[chan->address].low_thresh; 624 return IIO_VAL_INT; 625 case IIO_EV_INFO_PERIOD: 626 dr = data->channel_data[chan->address].data_rate; 627 comp_queue = data->thresh_data[chan->address].comp_queue; 628 period = ads1015_comp_queue[comp_queue] * 629 USEC_PER_SEC / data->chip->data_rate[dr]; 630 631 *val = period / USEC_PER_SEC; 632 *val2 = period % USEC_PER_SEC; 633 return IIO_VAL_INT_PLUS_MICRO; 634 default: 635 return -EINVAL; 636 } 637 } 638 639 static int ads1015_write_event(struct iio_dev *indio_dev, 640 const struct iio_chan_spec *chan, enum iio_event_type type, 641 enum iio_event_direction dir, enum iio_event_info info, int val, 642 int val2) 643 { 644 struct ads1015_data *data = iio_priv(indio_dev); 645 const int *data_rate = data->chip->data_rate; 646 int realbits = chan->scan_type.realbits; 647 long long period; 648 int i; 649 int dr; 650 651 guard(mutex)(&data->lock); 652 653 switch (info) { 654 case IIO_EV_INFO_VALUE: 655 if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) 656 return -EINVAL; 657 658 if (dir == IIO_EV_DIR_RISING) 659 data->thresh_data[chan->address].high_thresh = val; 660 else 661 data->thresh_data[chan->address].low_thresh = val; 662 return 0; 663 case IIO_EV_INFO_PERIOD: 664 dr = data->channel_data[chan->address].data_rate; 665 period = val * USEC_PER_SEC + val2; 666 667 for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) { 668 if (period <= ads1015_comp_queue[i] * 669 USEC_PER_SEC / data_rate[dr]) 670 break; 671 } 672 data->thresh_data[chan->address].comp_queue = i; 673 return 0; 674 default: 675 return -EINVAL; 676 } 677 } 678 679 static int ads1015_read_event_config(struct iio_dev *indio_dev, 680 const struct iio_chan_spec *chan, enum iio_event_type type, 681 enum iio_event_direction dir) 682 { 683 struct ads1015_data *data = iio_priv(indio_dev); 684 685 guard(mutex)(&data->lock); 686 if (data->event_channel != chan->address) 687 return 0; 688 689 switch (dir) { 690 case IIO_EV_DIR_RISING: 691 return 1; 692 case IIO_EV_DIR_EITHER: 693 return (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW); 694 default: 695 return -EINVAL; 696 } 697 } 698 699 static int ads1015_enable_event_config(struct ads1015_data *data, 700 const struct iio_chan_spec *chan, int comp_mode) 701 { 702 int low_thresh = data->thresh_data[chan->address].low_thresh; 703 int high_thresh = data->thresh_data[chan->address].high_thresh; 704 int ret; 705 unsigned int val; 706 707 if (ads1015_event_channel_enabled(data)) { 708 if (data->event_channel != chan->address || 709 (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD && 710 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)) 711 return -EBUSY; 712 713 return 0; 714 } 715 716 if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) { 717 low_thresh = max(-1 << (chan->scan_type.realbits - 1), 718 high_thresh - 1); 719 } 720 ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG, 721 low_thresh << chan->scan_type.shift); 722 if (ret) 723 return ret; 724 725 ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG, 726 high_thresh << chan->scan_type.shift); 727 if (ret) 728 return ret; 729 730 ret = ads1015_set_power_state(data, true); 731 if (ret < 0) 732 return ret; 733 734 ads1015_event_channel_enable(data, chan->address, comp_mode); 735 736 ret = ads1015_get_adc_result(data, chan->address, &val); 737 if (ret) { 738 ads1015_event_channel_disable(data, chan->address); 739 ads1015_set_power_state(data, false); 740 } 741 742 return ret; 743 } 744 745 static int ads1015_disable_event_config(struct ads1015_data *data, 746 const struct iio_chan_spec *chan, int comp_mode) 747 { 748 int ret; 749 750 if (!ads1015_event_channel_enabled(data)) 751 return 0; 752 753 if (data->event_channel != chan->address) 754 return 0; 755 756 if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD && 757 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW) 758 return 0; 759 760 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG, 761 ADS1015_CFG_COMP_QUE_MASK, 762 ADS1015_CFG_COMP_DISABLE << 763 ADS1015_CFG_COMP_QUE_SHIFT); 764 if (ret) 765 return ret; 766 767 ads1015_event_channel_disable(data, chan->address); 768 769 return ads1015_set_power_state(data, false); 770 } 771 772 static int ads1015_write_event_config(struct iio_dev *indio_dev, 773 const struct iio_chan_spec *chan, enum iio_event_type type, 774 enum iio_event_direction dir, bool state) 775 { 776 struct ads1015_data *data = iio_priv(indio_dev); 777 int ret; 778 int comp_mode = (dir == IIO_EV_DIR_EITHER) ? 779 ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD; 780 781 guard(mutex)(&data->lock); 782 783 /* Prevent from enabling both buffer and event at a time */ 784 if (!iio_device_claim_direct(indio_dev)) 785 return -EBUSY; 786 787 if (state) 788 ret = ads1015_enable_event_config(data, chan, comp_mode); 789 else 790 ret = ads1015_disable_event_config(data, chan, comp_mode); 791 792 iio_device_release_direct(indio_dev); 793 return ret; 794 } 795 796 static irqreturn_t ads1015_event_handler(int irq, void *priv) 797 { 798 struct iio_dev *indio_dev = priv; 799 struct ads1015_data *data = iio_priv(indio_dev); 800 int val; 801 int ret; 802 803 /* Clear the latched ALERT/RDY pin */ 804 ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val); 805 if (ret) 806 return IRQ_HANDLED; 807 808 if (ads1015_event_channel_enabled(data)) { 809 enum iio_event_direction dir; 810 u64 code; 811 812 dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ? 813 IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER; 814 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel, 815 IIO_EV_TYPE_THRESH, dir); 816 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev)); 817 } 818 819 return IRQ_HANDLED; 820 } 821 822 static int ads1015_buffer_preenable(struct iio_dev *indio_dev) 823 { 824 struct ads1015_data *data = iio_priv(indio_dev); 825 826 /* Prevent from enabling both buffer and event at a time */ 827 if (ads1015_event_channel_enabled(data)) 828 return -EBUSY; 829 830 return ads1015_set_power_state(iio_priv(indio_dev), true); 831 } 832 833 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev) 834 { 835 return ads1015_set_power_state(iio_priv(indio_dev), false); 836 } 837 838 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = { 839 .preenable = ads1015_buffer_preenable, 840 .postdisable = ads1015_buffer_postdisable, 841 .validate_scan_mask = &iio_validate_scan_mask_onehot, 842 }; 843 844 static const struct iio_info ads1015_info = { 845 .read_avail = ads1015_read_avail, 846 .read_raw = ads1015_read_raw, 847 .write_raw = ads1015_write_raw, 848 .read_event_value = ads1015_read_event, 849 .write_event_value = ads1015_write_event, 850 .read_event_config = ads1015_read_event_config, 851 .write_event_config = ads1015_write_event_config, 852 }; 853 854 static const struct iio_info tla2024_info = { 855 .read_avail = ads1015_read_avail, 856 .read_raw = ads1015_read_raw, 857 .write_raw = ads1015_write_raw, 858 }; 859 860 static int ads1015_client_get_channels_config(struct i2c_client *client) 861 { 862 struct iio_dev *indio_dev = i2c_get_clientdata(client); 863 struct ads1015_data *data = iio_priv(indio_dev); 864 struct device *dev = &client->dev; 865 int i = -1; 866 867 device_for_each_child_node_scoped(dev, node) { 868 u32 pval; 869 unsigned int channel; 870 unsigned int pga = ADS1015_DEFAULT_PGA; 871 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE; 872 873 if (fwnode_property_read_u32(node, "reg", &pval)) { 874 dev_err(dev, "invalid reg on %pfw\n", node); 875 continue; 876 } 877 878 channel = pval; 879 if (channel >= ADS1015_CHANNELS) { 880 dev_err(dev, "invalid channel index %d on %pfw\n", 881 channel, node); 882 continue; 883 } 884 885 if (!fwnode_property_read_u32(node, "ti,gain", &pval)) { 886 pga = pval; 887 if (pga > 5) { 888 dev_err(dev, "invalid gain on %pfw\n", node); 889 return -EINVAL; 890 } 891 } 892 893 if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) { 894 data_rate = pval; 895 if (data_rate > 7) { 896 dev_err(dev, "invalid data_rate on %pfw\n", node); 897 return -EINVAL; 898 } 899 } 900 901 data->channel_data[channel].pga = pga; 902 data->channel_data[channel].data_rate = data_rate; 903 904 i++; 905 } 906 907 return i < 0 ? -EINVAL : 0; 908 } 909 910 static void ads1015_get_channels_config(struct i2c_client *client) 911 { 912 unsigned int k; 913 914 struct iio_dev *indio_dev = i2c_get_clientdata(client); 915 struct ads1015_data *data = iio_priv(indio_dev); 916 917 if (!ads1015_client_get_channels_config(client)) 918 return; 919 920 /* fallback on default configuration */ 921 for (k = 0; k < ADS1015_CHANNELS; ++k) { 922 data->channel_data[k].pga = ADS1015_DEFAULT_PGA; 923 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE; 924 } 925 } 926 927 static int ads1015_set_conv_mode(struct ads1015_data *data, int mode) 928 { 929 return regmap_update_bits(data->regmap, ADS1015_CFG_REG, 930 ADS1015_CFG_MOD_MASK, 931 mode << ADS1015_CFG_MOD_SHIFT); 932 } 933 934 static int ads1015_probe(struct i2c_client *client) 935 { 936 const struct ads1015_chip_data *chip; 937 struct iio_dev *indio_dev; 938 struct ads1015_data *data; 939 int ret; 940 int i; 941 942 chip = i2c_get_match_data(client); 943 if (!chip) 944 return dev_err_probe(&client->dev, -EINVAL, "Unknown chip\n"); 945 946 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 947 if (!indio_dev) 948 return -ENOMEM; 949 950 data = iio_priv(indio_dev); 951 i2c_set_clientdata(client, indio_dev); 952 953 mutex_init(&data->lock); 954 955 indio_dev->name = ADS1015_DRV_NAME; 956 indio_dev->modes = INDIO_DIRECT_MODE; 957 958 indio_dev->channels = chip->channels; 959 indio_dev->num_channels = chip->num_channels; 960 indio_dev->info = chip->info; 961 data->chip = chip; 962 data->event_channel = ADS1015_CHANNELS; 963 964 /* 965 * Set default lower and upper threshold to min and max value 966 * respectively. 967 */ 968 for (i = 0; i < ADS1015_CHANNELS; i++) { 969 int realbits = indio_dev->channels[i].scan_type.realbits; 970 971 data->thresh_data[i].low_thresh = -1 << (realbits - 1); 972 data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1; 973 } 974 975 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */ 976 ads1015_get_channels_config(client); 977 978 data->regmap = devm_regmap_init_i2c(client, chip->has_comparator ? 979 &ads1015_regmap_config : 980 &tla2024_regmap_config); 981 if (IS_ERR(data->regmap)) { 982 dev_err(&client->dev, "Failed to allocate register map\n"); 983 return PTR_ERR(data->regmap); 984 } 985 986 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL, 987 ads1015_trigger_handler, 988 &ads1015_buffer_setup_ops); 989 if (ret < 0) { 990 dev_err(&client->dev, "iio triggered buffer setup failed\n"); 991 return ret; 992 } 993 994 if (client->irq && chip->has_comparator) { 995 unsigned long irq_trig = irq_get_trigger_type(client->irq); 996 unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK | 997 ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK; 998 unsigned int cfg_comp = 999 ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT | 1000 1 << ADS1015_CFG_COMP_LAT_SHIFT; 1001 1002 switch (irq_trig) { 1003 case IRQF_TRIGGER_FALLING: 1004 case IRQF_TRIGGER_LOW: 1005 cfg_comp |= ADS1015_CFG_COMP_POL_LOW << 1006 ADS1015_CFG_COMP_POL_SHIFT; 1007 break; 1008 case IRQF_TRIGGER_HIGH: 1009 case IRQF_TRIGGER_RISING: 1010 cfg_comp |= ADS1015_CFG_COMP_POL_HIGH << 1011 ADS1015_CFG_COMP_POL_SHIFT; 1012 break; 1013 default: 1014 return -EINVAL; 1015 } 1016 1017 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG, 1018 cfg_comp_mask, cfg_comp); 1019 if (ret) 1020 return ret; 1021 1022 ret = devm_request_threaded_irq(&client->dev, client->irq, 1023 NULL, ads1015_event_handler, 1024 irq_trig | IRQF_ONESHOT, 1025 client->name, indio_dev); 1026 if (ret) 1027 return ret; 1028 } 1029 1030 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS); 1031 if (ret) 1032 return ret; 1033 1034 data->conv_invalid = true; 1035 1036 ret = pm_runtime_set_active(&client->dev); 1037 if (ret) 1038 return ret; 1039 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS); 1040 pm_runtime_use_autosuspend(&client->dev); 1041 pm_runtime_enable(&client->dev); 1042 1043 ret = iio_device_register(indio_dev); 1044 if (ret < 0) { 1045 dev_err(&client->dev, "Failed to register IIO device\n"); 1046 return ret; 1047 } 1048 1049 return 0; 1050 } 1051 1052 static void ads1015_remove(struct i2c_client *client) 1053 { 1054 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1055 struct ads1015_data *data = iio_priv(indio_dev); 1056 int ret; 1057 1058 iio_device_unregister(indio_dev); 1059 1060 pm_runtime_disable(&client->dev); 1061 pm_runtime_set_suspended(&client->dev); 1062 1063 /* power down single shot mode */ 1064 ret = ads1015_set_conv_mode(data, ADS1015_SINGLESHOT); 1065 if (ret) 1066 dev_warn(&client->dev, "Failed to power down (%pe)\n", 1067 ERR_PTR(ret)); 1068 } 1069 1070 #ifdef CONFIG_PM 1071 static int ads1015_runtime_suspend(struct device *dev) 1072 { 1073 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1074 struct ads1015_data *data = iio_priv(indio_dev); 1075 1076 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT); 1077 } 1078 1079 static int ads1015_runtime_resume(struct device *dev) 1080 { 1081 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1082 struct ads1015_data *data = iio_priv(indio_dev); 1083 int ret; 1084 1085 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS); 1086 if (!ret) 1087 data->conv_invalid = true; 1088 1089 return ret; 1090 } 1091 #endif 1092 1093 static const struct dev_pm_ops ads1015_pm_ops = { 1094 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend, 1095 ads1015_runtime_resume, NULL) 1096 }; 1097 1098 static const struct ads1015_chip_data ads1015_data = { 1099 .channels = ads1015_channels, 1100 .num_channels = ARRAY_SIZE(ads1015_channels), 1101 .info = &ads1015_info, 1102 .data_rate = ads1015_data_rate, 1103 .data_rate_len = ARRAY_SIZE(ads1015_data_rate), 1104 .scale = ads1015_scale, 1105 .scale_len = ARRAY_SIZE(ads1015_scale), 1106 .has_comparator = true, 1107 }; 1108 1109 static const struct ads1015_chip_data ads1115_data = { 1110 .channels = ads1115_channels, 1111 .num_channels = ARRAY_SIZE(ads1115_channels), 1112 .info = &ads1015_info, 1113 .data_rate = ads1115_data_rate, 1114 .data_rate_len = ARRAY_SIZE(ads1115_data_rate), 1115 .scale = ads1115_scale, 1116 .scale_len = ARRAY_SIZE(ads1115_scale), 1117 .has_comparator = true, 1118 }; 1119 1120 static const struct ads1015_chip_data tla2024_data = { 1121 .channels = tla2024_channels, 1122 .num_channels = ARRAY_SIZE(tla2024_channels), 1123 .info = &tla2024_info, 1124 .data_rate = ads1015_data_rate, 1125 .data_rate_len = ARRAY_SIZE(ads1015_data_rate), 1126 .scale = ads1015_scale, 1127 .scale_len = ARRAY_SIZE(ads1015_scale), 1128 .has_comparator = false, 1129 }; 1130 1131 static const struct i2c_device_id ads1015_id[] = { 1132 { "ads1015", (kernel_ulong_t)&ads1015_data }, 1133 { "ads1115", (kernel_ulong_t)&ads1115_data }, 1134 { "tla2024", (kernel_ulong_t)&tla2024_data }, 1135 { } 1136 }; 1137 MODULE_DEVICE_TABLE(i2c, ads1015_id); 1138 1139 static const struct of_device_id ads1015_of_match[] = { 1140 { .compatible = "ti,ads1015", .data = &ads1015_data }, 1141 { .compatible = "ti,ads1115", .data = &ads1115_data }, 1142 { .compatible = "ti,tla2024", .data = &tla2024_data }, 1143 { } 1144 }; 1145 MODULE_DEVICE_TABLE(of, ads1015_of_match); 1146 1147 static struct i2c_driver ads1015_driver = { 1148 .driver = { 1149 .name = ADS1015_DRV_NAME, 1150 .of_match_table = ads1015_of_match, 1151 .pm = &ads1015_pm_ops, 1152 }, 1153 .probe = ads1015_probe, 1154 .remove = ads1015_remove, 1155 .id_table = ads1015_id, 1156 }; 1157 1158 module_i2c_driver(ads1015_driver); 1159 1160 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>"); 1161 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver"); 1162 MODULE_LICENSE("GPL v2"); 1163