1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * GPADC driver for sunxi platforms (D1, T113-S3 and R329) 4 * Copyright (c) 2023 Maksim Kiselev <bigunclemax@gmail.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/property.h> 16 #include <linux/reset.h> 17 18 #include <linux/iio/iio.h> 19 20 #define SUN20I_GPADC_DRIVER_NAME "sun20i-gpadc" 21 22 /* Register map definition */ 23 #define SUN20I_GPADC_SR 0x00 24 #define SUN20I_GPADC_CTRL 0x04 25 #define SUN20I_GPADC_CS_EN 0x08 26 #define SUN20I_GPADC_FIFO_INTC 0x0c 27 #define SUN20I_GPADC_FIFO_INTS 0x10 28 #define SUN20I_GPADC_FIFO_DATA 0X14 29 #define SUN20I_GPADC_CB_DATA 0X18 30 #define SUN20I_GPADC_DATAL_INTC 0x20 31 #define SUN20I_GPADC_DATAH_INTC 0x24 32 #define SUN20I_GPADC_DATA_INTC 0x28 33 #define SUN20I_GPADC_DATAL_INTS 0x30 34 #define SUN20I_GPADC_DATAH_INTS 0x34 35 #define SUN20I_GPADC_DATA_INTS 0x38 36 #define SUN20I_GPADC_CH_CMP_DATA(x) (0x40 + (x) * 4) 37 #define SUN20I_GPADC_CH_DATA(x) (0x80 + (x) * 4) 38 39 #define SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK BIT(23) 40 #define SUN20I_GPADC_CTRL_WORK_MODE_MASK GENMASK(19, 18) 41 #define SUN20I_GPADC_CTRL_ADC_EN_MASK BIT(16) 42 #define SUN20I_GPADC_CS_EN_ADC_CH(x) BIT(x) 43 #define SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(x) BIT(x) 44 45 #define SUN20I_GPADC_WORK_MODE_SINGLE 0 46 47 struct sun20i_gpadc_iio { 48 void __iomem *regs; 49 struct completion completion; 50 int last_channel; 51 /* 52 * Lock to protect the device state during a potential concurrent 53 * read access from userspace. Reading a raw value requires a sequence 54 * of register writes, then a wait for a completion callback, 55 * and finally a register read, during which userspace could issue 56 * another read request. This lock protects a read access from 57 * ocurring before another one has finished. 58 */ 59 struct mutex lock; 60 }; 61 62 static int sun20i_gpadc_adc_read(struct sun20i_gpadc_iio *info, 63 struct iio_chan_spec const *chan, int *val) 64 { 65 u32 ctrl; 66 int ret = IIO_VAL_INT; 67 68 mutex_lock(&info->lock); 69 70 reinit_completion(&info->completion); 71 72 if (info->last_channel != chan->channel) { 73 info->last_channel = chan->channel; 74 75 /* enable the analog input channel */ 76 writel(SUN20I_GPADC_CS_EN_ADC_CH(chan->channel), 77 info->regs + SUN20I_GPADC_CS_EN); 78 79 /* enable the data irq for input channel */ 80 writel(SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(chan->channel), 81 info->regs + SUN20I_GPADC_DATA_INTC); 82 } 83 84 /* enable the ADC function */ 85 ctrl = readl(info->regs + SUN20I_GPADC_CTRL); 86 ctrl |= FIELD_PREP(SUN20I_GPADC_CTRL_ADC_EN_MASK, 1); 87 writel(ctrl, info->regs + SUN20I_GPADC_CTRL); 88 89 /* 90 * According to the datasheet maximum acquire time(TACQ) can be 91 * (65535+1)/24Mhz and conversion time(CONV_TIME) is always constant 92 * and equal to 14/24Mhz, so (TACQ+CONV_TIME) <= 2.73125ms. 93 * A 10ms delay should be enough to make sure an interrupt occurs in 94 * normal conditions. If it doesn't occur, then there is a timeout. 95 */ 96 if (!wait_for_completion_timeout(&info->completion, msecs_to_jiffies(10))) { 97 ret = -ETIMEDOUT; 98 goto err_unlock; 99 } 100 101 /* read the ADC data */ 102 *val = readl(info->regs + SUN20I_GPADC_CH_DATA(chan->channel)); 103 104 err_unlock: 105 mutex_unlock(&info->lock); 106 107 return ret; 108 } 109 110 static int sun20i_gpadc_read_raw(struct iio_dev *indio_dev, 111 struct iio_chan_spec const *chan, int *val, 112 int *val2, long mask) 113 { 114 struct sun20i_gpadc_iio *info = iio_priv(indio_dev); 115 116 switch (mask) { 117 case IIO_CHAN_INFO_RAW: 118 return sun20i_gpadc_adc_read(info, chan, val); 119 case IIO_CHAN_INFO_SCALE: 120 /* value in mv = 1800mV / 4096 raw */ 121 *val = 1800; 122 *val2 = 12; 123 return IIO_VAL_FRACTIONAL_LOG2; 124 default: 125 return -EINVAL; 126 } 127 } 128 129 static irqreturn_t sun20i_gpadc_irq_handler(int irq, void *data) 130 { 131 struct sun20i_gpadc_iio *info = data; 132 133 /* clear data interrupt status register */ 134 writel(GENMASK(31, 0), info->regs + SUN20I_GPADC_DATA_INTS); 135 136 complete(&info->completion); 137 138 return IRQ_HANDLED; 139 } 140 141 static const struct iio_info sun20i_gpadc_iio_info = { 142 .read_raw = sun20i_gpadc_read_raw, 143 }; 144 145 static void sun20i_gpadc_reset_assert(void *data) 146 { 147 struct reset_control *rst = data; 148 149 reset_control_assert(rst); 150 } 151 152 static int sun20i_gpadc_alloc_channels(struct iio_dev *indio_dev, 153 struct device *dev) 154 { 155 unsigned int channel; 156 int num_channels, i, ret; 157 struct iio_chan_spec *channels; 158 159 num_channels = device_get_child_node_count(dev); 160 if (num_channels == 0) 161 return dev_err_probe(dev, -ENODEV, "no channel children\n"); 162 163 channels = devm_kcalloc(dev, num_channels, sizeof(*channels), 164 GFP_KERNEL); 165 if (!channels) 166 return -ENOMEM; 167 168 i = 0; 169 device_for_each_child_node_scoped(dev, node) { 170 ret = fwnode_property_read_u32(node, "reg", &channel); 171 if (ret) 172 return dev_err_probe(dev, ret, "invalid channel number\n"); 173 174 channels[i].type = IIO_VOLTAGE; 175 channels[i].indexed = 1; 176 channels[i].channel = channel; 177 channels[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 178 channels[i].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 179 180 i++; 181 } 182 183 indio_dev->channels = channels; 184 indio_dev->num_channels = num_channels; 185 186 return 0; 187 } 188 189 static int sun20i_gpadc_probe(struct platform_device *pdev) 190 { 191 struct device *dev = &pdev->dev; 192 struct iio_dev *indio_dev; 193 struct sun20i_gpadc_iio *info; 194 struct reset_control *rst; 195 struct clk *clk; 196 int irq; 197 int ret; 198 199 indio_dev = devm_iio_device_alloc(dev, sizeof(*info)); 200 if (!indio_dev) 201 return -ENOMEM; 202 203 info = iio_priv(indio_dev); 204 info->last_channel = -1; 205 206 mutex_init(&info->lock); 207 init_completion(&info->completion); 208 209 ret = sun20i_gpadc_alloc_channels(indio_dev, dev); 210 if (ret) 211 return ret; 212 213 indio_dev->info = &sun20i_gpadc_iio_info; 214 indio_dev->name = SUN20I_GPADC_DRIVER_NAME; 215 216 info->regs = devm_platform_ioremap_resource(pdev, 0); 217 if (IS_ERR(info->regs)) 218 return PTR_ERR(info->regs); 219 220 clk = devm_clk_get_enabled(dev, NULL); 221 if (IS_ERR(clk)) 222 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock\n"); 223 224 rst = devm_reset_control_get_exclusive(dev, NULL); 225 if (IS_ERR(rst)) 226 return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n"); 227 228 ret = reset_control_deassert(rst); 229 if (ret) 230 return dev_err_probe(dev, ret, "failed to deassert reset\n"); 231 232 ret = devm_add_action_or_reset(dev, sun20i_gpadc_reset_assert, rst); 233 if (ret) 234 return ret; 235 236 irq = platform_get_irq(pdev, 0); 237 if (irq < 0) 238 return irq; 239 240 ret = devm_request_irq(dev, irq, sun20i_gpadc_irq_handler, 0, 241 dev_name(dev), info); 242 if (ret) 243 return dev_err_probe(dev, ret, "failed requesting irq %d\n", irq); 244 245 writel(FIELD_PREP(SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK, 1) | 246 FIELD_PREP(SUN20I_GPADC_CTRL_WORK_MODE_MASK, SUN20I_GPADC_WORK_MODE_SINGLE), 247 info->regs + SUN20I_GPADC_CTRL); 248 249 ret = devm_iio_device_register(dev, indio_dev); 250 if (ret) 251 return dev_err_probe(dev, ret, "could not register the device\n"); 252 253 return 0; 254 } 255 256 static const struct of_device_id sun20i_gpadc_of_id[] = { 257 { .compatible = "allwinner,sun20i-d1-gpadc" }, 258 { /* sentinel */ } 259 }; 260 MODULE_DEVICE_TABLE(of, sun20i_gpadc_of_id); 261 262 static struct platform_driver sun20i_gpadc_driver = { 263 .driver = { 264 .name = SUN20I_GPADC_DRIVER_NAME, 265 .of_match_table = sun20i_gpadc_of_id, 266 }, 267 .probe = sun20i_gpadc_probe, 268 }; 269 module_platform_driver(sun20i_gpadc_driver); 270 271 MODULE_DESCRIPTION("ADC driver for sunxi platforms"); 272 MODULE_AUTHOR("Maksim Kiselev <bigunclemax@gmail.com>"); 273 MODULE_LICENSE("GPL"); 274