xref: /linux/drivers/iio/adc/stm32-adc.c (revision 25a85bed36f7da4e411f8744c2962e4e1003d7ea)
10f883b22SFabrice Gasnier /*
20f883b22SFabrice Gasnier  * This file is part of STM32 ADC driver
30f883b22SFabrice Gasnier  *
40f883b22SFabrice Gasnier  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
50f883b22SFabrice Gasnier  * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
60f883b22SFabrice Gasnier  *
70f883b22SFabrice Gasnier  * License type: GPLv2
80f883b22SFabrice Gasnier  *
90f883b22SFabrice Gasnier  * This program is free software; you can redistribute it and/or modify it
100f883b22SFabrice Gasnier  * under the terms of the GNU General Public License version 2 as published by
110f883b22SFabrice Gasnier  * the Free Software Foundation.
120f883b22SFabrice Gasnier  *
130f883b22SFabrice Gasnier  * This program is distributed in the hope that it will be useful, but
140f883b22SFabrice Gasnier  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
150f883b22SFabrice Gasnier  * or FITNESS FOR A PARTICULAR PURPOSE.
160f883b22SFabrice Gasnier  * See the GNU General Public License for more details.
170f883b22SFabrice Gasnier  *
180f883b22SFabrice Gasnier  * You should have received a copy of the GNU General Public License along with
190f883b22SFabrice Gasnier  * this program. If not, see <http://www.gnu.org/licenses/>.
200f883b22SFabrice Gasnier  */
210f883b22SFabrice Gasnier 
220f883b22SFabrice Gasnier #include <linux/clk.h>
230f883b22SFabrice Gasnier #include <linux/delay.h>
242763ea05SFabrice Gasnier #include <linux/dma-mapping.h>
252763ea05SFabrice Gasnier #include <linux/dmaengine.h>
260f883b22SFabrice Gasnier #include <linux/iio/iio.h>
27da9b9485SFabrice Gasnier #include <linux/iio/buffer.h>
28f24a33b3SFabrice Gasnier #include <linux/iio/timer/stm32-timer-trigger.h>
29da9b9485SFabrice Gasnier #include <linux/iio/trigger.h>
30da9b9485SFabrice Gasnier #include <linux/iio/trigger_consumer.h>
31da9b9485SFabrice Gasnier #include <linux/iio/triggered_buffer.h>
320f883b22SFabrice Gasnier #include <linux/interrupt.h>
330f883b22SFabrice Gasnier #include <linux/io.h>
340f883b22SFabrice Gasnier #include <linux/module.h>
350f883b22SFabrice Gasnier #include <linux/platform_device.h>
360f883b22SFabrice Gasnier #include <linux/of.h>
370f883b22SFabrice Gasnier 
380f883b22SFabrice Gasnier #include "stm32-adc-core.h"
390f883b22SFabrice Gasnier 
400f883b22SFabrice Gasnier /* STM32F4 - Registers for each ADC instance */
410f883b22SFabrice Gasnier #define STM32F4_ADC_SR			0x00
420f883b22SFabrice Gasnier #define STM32F4_ADC_CR1			0x04
430f883b22SFabrice Gasnier #define STM32F4_ADC_CR2			0x08
440f883b22SFabrice Gasnier #define STM32F4_ADC_SMPR1		0x0C
450f883b22SFabrice Gasnier #define STM32F4_ADC_SMPR2		0x10
460f883b22SFabrice Gasnier #define STM32F4_ADC_HTR			0x24
470f883b22SFabrice Gasnier #define STM32F4_ADC_LTR			0x28
480f883b22SFabrice Gasnier #define STM32F4_ADC_SQR1		0x2C
490f883b22SFabrice Gasnier #define STM32F4_ADC_SQR2		0x30
500f883b22SFabrice Gasnier #define STM32F4_ADC_SQR3		0x34
510f883b22SFabrice Gasnier #define STM32F4_ADC_JSQR		0x38
520f883b22SFabrice Gasnier #define STM32F4_ADC_JDR1		0x3C
530f883b22SFabrice Gasnier #define STM32F4_ADC_JDR2		0x40
540f883b22SFabrice Gasnier #define STM32F4_ADC_JDR3		0x44
550f883b22SFabrice Gasnier #define STM32F4_ADC_JDR4		0x48
560f883b22SFabrice Gasnier #define STM32F4_ADC_DR			0x4C
570f883b22SFabrice Gasnier 
580f883b22SFabrice Gasnier /* STM32F4_ADC_SR - bit fields */
590f883b22SFabrice Gasnier #define STM32F4_STRT			BIT(4)
600f883b22SFabrice Gasnier #define STM32F4_EOC			BIT(1)
610f883b22SFabrice Gasnier 
620f883b22SFabrice Gasnier /* STM32F4_ADC_CR1 - bit fields */
63*25a85bedSFabrice Gasnier #define STM32F4_RES_SHIFT		24
64*25a85bedSFabrice Gasnier #define STM32F4_RES_MASK		GENMASK(25, 24)
650f883b22SFabrice Gasnier #define STM32F4_SCAN			BIT(8)
660f883b22SFabrice Gasnier #define STM32F4_EOCIE			BIT(5)
670f883b22SFabrice Gasnier 
680f883b22SFabrice Gasnier /* STM32F4_ADC_CR2 - bit fields */
690f883b22SFabrice Gasnier #define STM32F4_SWSTART			BIT(30)
70da9b9485SFabrice Gasnier #define STM32F4_EXTEN_SHIFT		28
710f883b22SFabrice Gasnier #define STM32F4_EXTEN_MASK		GENMASK(29, 28)
72da9b9485SFabrice Gasnier #define STM32F4_EXTSEL_SHIFT		24
73da9b9485SFabrice Gasnier #define STM32F4_EXTSEL_MASK		GENMASK(27, 24)
740f883b22SFabrice Gasnier #define STM32F4_EOCS			BIT(10)
752763ea05SFabrice Gasnier #define STM32F4_DDS			BIT(9)
762763ea05SFabrice Gasnier #define STM32F4_DMA			BIT(8)
770f883b22SFabrice Gasnier #define STM32F4_ADON			BIT(0)
780f883b22SFabrice Gasnier 
79da9b9485SFabrice Gasnier #define STM32_ADC_MAX_SQ		16	/* SQ1..SQ16 */
800f883b22SFabrice Gasnier #define STM32_ADC_TIMEOUT_US		100000
810f883b22SFabrice Gasnier #define STM32_ADC_TIMEOUT	(msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
820f883b22SFabrice Gasnier 
832763ea05SFabrice Gasnier #define STM32_DMA_BUFFER_SIZE		PAGE_SIZE
842763ea05SFabrice Gasnier 
85da9b9485SFabrice Gasnier /* External trigger enable */
86da9b9485SFabrice Gasnier enum stm32_adc_exten {
87da9b9485SFabrice Gasnier 	STM32_EXTEN_SWTRIG,
88da9b9485SFabrice Gasnier 	STM32_EXTEN_HWTRIG_RISING_EDGE,
89da9b9485SFabrice Gasnier 	STM32_EXTEN_HWTRIG_FALLING_EDGE,
90da9b9485SFabrice Gasnier 	STM32_EXTEN_HWTRIG_BOTH_EDGES,
91da9b9485SFabrice Gasnier };
92da9b9485SFabrice Gasnier 
93f24a33b3SFabrice Gasnier /* extsel - trigger mux selection value */
94f24a33b3SFabrice Gasnier enum stm32_adc_extsel {
95f24a33b3SFabrice Gasnier 	STM32_EXT0,
96f24a33b3SFabrice Gasnier 	STM32_EXT1,
97f24a33b3SFabrice Gasnier 	STM32_EXT2,
98f24a33b3SFabrice Gasnier 	STM32_EXT3,
99f24a33b3SFabrice Gasnier 	STM32_EXT4,
100f24a33b3SFabrice Gasnier 	STM32_EXT5,
101f24a33b3SFabrice Gasnier 	STM32_EXT6,
102f24a33b3SFabrice Gasnier 	STM32_EXT7,
103f24a33b3SFabrice Gasnier 	STM32_EXT8,
104f24a33b3SFabrice Gasnier 	STM32_EXT9,
105f24a33b3SFabrice Gasnier 	STM32_EXT10,
106f24a33b3SFabrice Gasnier 	STM32_EXT11,
107f24a33b3SFabrice Gasnier 	STM32_EXT12,
108f24a33b3SFabrice Gasnier 	STM32_EXT13,
109f24a33b3SFabrice Gasnier 	STM32_EXT14,
110f24a33b3SFabrice Gasnier 	STM32_EXT15,
111f24a33b3SFabrice Gasnier };
112f24a33b3SFabrice Gasnier 
113f24a33b3SFabrice Gasnier /**
114f24a33b3SFabrice Gasnier  * struct stm32_adc_trig_info - ADC trigger info
115f24a33b3SFabrice Gasnier  * @name:		name of the trigger, corresponding to its source
116f24a33b3SFabrice Gasnier  * @extsel:		trigger selection
117f24a33b3SFabrice Gasnier  */
118f24a33b3SFabrice Gasnier struct stm32_adc_trig_info {
119f24a33b3SFabrice Gasnier 	const char *name;
120f24a33b3SFabrice Gasnier 	enum stm32_adc_extsel extsel;
121f24a33b3SFabrice Gasnier };
122f24a33b3SFabrice Gasnier 
123da9b9485SFabrice Gasnier /**
124da9b9485SFabrice Gasnier  * stm32_adc_regs - stm32 ADC misc registers & bitfield desc
125da9b9485SFabrice Gasnier  * @reg:		register offset
126da9b9485SFabrice Gasnier  * @mask:		bitfield mask
127da9b9485SFabrice Gasnier  * @shift:		left shift
128da9b9485SFabrice Gasnier  */
129da9b9485SFabrice Gasnier struct stm32_adc_regs {
130da9b9485SFabrice Gasnier 	int reg;
131da9b9485SFabrice Gasnier 	int mask;
132da9b9485SFabrice Gasnier 	int shift;
133da9b9485SFabrice Gasnier };
134da9b9485SFabrice Gasnier 
1350f883b22SFabrice Gasnier /**
1360f883b22SFabrice Gasnier  * struct stm32_adc - private data of each ADC IIO instance
1370f883b22SFabrice Gasnier  * @common:		reference to ADC block common data
1380f883b22SFabrice Gasnier  * @offset:		ADC instance register offset in ADC block
1390f883b22SFabrice Gasnier  * @completion:		end of single conversion completion
1400f883b22SFabrice Gasnier  * @buffer:		data buffer
1410f883b22SFabrice Gasnier  * @clk:		clock for this adc instance
1420f883b22SFabrice Gasnier  * @irq:		interrupt for this adc instance
1430f883b22SFabrice Gasnier  * @lock:		spinlock
144da9b9485SFabrice Gasnier  * @bufi:		data buffer index
145da9b9485SFabrice Gasnier  * @num_conv:		expected number of scan conversions
146*25a85bedSFabrice Gasnier  * @res:		data resolution (e.g. RES bitfield value)
147732f2dc4SFabrice Gasnier  * @trigger_polarity:	external trigger polarity (e.g. exten)
1482763ea05SFabrice Gasnier  * @dma_chan:		dma channel
1492763ea05SFabrice Gasnier  * @rx_buf:		dma rx buffer cpu address
1502763ea05SFabrice Gasnier  * @rx_dma_buf:		dma rx buffer bus address
1512763ea05SFabrice Gasnier  * @rx_buf_sz:		dma rx buffer size
1520f883b22SFabrice Gasnier  */
1530f883b22SFabrice Gasnier struct stm32_adc {
1540f883b22SFabrice Gasnier 	struct stm32_adc_common	*common;
1550f883b22SFabrice Gasnier 	u32			offset;
1560f883b22SFabrice Gasnier 	struct completion	completion;
157da9b9485SFabrice Gasnier 	u16			buffer[STM32_ADC_MAX_SQ];
1580f883b22SFabrice Gasnier 	struct clk		*clk;
1590f883b22SFabrice Gasnier 	int			irq;
1600f883b22SFabrice Gasnier 	spinlock_t		lock;		/* interrupt lock */
161da9b9485SFabrice Gasnier 	unsigned int		bufi;
162da9b9485SFabrice Gasnier 	unsigned int		num_conv;
163*25a85bedSFabrice Gasnier 	u32			res;
164732f2dc4SFabrice Gasnier 	u32			trigger_polarity;
1652763ea05SFabrice Gasnier 	struct dma_chan		*dma_chan;
1662763ea05SFabrice Gasnier 	u8			*rx_buf;
1672763ea05SFabrice Gasnier 	dma_addr_t		rx_dma_buf;
1682763ea05SFabrice Gasnier 	unsigned int		rx_buf_sz;
1690f883b22SFabrice Gasnier };
1700f883b22SFabrice Gasnier 
1710f883b22SFabrice Gasnier /**
1720f883b22SFabrice Gasnier  * struct stm32_adc_chan_spec - specification of stm32 adc channel
1730f883b22SFabrice Gasnier  * @type:	IIO channel type
1740f883b22SFabrice Gasnier  * @channel:	channel number (single ended)
1750f883b22SFabrice Gasnier  * @name:	channel name (single ended)
1760f883b22SFabrice Gasnier  */
1770f883b22SFabrice Gasnier struct stm32_adc_chan_spec {
1780f883b22SFabrice Gasnier 	enum iio_chan_type	type;
1790f883b22SFabrice Gasnier 	int			channel;
1800f883b22SFabrice Gasnier 	const char		*name;
1810f883b22SFabrice Gasnier };
1820f883b22SFabrice Gasnier 
1830f883b22SFabrice Gasnier /* Input definitions common for all STM32F4 instances */
1840f883b22SFabrice Gasnier static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = {
1850f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 0, "in0" },
1860f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 1, "in1" },
1870f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 2, "in2" },
1880f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 3, "in3" },
1890f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 4, "in4" },
1900f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 5, "in5" },
1910f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 6, "in6" },
1920f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 7, "in7" },
1930f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 8, "in8" },
1940f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 9, "in9" },
1950f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 10, "in10" },
1960f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 11, "in11" },
1970f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 12, "in12" },
1980f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 13, "in13" },
1990f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 14, "in14" },
2000f883b22SFabrice Gasnier 	{ IIO_VOLTAGE, 15, "in15" },
2010f883b22SFabrice Gasnier };
2020f883b22SFabrice Gasnier 
203*25a85bedSFabrice Gasnier static const unsigned int stm32f4_adc_resolutions[] = {
204*25a85bedSFabrice Gasnier 	/* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */
205*25a85bedSFabrice Gasnier 	12, 10, 8, 6,
206*25a85bedSFabrice Gasnier };
207*25a85bedSFabrice Gasnier 
2080f883b22SFabrice Gasnier /**
209da9b9485SFabrice Gasnier  * stm32f4_sq - describe regular sequence registers
210da9b9485SFabrice Gasnier  * - L: sequence len (register & bit field)
211da9b9485SFabrice Gasnier  * - SQ1..SQ16: sequence entries (register & bit field)
212da9b9485SFabrice Gasnier  */
213da9b9485SFabrice Gasnier static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = {
214da9b9485SFabrice Gasnier 	/* L: len bit field description to be kept as first element */
215da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR1, GENMASK(23, 20), 20 },
216da9b9485SFabrice Gasnier 	/* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
217da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR3, GENMASK(4, 0), 0 },
218da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR3, GENMASK(9, 5), 5 },
219da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR3, GENMASK(14, 10), 10 },
220da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR3, GENMASK(19, 15), 15 },
221da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR3, GENMASK(24, 20), 20 },
222da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR3, GENMASK(29, 25), 25 },
223da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR2, GENMASK(4, 0), 0 },
224da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR2, GENMASK(9, 5), 5 },
225da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR2, GENMASK(14, 10), 10 },
226da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR2, GENMASK(19, 15), 15 },
227da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR2, GENMASK(24, 20), 20 },
228da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR2, GENMASK(29, 25), 25 },
229da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR1, GENMASK(4, 0), 0 },
230da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR1, GENMASK(9, 5), 5 },
231da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR1, GENMASK(14, 10), 10 },
232da9b9485SFabrice Gasnier 	{ STM32F4_ADC_SQR1, GENMASK(19, 15), 15 },
233da9b9485SFabrice Gasnier };
234da9b9485SFabrice Gasnier 
235f24a33b3SFabrice Gasnier /* STM32F4 external trigger sources for all instances */
236f24a33b3SFabrice Gasnier static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
237f24a33b3SFabrice Gasnier 	{ TIM1_CH1, STM32_EXT0 },
238f24a33b3SFabrice Gasnier 	{ TIM1_CH2, STM32_EXT1 },
239f24a33b3SFabrice Gasnier 	{ TIM1_CH3, STM32_EXT2 },
240f24a33b3SFabrice Gasnier 	{ TIM2_CH2, STM32_EXT3 },
241f24a33b3SFabrice Gasnier 	{ TIM2_CH3, STM32_EXT4 },
242f24a33b3SFabrice Gasnier 	{ TIM2_CH4, STM32_EXT5 },
243f24a33b3SFabrice Gasnier 	{ TIM2_TRGO, STM32_EXT6 },
244f24a33b3SFabrice Gasnier 	{ TIM3_CH1, STM32_EXT7 },
245f24a33b3SFabrice Gasnier 	{ TIM3_TRGO, STM32_EXT8 },
246f24a33b3SFabrice Gasnier 	{ TIM4_CH4, STM32_EXT9 },
247f24a33b3SFabrice Gasnier 	{ TIM5_CH1, STM32_EXT10 },
248f24a33b3SFabrice Gasnier 	{ TIM5_CH2, STM32_EXT11 },
249f24a33b3SFabrice Gasnier 	{ TIM5_CH3, STM32_EXT12 },
250f24a33b3SFabrice Gasnier 	{ TIM8_CH1, STM32_EXT13 },
251f24a33b3SFabrice Gasnier 	{ TIM8_TRGO, STM32_EXT14 },
252f24a33b3SFabrice Gasnier 	{}, /* sentinel */
253f24a33b3SFabrice Gasnier };
254f24a33b3SFabrice Gasnier 
255da9b9485SFabrice Gasnier /**
2560f883b22SFabrice Gasnier  * STM32 ADC registers access routines
2570f883b22SFabrice Gasnier  * @adc: stm32 adc instance
2580f883b22SFabrice Gasnier  * @reg: reg offset in adc instance
2590f883b22SFabrice Gasnier  *
2600f883b22SFabrice Gasnier  * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
2610f883b22SFabrice Gasnier  * for adc1, adc2 and adc3.
2620f883b22SFabrice Gasnier  */
2630f883b22SFabrice Gasnier static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
2640f883b22SFabrice Gasnier {
2650f883b22SFabrice Gasnier 	return readl_relaxed(adc->common->base + adc->offset + reg);
2660f883b22SFabrice Gasnier }
2670f883b22SFabrice Gasnier 
2680f883b22SFabrice Gasnier static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
2690f883b22SFabrice Gasnier {
2700f883b22SFabrice Gasnier 	return readw_relaxed(adc->common->base + adc->offset + reg);
2710f883b22SFabrice Gasnier }
2720f883b22SFabrice Gasnier 
2730f883b22SFabrice Gasnier static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
2740f883b22SFabrice Gasnier {
2750f883b22SFabrice Gasnier 	writel_relaxed(val, adc->common->base + adc->offset + reg);
2760f883b22SFabrice Gasnier }
2770f883b22SFabrice Gasnier 
2780f883b22SFabrice Gasnier static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
2790f883b22SFabrice Gasnier {
2800f883b22SFabrice Gasnier 	unsigned long flags;
2810f883b22SFabrice Gasnier 
2820f883b22SFabrice Gasnier 	spin_lock_irqsave(&adc->lock, flags);
2830f883b22SFabrice Gasnier 	stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
2840f883b22SFabrice Gasnier 	spin_unlock_irqrestore(&adc->lock, flags);
2850f883b22SFabrice Gasnier }
2860f883b22SFabrice Gasnier 
2870f883b22SFabrice Gasnier static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
2880f883b22SFabrice Gasnier {
2890f883b22SFabrice Gasnier 	unsigned long flags;
2900f883b22SFabrice Gasnier 
2910f883b22SFabrice Gasnier 	spin_lock_irqsave(&adc->lock, flags);
2920f883b22SFabrice Gasnier 	stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
2930f883b22SFabrice Gasnier 	spin_unlock_irqrestore(&adc->lock, flags);
2940f883b22SFabrice Gasnier }
2950f883b22SFabrice Gasnier 
2960f883b22SFabrice Gasnier /**
2970f883b22SFabrice Gasnier  * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
2980f883b22SFabrice Gasnier  * @adc: stm32 adc instance
2990f883b22SFabrice Gasnier  */
3000f883b22SFabrice Gasnier static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
3010f883b22SFabrice Gasnier {
3020f883b22SFabrice Gasnier 	stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
3030f883b22SFabrice Gasnier };
3040f883b22SFabrice Gasnier 
3050f883b22SFabrice Gasnier /**
3060f883b22SFabrice Gasnier  * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
3070f883b22SFabrice Gasnier  * @adc: stm32 adc instance
3080f883b22SFabrice Gasnier  */
3090f883b22SFabrice Gasnier static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
3100f883b22SFabrice Gasnier {
3110f883b22SFabrice Gasnier 	stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE);
3120f883b22SFabrice Gasnier }
3130f883b22SFabrice Gasnier 
314*25a85bedSFabrice Gasnier static void stm32_adc_set_res(struct stm32_adc *adc)
315*25a85bedSFabrice Gasnier {
316*25a85bedSFabrice Gasnier 	u32 val = stm32_adc_readl(adc, STM32F4_ADC_CR1);
317*25a85bedSFabrice Gasnier 
318*25a85bedSFabrice Gasnier 	val = (val & ~STM32F4_RES_MASK) | (adc->res << STM32F4_RES_SHIFT);
319*25a85bedSFabrice Gasnier 	stm32_adc_writel(adc, STM32F4_ADC_CR1, val);
320*25a85bedSFabrice Gasnier }
321*25a85bedSFabrice Gasnier 
3220f883b22SFabrice Gasnier /**
3230f883b22SFabrice Gasnier  * stm32_adc_start_conv() - Start conversions for regular channels.
3240f883b22SFabrice Gasnier  * @adc: stm32 adc instance
3252763ea05SFabrice Gasnier  * @dma: use dma to transfer conversion result
3262763ea05SFabrice Gasnier  *
3272763ea05SFabrice Gasnier  * Start conversions for regular channels.
3282763ea05SFabrice Gasnier  * Also take care of normal or DMA mode. Circular DMA may be used for regular
3292763ea05SFabrice Gasnier  * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
3302763ea05SFabrice Gasnier  * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
3310f883b22SFabrice Gasnier  */
3322763ea05SFabrice Gasnier static void stm32_adc_start_conv(struct stm32_adc *adc, bool dma)
3330f883b22SFabrice Gasnier {
3340f883b22SFabrice Gasnier 	stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
3352763ea05SFabrice Gasnier 
3362763ea05SFabrice Gasnier 	if (dma)
3372763ea05SFabrice Gasnier 		stm32_adc_set_bits(adc, STM32F4_ADC_CR2,
3382763ea05SFabrice Gasnier 				   STM32F4_DMA | STM32F4_DDS);
3392763ea05SFabrice Gasnier 
3400f883b22SFabrice Gasnier 	stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
3410f883b22SFabrice Gasnier 
3420f883b22SFabrice Gasnier 	/* Wait for Power-up time (tSTAB from datasheet) */
3430f883b22SFabrice Gasnier 	usleep_range(2, 3);
3440f883b22SFabrice Gasnier 
3450f883b22SFabrice Gasnier 	/* Software start ? (e.g. trigger detection disabled ?) */
3460f883b22SFabrice Gasnier 	if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
3470f883b22SFabrice Gasnier 		stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
3480f883b22SFabrice Gasnier }
3490f883b22SFabrice Gasnier 
3500f883b22SFabrice Gasnier static void stm32_adc_stop_conv(struct stm32_adc *adc)
3510f883b22SFabrice Gasnier {
3520f883b22SFabrice Gasnier 	stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
3530f883b22SFabrice Gasnier 	stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
3540f883b22SFabrice Gasnier 
3550f883b22SFabrice Gasnier 	stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
3562763ea05SFabrice Gasnier 	stm32_adc_clr_bits(adc, STM32F4_ADC_CR2,
3572763ea05SFabrice Gasnier 			   STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
3580f883b22SFabrice Gasnier }
3590f883b22SFabrice Gasnier 
3600f883b22SFabrice Gasnier /**
361da9b9485SFabrice Gasnier  * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
362da9b9485SFabrice Gasnier  * @indio_dev: IIO device
363da9b9485SFabrice Gasnier  * @scan_mask: channels to be converted
364da9b9485SFabrice Gasnier  *
365da9b9485SFabrice Gasnier  * Conversion sequence :
366da9b9485SFabrice Gasnier  * Configure ADC scan sequence based on selected channels in scan_mask.
367da9b9485SFabrice Gasnier  * Add channels to SQR registers, from scan_mask LSB to MSB, then
368da9b9485SFabrice Gasnier  * program sequence len.
369da9b9485SFabrice Gasnier  */
370da9b9485SFabrice Gasnier static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
371da9b9485SFabrice Gasnier 				   const unsigned long *scan_mask)
372da9b9485SFabrice Gasnier {
373da9b9485SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
374da9b9485SFabrice Gasnier 	const struct iio_chan_spec *chan;
375da9b9485SFabrice Gasnier 	u32 val, bit;
376da9b9485SFabrice Gasnier 	int i = 0;
377da9b9485SFabrice Gasnier 
378da9b9485SFabrice Gasnier 	for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
379da9b9485SFabrice Gasnier 		chan = indio_dev->channels + bit;
380da9b9485SFabrice Gasnier 		/*
381da9b9485SFabrice Gasnier 		 * Assign one channel per SQ entry in regular
382da9b9485SFabrice Gasnier 		 * sequence, starting with SQ1.
383da9b9485SFabrice Gasnier 		 */
384da9b9485SFabrice Gasnier 		i++;
385da9b9485SFabrice Gasnier 		if (i > STM32_ADC_MAX_SQ)
386da9b9485SFabrice Gasnier 			return -EINVAL;
387da9b9485SFabrice Gasnier 
388da9b9485SFabrice Gasnier 		dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",
389da9b9485SFabrice Gasnier 			__func__, chan->channel, i);
390da9b9485SFabrice Gasnier 
391da9b9485SFabrice Gasnier 		val = stm32_adc_readl(adc, stm32f4_sq[i].reg);
392da9b9485SFabrice Gasnier 		val &= ~stm32f4_sq[i].mask;
393da9b9485SFabrice Gasnier 		val |= chan->channel << stm32f4_sq[i].shift;
394da9b9485SFabrice Gasnier 		stm32_adc_writel(adc, stm32f4_sq[i].reg, val);
395da9b9485SFabrice Gasnier 	}
396da9b9485SFabrice Gasnier 
397da9b9485SFabrice Gasnier 	if (!i)
398da9b9485SFabrice Gasnier 		return -EINVAL;
399da9b9485SFabrice Gasnier 
400da9b9485SFabrice Gasnier 	/* Sequence len */
401da9b9485SFabrice Gasnier 	val = stm32_adc_readl(adc, stm32f4_sq[0].reg);
402da9b9485SFabrice Gasnier 	val &= ~stm32f4_sq[0].mask;
403da9b9485SFabrice Gasnier 	val |= ((i - 1) << stm32f4_sq[0].shift);
404da9b9485SFabrice Gasnier 	stm32_adc_writel(adc, stm32f4_sq[0].reg, val);
405da9b9485SFabrice Gasnier 
406da9b9485SFabrice Gasnier 	return 0;
407da9b9485SFabrice Gasnier }
408da9b9485SFabrice Gasnier 
409da9b9485SFabrice Gasnier /**
410da9b9485SFabrice Gasnier  * stm32_adc_get_trig_extsel() - Get external trigger selection
411da9b9485SFabrice Gasnier  * @trig: trigger
412da9b9485SFabrice Gasnier  *
413da9b9485SFabrice Gasnier  * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
414da9b9485SFabrice Gasnier  */
415da9b9485SFabrice Gasnier static int stm32_adc_get_trig_extsel(struct iio_trigger *trig)
416da9b9485SFabrice Gasnier {
417f24a33b3SFabrice Gasnier 	int i;
418f24a33b3SFabrice Gasnier 
419f24a33b3SFabrice Gasnier 	/* lookup triggers registered by stm32 timer trigger driver */
420f24a33b3SFabrice Gasnier 	for (i = 0; stm32f4_adc_trigs[i].name; i++) {
421f24a33b3SFabrice Gasnier 		/**
422f24a33b3SFabrice Gasnier 		 * Checking both stm32 timer trigger type and trig name
423f24a33b3SFabrice Gasnier 		 * should be safe against arbitrary trigger names.
424f24a33b3SFabrice Gasnier 		 */
425f24a33b3SFabrice Gasnier 		if (is_stm32_timer_trigger(trig) &&
426f24a33b3SFabrice Gasnier 		    !strcmp(stm32f4_adc_trigs[i].name, trig->name)) {
427f24a33b3SFabrice Gasnier 			return stm32f4_adc_trigs[i].extsel;
428f24a33b3SFabrice Gasnier 		}
429f24a33b3SFabrice Gasnier 	}
430f24a33b3SFabrice Gasnier 
431da9b9485SFabrice Gasnier 	return -EINVAL;
432da9b9485SFabrice Gasnier }
433da9b9485SFabrice Gasnier 
434da9b9485SFabrice Gasnier /**
435da9b9485SFabrice Gasnier  * stm32_adc_set_trig() - Set a regular trigger
436da9b9485SFabrice Gasnier  * @indio_dev: IIO device
437da9b9485SFabrice Gasnier  * @trig: IIO trigger
438da9b9485SFabrice Gasnier  *
439da9b9485SFabrice Gasnier  * Set trigger source/polarity (e.g. SW, or HW with polarity) :
440da9b9485SFabrice Gasnier  * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
441da9b9485SFabrice Gasnier  * - if HW trigger enabled, set source & polarity
442da9b9485SFabrice Gasnier  */
443da9b9485SFabrice Gasnier static int stm32_adc_set_trig(struct iio_dev *indio_dev,
444da9b9485SFabrice Gasnier 			      struct iio_trigger *trig)
445da9b9485SFabrice Gasnier {
446da9b9485SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
447da9b9485SFabrice Gasnier 	u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG;
448da9b9485SFabrice Gasnier 	unsigned long flags;
449da9b9485SFabrice Gasnier 	int ret;
450da9b9485SFabrice Gasnier 
451da9b9485SFabrice Gasnier 	if (trig) {
452da9b9485SFabrice Gasnier 		ret = stm32_adc_get_trig_extsel(trig);
453da9b9485SFabrice Gasnier 		if (ret < 0)
454da9b9485SFabrice Gasnier 			return ret;
455da9b9485SFabrice Gasnier 
456da9b9485SFabrice Gasnier 		/* set trigger source and polarity (default to rising edge) */
457da9b9485SFabrice Gasnier 		extsel = ret;
458732f2dc4SFabrice Gasnier 		exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;
459da9b9485SFabrice Gasnier 	}
460da9b9485SFabrice Gasnier 
461da9b9485SFabrice Gasnier 	spin_lock_irqsave(&adc->lock, flags);
462da9b9485SFabrice Gasnier 	val = stm32_adc_readl(adc, STM32F4_ADC_CR2);
463da9b9485SFabrice Gasnier 	val &= ~(STM32F4_EXTEN_MASK | STM32F4_EXTSEL_MASK);
464da9b9485SFabrice Gasnier 	val |= exten << STM32F4_EXTEN_SHIFT;
465da9b9485SFabrice Gasnier 	val |= extsel << STM32F4_EXTSEL_SHIFT;
466da9b9485SFabrice Gasnier 	stm32_adc_writel(adc, STM32F4_ADC_CR2, val);
467da9b9485SFabrice Gasnier 	spin_unlock_irqrestore(&adc->lock, flags);
468da9b9485SFabrice Gasnier 
469da9b9485SFabrice Gasnier 	return 0;
470da9b9485SFabrice Gasnier }
471da9b9485SFabrice Gasnier 
472732f2dc4SFabrice Gasnier static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev,
473732f2dc4SFabrice Gasnier 				  const struct iio_chan_spec *chan,
474732f2dc4SFabrice Gasnier 				  unsigned int type)
475732f2dc4SFabrice Gasnier {
476732f2dc4SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
477732f2dc4SFabrice Gasnier 
478732f2dc4SFabrice Gasnier 	adc->trigger_polarity = type;
479732f2dc4SFabrice Gasnier 
480732f2dc4SFabrice Gasnier 	return 0;
481732f2dc4SFabrice Gasnier }
482732f2dc4SFabrice Gasnier 
483732f2dc4SFabrice Gasnier static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev,
484732f2dc4SFabrice Gasnier 				  const struct iio_chan_spec *chan)
485732f2dc4SFabrice Gasnier {
486732f2dc4SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
487732f2dc4SFabrice Gasnier 
488732f2dc4SFabrice Gasnier 	return adc->trigger_polarity;
489732f2dc4SFabrice Gasnier }
490732f2dc4SFabrice Gasnier 
491732f2dc4SFabrice Gasnier static const char * const stm32_trig_pol_items[] = {
492732f2dc4SFabrice Gasnier 	"rising-edge", "falling-edge", "both-edges",
493732f2dc4SFabrice Gasnier };
494732f2dc4SFabrice Gasnier 
4952763ea05SFabrice Gasnier static const struct iio_enum stm32_adc_trig_pol = {
496732f2dc4SFabrice Gasnier 	.items = stm32_trig_pol_items,
497732f2dc4SFabrice Gasnier 	.num_items = ARRAY_SIZE(stm32_trig_pol_items),
498732f2dc4SFabrice Gasnier 	.get = stm32_adc_get_trig_pol,
499732f2dc4SFabrice Gasnier 	.set = stm32_adc_set_trig_pol,
500732f2dc4SFabrice Gasnier };
501732f2dc4SFabrice Gasnier 
502da9b9485SFabrice Gasnier /**
5030f883b22SFabrice Gasnier  * stm32_adc_single_conv() - Performs a single conversion
5040f883b22SFabrice Gasnier  * @indio_dev: IIO device
5050f883b22SFabrice Gasnier  * @chan: IIO channel
5060f883b22SFabrice Gasnier  * @res: conversion result
5070f883b22SFabrice Gasnier  *
5080f883b22SFabrice Gasnier  * The function performs a single conversion on a given channel:
5090f883b22SFabrice Gasnier  * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
5100f883b22SFabrice Gasnier  * - Use SW trigger
5110f883b22SFabrice Gasnier  * - Start conversion, then wait for interrupt completion.
5120f883b22SFabrice Gasnier  */
5130f883b22SFabrice Gasnier static int stm32_adc_single_conv(struct iio_dev *indio_dev,
5140f883b22SFabrice Gasnier 				 const struct iio_chan_spec *chan,
5150f883b22SFabrice Gasnier 				 int *res)
5160f883b22SFabrice Gasnier {
5170f883b22SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
5180f883b22SFabrice Gasnier 	long timeout;
5190f883b22SFabrice Gasnier 	u32 val;
5200f883b22SFabrice Gasnier 	int ret;
5210f883b22SFabrice Gasnier 
5220f883b22SFabrice Gasnier 	reinit_completion(&adc->completion);
5230f883b22SFabrice Gasnier 
524da9b9485SFabrice Gasnier 	adc->bufi = 0;
5250f883b22SFabrice Gasnier 
526da9b9485SFabrice Gasnier 	/* Program chan number in regular sequence (SQ1) */
527da9b9485SFabrice Gasnier 	val = stm32_adc_readl(adc, stm32f4_sq[1].reg);
528da9b9485SFabrice Gasnier 	val &= ~stm32f4_sq[1].mask;
529da9b9485SFabrice Gasnier 	val |= chan->channel << stm32f4_sq[1].shift;
530da9b9485SFabrice Gasnier 	stm32_adc_writel(adc, stm32f4_sq[1].reg, val);
5310f883b22SFabrice Gasnier 
5320f883b22SFabrice Gasnier 	/* Set regular sequence len (0 for 1 conversion) */
533da9b9485SFabrice Gasnier 	stm32_adc_clr_bits(adc, stm32f4_sq[0].reg, stm32f4_sq[0].mask);
5340f883b22SFabrice Gasnier 
5350f883b22SFabrice Gasnier 	/* Trigger detection disabled (conversion can be launched in SW) */
5360f883b22SFabrice Gasnier 	stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
5370f883b22SFabrice Gasnier 
5380f883b22SFabrice Gasnier 	stm32_adc_conv_irq_enable(adc);
5390f883b22SFabrice Gasnier 
5402763ea05SFabrice Gasnier 	stm32_adc_start_conv(adc, false);
5410f883b22SFabrice Gasnier 
5420f883b22SFabrice Gasnier 	timeout = wait_for_completion_interruptible_timeout(
5430f883b22SFabrice Gasnier 					&adc->completion, STM32_ADC_TIMEOUT);
5440f883b22SFabrice Gasnier 	if (timeout == 0) {
5450f883b22SFabrice Gasnier 		ret = -ETIMEDOUT;
5460f883b22SFabrice Gasnier 	} else if (timeout < 0) {
5470f883b22SFabrice Gasnier 		ret = timeout;
5480f883b22SFabrice Gasnier 	} else {
549da9b9485SFabrice Gasnier 		*res = adc->buffer[0];
5500f883b22SFabrice Gasnier 		ret = IIO_VAL_INT;
5510f883b22SFabrice Gasnier 	}
5520f883b22SFabrice Gasnier 
5530f883b22SFabrice Gasnier 	stm32_adc_stop_conv(adc);
5540f883b22SFabrice Gasnier 
5550f883b22SFabrice Gasnier 	stm32_adc_conv_irq_disable(adc);
5560f883b22SFabrice Gasnier 
5570f883b22SFabrice Gasnier 	return ret;
5580f883b22SFabrice Gasnier }
5590f883b22SFabrice Gasnier 
5600f883b22SFabrice Gasnier static int stm32_adc_read_raw(struct iio_dev *indio_dev,
5610f883b22SFabrice Gasnier 			      struct iio_chan_spec const *chan,
5620f883b22SFabrice Gasnier 			      int *val, int *val2, long mask)
5630f883b22SFabrice Gasnier {
5640f883b22SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
5650f883b22SFabrice Gasnier 	int ret;
5660f883b22SFabrice Gasnier 
5670f883b22SFabrice Gasnier 	switch (mask) {
5680f883b22SFabrice Gasnier 	case IIO_CHAN_INFO_RAW:
5690f883b22SFabrice Gasnier 		ret = iio_device_claim_direct_mode(indio_dev);
5700f883b22SFabrice Gasnier 		if (ret)
5710f883b22SFabrice Gasnier 			return ret;
5720f883b22SFabrice Gasnier 		if (chan->type == IIO_VOLTAGE)
5730f883b22SFabrice Gasnier 			ret = stm32_adc_single_conv(indio_dev, chan, val);
5740f883b22SFabrice Gasnier 		else
5750f883b22SFabrice Gasnier 			ret = -EINVAL;
5760f883b22SFabrice Gasnier 		iio_device_release_direct_mode(indio_dev);
5770f883b22SFabrice Gasnier 		return ret;
5780f883b22SFabrice Gasnier 
5790f883b22SFabrice Gasnier 	case IIO_CHAN_INFO_SCALE:
5800f883b22SFabrice Gasnier 		*val = adc->common->vref_mv;
5810f883b22SFabrice Gasnier 		*val2 = chan->scan_type.realbits;
5820f883b22SFabrice Gasnier 		return IIO_VAL_FRACTIONAL_LOG2;
5830f883b22SFabrice Gasnier 
5840f883b22SFabrice Gasnier 	default:
5850f883b22SFabrice Gasnier 		return -EINVAL;
5860f883b22SFabrice Gasnier 	}
5870f883b22SFabrice Gasnier }
5880f883b22SFabrice Gasnier 
5890f883b22SFabrice Gasnier static irqreturn_t stm32_adc_isr(int irq, void *data)
5900f883b22SFabrice Gasnier {
5910f883b22SFabrice Gasnier 	struct stm32_adc *adc = data;
592da9b9485SFabrice Gasnier 	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
5930f883b22SFabrice Gasnier 	u32 status = stm32_adc_readl(adc, STM32F4_ADC_SR);
5940f883b22SFabrice Gasnier 
5950f883b22SFabrice Gasnier 	if (status & STM32F4_EOC) {
596da9b9485SFabrice Gasnier 		/* Reading DR also clears EOC status flag */
597da9b9485SFabrice Gasnier 		adc->buffer[adc->bufi] = stm32_adc_readw(adc, STM32F4_ADC_DR);
598da9b9485SFabrice Gasnier 		if (iio_buffer_enabled(indio_dev)) {
599da9b9485SFabrice Gasnier 			adc->bufi++;
600da9b9485SFabrice Gasnier 			if (adc->bufi >= adc->num_conv) {
601da9b9485SFabrice Gasnier 				stm32_adc_conv_irq_disable(adc);
602da9b9485SFabrice Gasnier 				iio_trigger_poll(indio_dev->trig);
603da9b9485SFabrice Gasnier 			}
604da9b9485SFabrice Gasnier 		} else {
6050f883b22SFabrice Gasnier 			complete(&adc->completion);
606da9b9485SFabrice Gasnier 		}
6070f883b22SFabrice Gasnier 		return IRQ_HANDLED;
6080f883b22SFabrice Gasnier 	}
6090f883b22SFabrice Gasnier 
6100f883b22SFabrice Gasnier 	return IRQ_NONE;
6110f883b22SFabrice Gasnier }
6120f883b22SFabrice Gasnier 
613da9b9485SFabrice Gasnier /**
614da9b9485SFabrice Gasnier  * stm32_adc_validate_trigger() - validate trigger for stm32 adc
615da9b9485SFabrice Gasnier  * @indio_dev: IIO device
616da9b9485SFabrice Gasnier  * @trig: new trigger
617da9b9485SFabrice Gasnier  *
618da9b9485SFabrice Gasnier  * Returns: 0 if trig matches one of the triggers registered by stm32 adc
619da9b9485SFabrice Gasnier  * driver, -EINVAL otherwise.
620da9b9485SFabrice Gasnier  */
621da9b9485SFabrice Gasnier static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
622da9b9485SFabrice Gasnier 				      struct iio_trigger *trig)
623da9b9485SFabrice Gasnier {
624da9b9485SFabrice Gasnier 	return stm32_adc_get_trig_extsel(trig) < 0 ? -EINVAL : 0;
625da9b9485SFabrice Gasnier }
626da9b9485SFabrice Gasnier 
6272763ea05SFabrice Gasnier static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
6282763ea05SFabrice Gasnier {
6292763ea05SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
6302763ea05SFabrice Gasnier 	unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2;
6312763ea05SFabrice Gasnier 
6322763ea05SFabrice Gasnier 	/*
6332763ea05SFabrice Gasnier 	 * dma cyclic transfers are used, buffer is split into two periods.
6342763ea05SFabrice Gasnier 	 * There should be :
6352763ea05SFabrice Gasnier 	 * - always one buffer (period) dma is working on
6362763ea05SFabrice Gasnier 	 * - one buffer (period) driver can push with iio_trigger_poll().
6372763ea05SFabrice Gasnier 	 */
6382763ea05SFabrice Gasnier 	watermark = min(watermark, val * (unsigned)(sizeof(u16)));
6392763ea05SFabrice Gasnier 	adc->rx_buf_sz = watermark * 2;
6402763ea05SFabrice Gasnier 
6412763ea05SFabrice Gasnier 	return 0;
6422763ea05SFabrice Gasnier }
6432763ea05SFabrice Gasnier 
644da9b9485SFabrice Gasnier static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev,
645da9b9485SFabrice Gasnier 				      const unsigned long *scan_mask)
646da9b9485SFabrice Gasnier {
647da9b9485SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
648da9b9485SFabrice Gasnier 	int ret;
649da9b9485SFabrice Gasnier 
650da9b9485SFabrice Gasnier 	adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
651da9b9485SFabrice Gasnier 
652da9b9485SFabrice Gasnier 	ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
653da9b9485SFabrice Gasnier 	if (ret)
654da9b9485SFabrice Gasnier 		return ret;
655da9b9485SFabrice Gasnier 
656da9b9485SFabrice Gasnier 	return 0;
657da9b9485SFabrice Gasnier }
658da9b9485SFabrice Gasnier 
6590f883b22SFabrice Gasnier static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
6600f883b22SFabrice Gasnier 			      const struct of_phandle_args *iiospec)
6610f883b22SFabrice Gasnier {
6620f883b22SFabrice Gasnier 	int i;
6630f883b22SFabrice Gasnier 
6640f883b22SFabrice Gasnier 	for (i = 0; i < indio_dev->num_channels; i++)
6650f883b22SFabrice Gasnier 		if (indio_dev->channels[i].channel == iiospec->args[0])
6660f883b22SFabrice Gasnier 			return i;
6670f883b22SFabrice Gasnier 
6680f883b22SFabrice Gasnier 	return -EINVAL;
6690f883b22SFabrice Gasnier }
6700f883b22SFabrice Gasnier 
6710f883b22SFabrice Gasnier /**
6720f883b22SFabrice Gasnier  * stm32_adc_debugfs_reg_access - read or write register value
6730f883b22SFabrice Gasnier  *
6740f883b22SFabrice Gasnier  * To read a value from an ADC register:
6750f883b22SFabrice Gasnier  *   echo [ADC reg offset] > direct_reg_access
6760f883b22SFabrice Gasnier  *   cat direct_reg_access
6770f883b22SFabrice Gasnier  *
6780f883b22SFabrice Gasnier  * To write a value in a ADC register:
6790f883b22SFabrice Gasnier  *   echo [ADC_reg_offset] [value] > direct_reg_access
6800f883b22SFabrice Gasnier  */
6810f883b22SFabrice Gasnier static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
6820f883b22SFabrice Gasnier 					unsigned reg, unsigned writeval,
6830f883b22SFabrice Gasnier 					unsigned *readval)
6840f883b22SFabrice Gasnier {
6850f883b22SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
6860f883b22SFabrice Gasnier 
6870f883b22SFabrice Gasnier 	if (!readval)
6880f883b22SFabrice Gasnier 		stm32_adc_writel(adc, reg, writeval);
6890f883b22SFabrice Gasnier 	else
6900f883b22SFabrice Gasnier 		*readval = stm32_adc_readl(adc, reg);
6910f883b22SFabrice Gasnier 
6920f883b22SFabrice Gasnier 	return 0;
6930f883b22SFabrice Gasnier }
6940f883b22SFabrice Gasnier 
6950f883b22SFabrice Gasnier static const struct iio_info stm32_adc_iio_info = {
6960f883b22SFabrice Gasnier 	.read_raw = stm32_adc_read_raw,
697da9b9485SFabrice Gasnier 	.validate_trigger = stm32_adc_validate_trigger,
6982763ea05SFabrice Gasnier 	.hwfifo_set_watermark = stm32_adc_set_watermark,
699da9b9485SFabrice Gasnier 	.update_scan_mode = stm32_adc_update_scan_mode,
7000f883b22SFabrice Gasnier 	.debugfs_reg_access = stm32_adc_debugfs_reg_access,
7010f883b22SFabrice Gasnier 	.of_xlate = stm32_adc_of_xlate,
7020f883b22SFabrice Gasnier 	.driver_module = THIS_MODULE,
7030f883b22SFabrice Gasnier };
7040f883b22SFabrice Gasnier 
7052763ea05SFabrice Gasnier static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
7062763ea05SFabrice Gasnier {
7072763ea05SFabrice Gasnier 	struct dma_tx_state state;
7082763ea05SFabrice Gasnier 	enum dma_status status;
7092763ea05SFabrice Gasnier 
7102763ea05SFabrice Gasnier 	status = dmaengine_tx_status(adc->dma_chan,
7112763ea05SFabrice Gasnier 				     adc->dma_chan->cookie,
7122763ea05SFabrice Gasnier 				     &state);
7132763ea05SFabrice Gasnier 	if (status == DMA_IN_PROGRESS) {
7142763ea05SFabrice Gasnier 		/* Residue is size in bytes from end of buffer */
7152763ea05SFabrice Gasnier 		unsigned int i = adc->rx_buf_sz - state.residue;
7162763ea05SFabrice Gasnier 		unsigned int size;
7172763ea05SFabrice Gasnier 
7182763ea05SFabrice Gasnier 		/* Return available bytes */
7192763ea05SFabrice Gasnier 		if (i >= adc->bufi)
7202763ea05SFabrice Gasnier 			size = i - adc->bufi;
7212763ea05SFabrice Gasnier 		else
7222763ea05SFabrice Gasnier 			size = adc->rx_buf_sz + i - adc->bufi;
7232763ea05SFabrice Gasnier 
7242763ea05SFabrice Gasnier 		return size;
7252763ea05SFabrice Gasnier 	}
7262763ea05SFabrice Gasnier 
7272763ea05SFabrice Gasnier 	return 0;
7282763ea05SFabrice Gasnier }
7292763ea05SFabrice Gasnier 
7302763ea05SFabrice Gasnier static void stm32_adc_dma_buffer_done(void *data)
7312763ea05SFabrice Gasnier {
7322763ea05SFabrice Gasnier 	struct iio_dev *indio_dev = data;
7332763ea05SFabrice Gasnier 
7342763ea05SFabrice Gasnier 	iio_trigger_poll_chained(indio_dev->trig);
7352763ea05SFabrice Gasnier }
7362763ea05SFabrice Gasnier 
7372763ea05SFabrice Gasnier static int stm32_adc_dma_start(struct iio_dev *indio_dev)
7382763ea05SFabrice Gasnier {
7392763ea05SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
7402763ea05SFabrice Gasnier 	struct dma_async_tx_descriptor *desc;
7412763ea05SFabrice Gasnier 	dma_cookie_t cookie;
7422763ea05SFabrice Gasnier 	int ret;
7432763ea05SFabrice Gasnier 
7442763ea05SFabrice Gasnier 	if (!adc->dma_chan)
7452763ea05SFabrice Gasnier 		return 0;
7462763ea05SFabrice Gasnier 
7472763ea05SFabrice Gasnier 	dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
7482763ea05SFabrice Gasnier 		adc->rx_buf_sz, adc->rx_buf_sz / 2);
7492763ea05SFabrice Gasnier 
7502763ea05SFabrice Gasnier 	/* Prepare a DMA cyclic transaction */
7512763ea05SFabrice Gasnier 	desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
7522763ea05SFabrice Gasnier 					 adc->rx_dma_buf,
7532763ea05SFabrice Gasnier 					 adc->rx_buf_sz, adc->rx_buf_sz / 2,
7542763ea05SFabrice Gasnier 					 DMA_DEV_TO_MEM,
7552763ea05SFabrice Gasnier 					 DMA_PREP_INTERRUPT);
7562763ea05SFabrice Gasnier 	if (!desc)
7572763ea05SFabrice Gasnier 		return -EBUSY;
7582763ea05SFabrice Gasnier 
7592763ea05SFabrice Gasnier 	desc->callback = stm32_adc_dma_buffer_done;
7602763ea05SFabrice Gasnier 	desc->callback_param = indio_dev;
7612763ea05SFabrice Gasnier 
7622763ea05SFabrice Gasnier 	cookie = dmaengine_submit(desc);
7632763ea05SFabrice Gasnier 	ret = dma_submit_error(cookie);
7642763ea05SFabrice Gasnier 	if (ret) {
7652763ea05SFabrice Gasnier 		dmaengine_terminate_all(adc->dma_chan);
7662763ea05SFabrice Gasnier 		return ret;
7672763ea05SFabrice Gasnier 	}
7682763ea05SFabrice Gasnier 
7692763ea05SFabrice Gasnier 	/* Issue pending DMA requests */
7702763ea05SFabrice Gasnier 	dma_async_issue_pending(adc->dma_chan);
7712763ea05SFabrice Gasnier 
7722763ea05SFabrice Gasnier 	return 0;
7732763ea05SFabrice Gasnier }
7742763ea05SFabrice Gasnier 
775da9b9485SFabrice Gasnier static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
776da9b9485SFabrice Gasnier {
777da9b9485SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
778da9b9485SFabrice Gasnier 	int ret;
779da9b9485SFabrice Gasnier 
780da9b9485SFabrice Gasnier 	ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
781da9b9485SFabrice Gasnier 	if (ret) {
782da9b9485SFabrice Gasnier 		dev_err(&indio_dev->dev, "Can't set trigger\n");
783da9b9485SFabrice Gasnier 		return ret;
784da9b9485SFabrice Gasnier 	}
785da9b9485SFabrice Gasnier 
7862763ea05SFabrice Gasnier 	ret = stm32_adc_dma_start(indio_dev);
7872763ea05SFabrice Gasnier 	if (ret) {
7882763ea05SFabrice Gasnier 		dev_err(&indio_dev->dev, "Can't start dma\n");
7892763ea05SFabrice Gasnier 		goto err_clr_trig;
7902763ea05SFabrice Gasnier 	}
7912763ea05SFabrice Gasnier 
792da9b9485SFabrice Gasnier 	ret = iio_triggered_buffer_postenable(indio_dev);
793da9b9485SFabrice Gasnier 	if (ret < 0)
7942763ea05SFabrice Gasnier 		goto err_stop_dma;
795da9b9485SFabrice Gasnier 
796da9b9485SFabrice Gasnier 	/* Reset adc buffer index */
797da9b9485SFabrice Gasnier 	adc->bufi = 0;
798da9b9485SFabrice Gasnier 
7992763ea05SFabrice Gasnier 	if (!adc->dma_chan)
800da9b9485SFabrice Gasnier 		stm32_adc_conv_irq_enable(adc);
8012763ea05SFabrice Gasnier 
8022763ea05SFabrice Gasnier 	stm32_adc_start_conv(adc, !!adc->dma_chan);
803da9b9485SFabrice Gasnier 
804da9b9485SFabrice Gasnier 	return 0;
805da9b9485SFabrice Gasnier 
8062763ea05SFabrice Gasnier err_stop_dma:
8072763ea05SFabrice Gasnier 	if (adc->dma_chan)
8082763ea05SFabrice Gasnier 		dmaengine_terminate_all(adc->dma_chan);
809da9b9485SFabrice Gasnier err_clr_trig:
810da9b9485SFabrice Gasnier 	stm32_adc_set_trig(indio_dev, NULL);
811da9b9485SFabrice Gasnier 
812da9b9485SFabrice Gasnier 	return ret;
813da9b9485SFabrice Gasnier }
814da9b9485SFabrice Gasnier 
815da9b9485SFabrice Gasnier static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
816da9b9485SFabrice Gasnier {
817da9b9485SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
818da9b9485SFabrice Gasnier 	int ret;
819da9b9485SFabrice Gasnier 
820da9b9485SFabrice Gasnier 	stm32_adc_stop_conv(adc);
8212763ea05SFabrice Gasnier 	if (!adc->dma_chan)
822da9b9485SFabrice Gasnier 		stm32_adc_conv_irq_disable(adc);
823da9b9485SFabrice Gasnier 
824da9b9485SFabrice Gasnier 	ret = iio_triggered_buffer_predisable(indio_dev);
825da9b9485SFabrice Gasnier 	if (ret < 0)
826da9b9485SFabrice Gasnier 		dev_err(&indio_dev->dev, "predisable failed\n");
827da9b9485SFabrice Gasnier 
8282763ea05SFabrice Gasnier 	if (adc->dma_chan)
8292763ea05SFabrice Gasnier 		dmaengine_terminate_all(adc->dma_chan);
8302763ea05SFabrice Gasnier 
831da9b9485SFabrice Gasnier 	if (stm32_adc_set_trig(indio_dev, NULL))
832da9b9485SFabrice Gasnier 		dev_err(&indio_dev->dev, "Can't clear trigger\n");
833da9b9485SFabrice Gasnier 
834da9b9485SFabrice Gasnier 	return ret;
835da9b9485SFabrice Gasnier }
836da9b9485SFabrice Gasnier 
837da9b9485SFabrice Gasnier static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = {
838da9b9485SFabrice Gasnier 	.postenable = &stm32_adc_buffer_postenable,
839da9b9485SFabrice Gasnier 	.predisable = &stm32_adc_buffer_predisable,
840da9b9485SFabrice Gasnier };
841da9b9485SFabrice Gasnier 
842da9b9485SFabrice Gasnier static irqreturn_t stm32_adc_trigger_handler(int irq, void *p)
843da9b9485SFabrice Gasnier {
844da9b9485SFabrice Gasnier 	struct iio_poll_func *pf = p;
845da9b9485SFabrice Gasnier 	struct iio_dev *indio_dev = pf->indio_dev;
846da9b9485SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
847da9b9485SFabrice Gasnier 
848da9b9485SFabrice Gasnier 	dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
849da9b9485SFabrice Gasnier 
8502763ea05SFabrice Gasnier 	if (!adc->dma_chan) {
851da9b9485SFabrice Gasnier 		/* reset buffer index */
852da9b9485SFabrice Gasnier 		adc->bufi = 0;
853da9b9485SFabrice Gasnier 		iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
854da9b9485SFabrice Gasnier 						   pf->timestamp);
8552763ea05SFabrice Gasnier 	} else {
8562763ea05SFabrice Gasnier 		int residue = stm32_adc_dma_residue(adc);
8572763ea05SFabrice Gasnier 
8582763ea05SFabrice Gasnier 		while (residue >= indio_dev->scan_bytes) {
8592763ea05SFabrice Gasnier 			u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
8602763ea05SFabrice Gasnier 
8612763ea05SFabrice Gasnier 			iio_push_to_buffers_with_timestamp(indio_dev, buffer,
8622763ea05SFabrice Gasnier 							   pf->timestamp);
8632763ea05SFabrice Gasnier 			residue -= indio_dev->scan_bytes;
8642763ea05SFabrice Gasnier 			adc->bufi += indio_dev->scan_bytes;
8652763ea05SFabrice Gasnier 			if (adc->bufi >= adc->rx_buf_sz)
8662763ea05SFabrice Gasnier 				adc->bufi = 0;
8672763ea05SFabrice Gasnier 		}
8682763ea05SFabrice Gasnier 	}
869da9b9485SFabrice Gasnier 
870da9b9485SFabrice Gasnier 	iio_trigger_notify_done(indio_dev->trig);
871da9b9485SFabrice Gasnier 
872da9b9485SFabrice Gasnier 	/* re-enable eoc irq */
8732763ea05SFabrice Gasnier 	if (!adc->dma_chan)
874da9b9485SFabrice Gasnier 		stm32_adc_conv_irq_enable(adc);
875da9b9485SFabrice Gasnier 
876da9b9485SFabrice Gasnier 	return IRQ_HANDLED;
877da9b9485SFabrice Gasnier }
878da9b9485SFabrice Gasnier 
879732f2dc4SFabrice Gasnier static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = {
880732f2dc4SFabrice Gasnier 	IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol),
881732f2dc4SFabrice Gasnier 	{
882732f2dc4SFabrice Gasnier 		.name = "trigger_polarity_available",
883732f2dc4SFabrice Gasnier 		.shared = IIO_SHARED_BY_ALL,
884732f2dc4SFabrice Gasnier 		.read = iio_enum_available_read,
885732f2dc4SFabrice Gasnier 		.private = (uintptr_t)&stm32_adc_trig_pol,
886732f2dc4SFabrice Gasnier 	},
887732f2dc4SFabrice Gasnier 	{},
888732f2dc4SFabrice Gasnier };
889732f2dc4SFabrice Gasnier 
890*25a85bedSFabrice Gasnier static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
891*25a85bedSFabrice Gasnier {
892*25a85bedSFabrice Gasnier 	struct device_node *node = indio_dev->dev.of_node;
893*25a85bedSFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
894*25a85bedSFabrice Gasnier 	unsigned int i;
895*25a85bedSFabrice Gasnier 	u32 res;
896*25a85bedSFabrice Gasnier 
897*25a85bedSFabrice Gasnier 	if (of_property_read_u32(node, "assigned-resolution-bits", &res))
898*25a85bedSFabrice Gasnier 		res = stm32f4_adc_resolutions[0];
899*25a85bedSFabrice Gasnier 
900*25a85bedSFabrice Gasnier 	for (i = 0; i < ARRAY_SIZE(stm32f4_adc_resolutions); i++)
901*25a85bedSFabrice Gasnier 		if (res == stm32f4_adc_resolutions[i])
902*25a85bedSFabrice Gasnier 			break;
903*25a85bedSFabrice Gasnier 	if (i >= ARRAY_SIZE(stm32f4_adc_resolutions)) {
904*25a85bedSFabrice Gasnier 		dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
905*25a85bedSFabrice Gasnier 		return -EINVAL;
906*25a85bedSFabrice Gasnier 	}
907*25a85bedSFabrice Gasnier 
908*25a85bedSFabrice Gasnier 	dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res);
909*25a85bedSFabrice Gasnier 	adc->res = i;
910*25a85bedSFabrice Gasnier 
911*25a85bedSFabrice Gasnier 	return 0;
912*25a85bedSFabrice Gasnier }
913*25a85bedSFabrice Gasnier 
9140f883b22SFabrice Gasnier static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
9150f883b22SFabrice Gasnier 				    struct iio_chan_spec *chan,
9160f883b22SFabrice Gasnier 				    const struct stm32_adc_chan_spec *channel,
9170f883b22SFabrice Gasnier 				    int scan_index)
9180f883b22SFabrice Gasnier {
919*25a85bedSFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
920*25a85bedSFabrice Gasnier 
9210f883b22SFabrice Gasnier 	chan->type = channel->type;
9220f883b22SFabrice Gasnier 	chan->channel = channel->channel;
9230f883b22SFabrice Gasnier 	chan->datasheet_name = channel->name;
9240f883b22SFabrice Gasnier 	chan->scan_index = scan_index;
9250f883b22SFabrice Gasnier 	chan->indexed = 1;
9260f883b22SFabrice Gasnier 	chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
9270f883b22SFabrice Gasnier 	chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
9280f883b22SFabrice Gasnier 	chan->scan_type.sign = 'u';
929*25a85bedSFabrice Gasnier 	chan->scan_type.realbits = stm32f4_adc_resolutions[adc->res];
9300f883b22SFabrice Gasnier 	chan->scan_type.storagebits = 16;
931732f2dc4SFabrice Gasnier 	chan->ext_info = stm32_adc_ext_info;
9320f883b22SFabrice Gasnier }
9330f883b22SFabrice Gasnier 
9340f883b22SFabrice Gasnier static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
9350f883b22SFabrice Gasnier {
9360f883b22SFabrice Gasnier 	struct device_node *node = indio_dev->dev.of_node;
9370f883b22SFabrice Gasnier 	struct property *prop;
9380f883b22SFabrice Gasnier 	const __be32 *cur;
9390f883b22SFabrice Gasnier 	struct iio_chan_spec *channels;
9400f883b22SFabrice Gasnier 	int scan_index = 0, num_channels;
9410f883b22SFabrice Gasnier 	u32 val;
9420f883b22SFabrice Gasnier 
9430f883b22SFabrice Gasnier 	num_channels = of_property_count_u32_elems(node, "st,adc-channels");
9440f883b22SFabrice Gasnier 	if (num_channels < 0 ||
9450f883b22SFabrice Gasnier 	    num_channels >= ARRAY_SIZE(stm32f4_adc123_channels)) {
9460f883b22SFabrice Gasnier 		dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
9470f883b22SFabrice Gasnier 		return num_channels < 0 ? num_channels : -EINVAL;
9480f883b22SFabrice Gasnier 	}
9490f883b22SFabrice Gasnier 
9500f883b22SFabrice Gasnier 	channels = devm_kcalloc(&indio_dev->dev, num_channels,
9510f883b22SFabrice Gasnier 				sizeof(struct iio_chan_spec), GFP_KERNEL);
9520f883b22SFabrice Gasnier 	if (!channels)
9530f883b22SFabrice Gasnier 		return -ENOMEM;
9540f883b22SFabrice Gasnier 
9550f883b22SFabrice Gasnier 	of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
9560f883b22SFabrice Gasnier 		if (val >= ARRAY_SIZE(stm32f4_adc123_channels)) {
9570f883b22SFabrice Gasnier 			dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
9580f883b22SFabrice Gasnier 			return -EINVAL;
9590f883b22SFabrice Gasnier 		}
9600f883b22SFabrice Gasnier 		stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
9610f883b22SFabrice Gasnier 					&stm32f4_adc123_channels[val],
9620f883b22SFabrice Gasnier 					scan_index);
9630f883b22SFabrice Gasnier 		scan_index++;
9640f883b22SFabrice Gasnier 	}
9650f883b22SFabrice Gasnier 
9660f883b22SFabrice Gasnier 	indio_dev->num_channels = scan_index;
9670f883b22SFabrice Gasnier 	indio_dev->channels = channels;
9680f883b22SFabrice Gasnier 
9690f883b22SFabrice Gasnier 	return 0;
9700f883b22SFabrice Gasnier }
9710f883b22SFabrice Gasnier 
9722763ea05SFabrice Gasnier static int stm32_adc_dma_request(struct iio_dev *indio_dev)
9732763ea05SFabrice Gasnier {
9742763ea05SFabrice Gasnier 	struct stm32_adc *adc = iio_priv(indio_dev);
9752763ea05SFabrice Gasnier 	struct dma_slave_config config;
9762763ea05SFabrice Gasnier 	int ret;
9772763ea05SFabrice Gasnier 
9782763ea05SFabrice Gasnier 	adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
9792763ea05SFabrice Gasnier 	if (!adc->dma_chan)
9802763ea05SFabrice Gasnier 		return 0;
9812763ea05SFabrice Gasnier 
9822763ea05SFabrice Gasnier 	adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
9832763ea05SFabrice Gasnier 					 STM32_DMA_BUFFER_SIZE,
9842763ea05SFabrice Gasnier 					 &adc->rx_dma_buf, GFP_KERNEL);
9852763ea05SFabrice Gasnier 	if (!adc->rx_buf) {
9862763ea05SFabrice Gasnier 		ret = -ENOMEM;
9872763ea05SFabrice Gasnier 		goto err_release;
9882763ea05SFabrice Gasnier 	}
9892763ea05SFabrice Gasnier 
9902763ea05SFabrice Gasnier 	/* Configure DMA channel to read data register */
9912763ea05SFabrice Gasnier 	memset(&config, 0, sizeof(config));
9922763ea05SFabrice Gasnier 	config.src_addr = (dma_addr_t)adc->common->phys_base;
9932763ea05SFabrice Gasnier 	config.src_addr += adc->offset + STM32F4_ADC_DR;
9942763ea05SFabrice Gasnier 	config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
9952763ea05SFabrice Gasnier 
9962763ea05SFabrice Gasnier 	ret = dmaengine_slave_config(adc->dma_chan, &config);
9972763ea05SFabrice Gasnier 	if (ret)
9982763ea05SFabrice Gasnier 		goto err_free;
9992763ea05SFabrice Gasnier 
10002763ea05SFabrice Gasnier 	return 0;
10012763ea05SFabrice Gasnier 
10022763ea05SFabrice Gasnier err_free:
10032763ea05SFabrice Gasnier 	dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,
10042763ea05SFabrice Gasnier 			  adc->rx_buf, adc->rx_dma_buf);
10052763ea05SFabrice Gasnier err_release:
10062763ea05SFabrice Gasnier 	dma_release_channel(adc->dma_chan);
10072763ea05SFabrice Gasnier 
10082763ea05SFabrice Gasnier 	return ret;
10092763ea05SFabrice Gasnier }
10102763ea05SFabrice Gasnier 
10110f883b22SFabrice Gasnier static int stm32_adc_probe(struct platform_device *pdev)
10120f883b22SFabrice Gasnier {
10130f883b22SFabrice Gasnier 	struct iio_dev *indio_dev;
10140f883b22SFabrice Gasnier 	struct stm32_adc *adc;
10150f883b22SFabrice Gasnier 	int ret;
10160f883b22SFabrice Gasnier 
10170f883b22SFabrice Gasnier 	if (!pdev->dev.of_node)
10180f883b22SFabrice Gasnier 		return -ENODEV;
10190f883b22SFabrice Gasnier 
10200f883b22SFabrice Gasnier 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
10210f883b22SFabrice Gasnier 	if (!indio_dev)
10220f883b22SFabrice Gasnier 		return -ENOMEM;
10230f883b22SFabrice Gasnier 
10240f883b22SFabrice Gasnier 	adc = iio_priv(indio_dev);
10250f883b22SFabrice Gasnier 	adc->common = dev_get_drvdata(pdev->dev.parent);
10260f883b22SFabrice Gasnier 	spin_lock_init(&adc->lock);
10270f883b22SFabrice Gasnier 	init_completion(&adc->completion);
10280f883b22SFabrice Gasnier 
10290f883b22SFabrice Gasnier 	indio_dev->name = dev_name(&pdev->dev);
10300f883b22SFabrice Gasnier 	indio_dev->dev.parent = &pdev->dev;
10310f883b22SFabrice Gasnier 	indio_dev->dev.of_node = pdev->dev.of_node;
10320f883b22SFabrice Gasnier 	indio_dev->info = &stm32_adc_iio_info;
10330f883b22SFabrice Gasnier 	indio_dev->modes = INDIO_DIRECT_MODE;
10340f883b22SFabrice Gasnier 
10350f883b22SFabrice Gasnier 	platform_set_drvdata(pdev, adc);
10360f883b22SFabrice Gasnier 
10370f883b22SFabrice Gasnier 	ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
10380f883b22SFabrice Gasnier 	if (ret != 0) {
10390f883b22SFabrice Gasnier 		dev_err(&pdev->dev, "missing reg property\n");
10400f883b22SFabrice Gasnier 		return -EINVAL;
10410f883b22SFabrice Gasnier 	}
10420f883b22SFabrice Gasnier 
10430f883b22SFabrice Gasnier 	adc->irq = platform_get_irq(pdev, 0);
10440f883b22SFabrice Gasnier 	if (adc->irq < 0) {
10450f883b22SFabrice Gasnier 		dev_err(&pdev->dev, "failed to get irq\n");
10460f883b22SFabrice Gasnier 		return adc->irq;
10470f883b22SFabrice Gasnier 	}
10480f883b22SFabrice Gasnier 
10490f883b22SFabrice Gasnier 	ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr,
10500f883b22SFabrice Gasnier 			       0, pdev->name, adc);
10510f883b22SFabrice Gasnier 	if (ret) {
10520f883b22SFabrice Gasnier 		dev_err(&pdev->dev, "failed to request IRQ\n");
10530f883b22SFabrice Gasnier 		return ret;
10540f883b22SFabrice Gasnier 	}
10550f883b22SFabrice Gasnier 
10560f883b22SFabrice Gasnier 	adc->clk = devm_clk_get(&pdev->dev, NULL);
10570f883b22SFabrice Gasnier 	if (IS_ERR(adc->clk)) {
10580f883b22SFabrice Gasnier 		dev_err(&pdev->dev, "Can't get clock\n");
10590f883b22SFabrice Gasnier 		return PTR_ERR(adc->clk);
10600f883b22SFabrice Gasnier 	}
10610f883b22SFabrice Gasnier 
10620f883b22SFabrice Gasnier 	ret = clk_prepare_enable(adc->clk);
10630f883b22SFabrice Gasnier 	if (ret < 0) {
10640f883b22SFabrice Gasnier 		dev_err(&pdev->dev, "clk enable failed\n");
10650f883b22SFabrice Gasnier 		return ret;
10660f883b22SFabrice Gasnier 	}
10670f883b22SFabrice Gasnier 
1068*25a85bedSFabrice Gasnier 	ret = stm32_adc_of_get_resolution(indio_dev);
1069*25a85bedSFabrice Gasnier 	if (ret < 0)
1070*25a85bedSFabrice Gasnier 		goto err_clk_disable;
1071*25a85bedSFabrice Gasnier 	stm32_adc_set_res(adc);
1072*25a85bedSFabrice Gasnier 
10730f883b22SFabrice Gasnier 	ret = stm32_adc_chan_of_init(indio_dev);
10740f883b22SFabrice Gasnier 	if (ret < 0)
10750f883b22SFabrice Gasnier 		goto err_clk_disable;
10760f883b22SFabrice Gasnier 
10772763ea05SFabrice Gasnier 	ret = stm32_adc_dma_request(indio_dev);
10782763ea05SFabrice Gasnier 	if (ret < 0)
10792763ea05SFabrice Gasnier 		goto err_clk_disable;
10802763ea05SFabrice Gasnier 
1081da9b9485SFabrice Gasnier 	ret = iio_triggered_buffer_setup(indio_dev,
1082da9b9485SFabrice Gasnier 					 &iio_pollfunc_store_time,
1083da9b9485SFabrice Gasnier 					 &stm32_adc_trigger_handler,
1084da9b9485SFabrice Gasnier 					 &stm32_adc_buffer_setup_ops);
10850f883b22SFabrice Gasnier 	if (ret) {
1086da9b9485SFabrice Gasnier 		dev_err(&pdev->dev, "buffer setup failed\n");
10872763ea05SFabrice Gasnier 		goto err_dma_disable;
10880f883b22SFabrice Gasnier 	}
10890f883b22SFabrice Gasnier 
1090da9b9485SFabrice Gasnier 	ret = iio_device_register(indio_dev);
1091da9b9485SFabrice Gasnier 	if (ret) {
1092da9b9485SFabrice Gasnier 		dev_err(&pdev->dev, "iio dev register failed\n");
1093da9b9485SFabrice Gasnier 		goto err_buffer_cleanup;
1094da9b9485SFabrice Gasnier 	}
1095da9b9485SFabrice Gasnier 
10960f883b22SFabrice Gasnier 	return 0;
10970f883b22SFabrice Gasnier 
1098da9b9485SFabrice Gasnier err_buffer_cleanup:
1099da9b9485SFabrice Gasnier 	iio_triggered_buffer_cleanup(indio_dev);
1100da9b9485SFabrice Gasnier 
11012763ea05SFabrice Gasnier err_dma_disable:
11022763ea05SFabrice Gasnier 	if (adc->dma_chan) {
11032763ea05SFabrice Gasnier 		dma_free_coherent(adc->dma_chan->device->dev,
11042763ea05SFabrice Gasnier 				  STM32_DMA_BUFFER_SIZE,
11052763ea05SFabrice Gasnier 				  adc->rx_buf, adc->rx_dma_buf);
11062763ea05SFabrice Gasnier 		dma_release_channel(adc->dma_chan);
11072763ea05SFabrice Gasnier 	}
11080f883b22SFabrice Gasnier err_clk_disable:
11090f883b22SFabrice Gasnier 	clk_disable_unprepare(adc->clk);
11100f883b22SFabrice Gasnier 
11110f883b22SFabrice Gasnier 	return ret;
11120f883b22SFabrice Gasnier }
11130f883b22SFabrice Gasnier 
11140f883b22SFabrice Gasnier static int stm32_adc_remove(struct platform_device *pdev)
11150f883b22SFabrice Gasnier {
11160f883b22SFabrice Gasnier 	struct stm32_adc *adc = platform_get_drvdata(pdev);
11170f883b22SFabrice Gasnier 	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
11180f883b22SFabrice Gasnier 
11190f883b22SFabrice Gasnier 	iio_device_unregister(indio_dev);
1120da9b9485SFabrice Gasnier 	iio_triggered_buffer_cleanup(indio_dev);
11212763ea05SFabrice Gasnier 	if (adc->dma_chan) {
11222763ea05SFabrice Gasnier 		dma_free_coherent(adc->dma_chan->device->dev,
11232763ea05SFabrice Gasnier 				  STM32_DMA_BUFFER_SIZE,
11242763ea05SFabrice Gasnier 				  adc->rx_buf, adc->rx_dma_buf);
11252763ea05SFabrice Gasnier 		dma_release_channel(adc->dma_chan);
11262763ea05SFabrice Gasnier 	}
11270f883b22SFabrice Gasnier 	clk_disable_unprepare(adc->clk);
11280f883b22SFabrice Gasnier 
11290f883b22SFabrice Gasnier 	return 0;
11300f883b22SFabrice Gasnier }
11310f883b22SFabrice Gasnier 
11320f883b22SFabrice Gasnier static const struct of_device_id stm32_adc_of_match[] = {
11330f883b22SFabrice Gasnier 	{ .compatible = "st,stm32f4-adc" },
11340f883b22SFabrice Gasnier 	{},
11350f883b22SFabrice Gasnier };
11360f883b22SFabrice Gasnier MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
11370f883b22SFabrice Gasnier 
11380f883b22SFabrice Gasnier static struct platform_driver stm32_adc_driver = {
11390f883b22SFabrice Gasnier 	.probe = stm32_adc_probe,
11400f883b22SFabrice Gasnier 	.remove = stm32_adc_remove,
11410f883b22SFabrice Gasnier 	.driver = {
11420f883b22SFabrice Gasnier 		.name = "stm32-adc",
11430f883b22SFabrice Gasnier 		.of_match_table = stm32_adc_of_match,
11440f883b22SFabrice Gasnier 	},
11450f883b22SFabrice Gasnier };
11460f883b22SFabrice Gasnier module_platform_driver(stm32_adc_driver);
11470f883b22SFabrice Gasnier 
11480f883b22SFabrice Gasnier MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
11490f883b22SFabrice Gasnier MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
11500f883b22SFabrice Gasnier MODULE_LICENSE("GPL v2");
11510f883b22SFabrice Gasnier MODULE_ALIAS("platform:stm32-adc");
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