1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 */ 9 10 #ifndef __STM32_ADC_H 11 #define __STM32_ADC_H 12 13 /* 14 * STM32 - ADC global register map 15 * ________________________________________________________ 16 * | Offset | Register | 17 * -------------------------------------------------------- 18 * | 0x000 | Master ADC1 | 19 * -------------------------------------------------------- 20 * | 0x100 | Slave ADC2 | 21 * -------------------------------------------------------- 22 * | 0x200 | Slave ADC3 | 23 * -------------------------------------------------------- 24 * | 0x300 | Master & Slave common regs | 25 * -------------------------------------------------------- 26 */ 27 /* Maximum ADC instances number per ADC block for all supported SoCs */ 28 #define STM32_ADC_MAX_ADCS 3 29 #define STM32_ADC_OFFSET 0x100 30 #define STM32_ADCX_COMN_OFFSET 0x300 31 32 /* STM32F4 - Registers for each ADC instance */ 33 #define STM32F4_ADC_SR 0x00 34 #define STM32F4_ADC_CR1 0x04 35 #define STM32F4_ADC_CR2 0x08 36 #define STM32F4_ADC_SMPR1 0x0C 37 #define STM32F4_ADC_SMPR2 0x10 38 #define STM32F4_ADC_HTR 0x24 39 #define STM32F4_ADC_LTR 0x28 40 #define STM32F4_ADC_SQR1 0x2C 41 #define STM32F4_ADC_SQR2 0x30 42 #define STM32F4_ADC_SQR3 0x34 43 #define STM32F4_ADC_JSQR 0x38 44 #define STM32F4_ADC_JDR1 0x3C 45 #define STM32F4_ADC_JDR2 0x40 46 #define STM32F4_ADC_JDR3 0x44 47 #define STM32F4_ADC_JDR4 0x48 48 #define STM32F4_ADC_DR 0x4C 49 50 /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */ 51 #define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) 52 #define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04) 53 54 /* STM32F4_ADC_SR - bit fields */ 55 #define STM32F4_OVR BIT(5) 56 #define STM32F4_STRT BIT(4) 57 #define STM32F4_EOC BIT(1) 58 59 /* STM32F4_ADC_CR1 - bit fields */ 60 #define STM32F4_OVRIE BIT(26) 61 #define STM32F4_RES_SHIFT 24 62 #define STM32F4_RES_MASK GENMASK(25, 24) 63 #define STM32F4_SCAN BIT(8) 64 #define STM32F4_EOCIE BIT(5) 65 66 /* STM32F4_ADC_CR2 - bit fields */ 67 #define STM32F4_SWSTART BIT(30) 68 #define STM32F4_EXTEN_SHIFT 28 69 #define STM32F4_EXTEN_MASK GENMASK(29, 28) 70 #define STM32F4_EXTSEL_SHIFT 24 71 #define STM32F4_EXTSEL_MASK GENMASK(27, 24) 72 #define STM32F4_EOCS BIT(10) 73 #define STM32F4_DDS BIT(9) 74 #define STM32F4_DMA BIT(8) 75 #define STM32F4_ADON BIT(0) 76 77 /* STM32F4_ADC_CSR - bit fields */ 78 #define STM32F4_OVR3 BIT(21) 79 #define STM32F4_EOC3 BIT(17) 80 #define STM32F4_OVR2 BIT(13) 81 #define STM32F4_EOC2 BIT(9) 82 #define STM32F4_OVR1 BIT(5) 83 #define STM32F4_EOC1 BIT(1) 84 85 /* STM32F4_ADC_CCR - bit fields */ 86 #define STM32F4_ADC_ADCPRE_SHIFT 16 87 #define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16) 88 89 /* STM32H7 - Registers for each ADC instance */ 90 #define STM32H7_ADC_ISR 0x00 91 #define STM32H7_ADC_IER 0x04 92 #define STM32H7_ADC_CR 0x08 93 #define STM32H7_ADC_CFGR 0x0C 94 #define STM32H7_ADC_SMPR1 0x14 95 #define STM32H7_ADC_SMPR2 0x18 96 #define STM32H7_ADC_PCSEL 0x1C 97 #define STM32H7_ADC_SQR1 0x30 98 #define STM32H7_ADC_SQR2 0x34 99 #define STM32H7_ADC_SQR3 0x38 100 #define STM32H7_ADC_SQR4 0x3C 101 #define STM32H7_ADC_DR 0x40 102 #define STM32H7_ADC_DIFSEL 0xC0 103 #define STM32H7_ADC_CALFACT 0xC4 104 #define STM32H7_ADC_CALFACT2 0xC8 105 106 /* STM32MP1 - ADC2 instance option register */ 107 #define STM32MP1_ADC2_OR 0xD0 108 109 /* STM32MP1 - Identification registers */ 110 #define STM32MP1_ADC_HWCFGR0 0x3F0 111 #define STM32MP1_ADC_VERR 0x3F4 112 #define STM32MP1_ADC_IPDR 0x3F8 113 #define STM32MP1_ADC_SIDR 0x3FC 114 115 /* STM32MP13 - Registers for each ADC instance */ 116 #define STM32MP13_ADC_DIFSEL 0xB0 117 #define STM32MP13_ADC_CALFACT 0xB4 118 #define STM32MP13_ADC2_OR 0xC8 119 120 /* STM32H7 - common registers for all ADC instances */ 121 #define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) 122 #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08) 123 124 /* STM32H7_ADC_ISR - bit fields */ 125 #define STM32MP1_VREGREADY BIT(12) 126 #define STM32H7_OVR BIT(4) 127 #define STM32H7_EOC BIT(2) 128 #define STM32H7_ADRDY BIT(0) 129 130 /* STM32H7_ADC_IER - bit fields */ 131 #define STM32H7_OVRIE STM32H7_OVR 132 #define STM32H7_EOCIE STM32H7_EOC 133 134 /* STM32H7_ADC_CR - bit fields */ 135 #define STM32H7_ADCAL BIT(31) 136 #define STM32H7_ADCALDIF BIT(30) 137 #define STM32H7_DEEPPWD BIT(29) 138 #define STM32H7_ADVREGEN BIT(28) 139 #define STM32H7_LINCALRDYW6 BIT(27) 140 #define STM32H7_LINCALRDYW5 BIT(26) 141 #define STM32H7_LINCALRDYW4 BIT(25) 142 #define STM32H7_LINCALRDYW3 BIT(24) 143 #define STM32H7_LINCALRDYW2 BIT(23) 144 #define STM32H7_LINCALRDYW1 BIT(22) 145 #define STM32H7_LINCALRDYW_MASK GENMASK(27, 22) 146 #define STM32H7_ADCALLIN BIT(16) 147 #define STM32H7_BOOST BIT(8) 148 #define STM32H7_ADSTP BIT(4) 149 #define STM32H7_ADSTART BIT(2) 150 #define STM32H7_ADDIS BIT(1) 151 #define STM32H7_ADEN BIT(0) 152 153 /* STM32H7_ADC_CFGR bit fields */ 154 #define STM32H7_EXTEN_SHIFT 10 155 #define STM32H7_EXTEN_MASK GENMASK(11, 10) 156 #define STM32H7_EXTSEL_SHIFT 5 157 #define STM32H7_EXTSEL_MASK GENMASK(9, 5) 158 #define STM32H7_RES_SHIFT 2 159 #define STM32H7_RES_MASK GENMASK(4, 2) 160 #define STM32H7_DMNGT_SHIFT 0 161 #define STM32H7_DMNGT_MASK GENMASK(1, 0) 162 163 enum stm32h7_adc_dmngt { 164 STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */ 165 STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */ 166 STM32H7_DMNGT_DFSDM, /* DFSDM mode */ 167 STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */ 168 }; 169 170 /* STM32H7_ADC_DIFSEL - bit fields */ 171 #define STM32H7_DIFSEL_MASK GENMASK(19, 0) 172 173 /* STM32H7_ADC_CALFACT - bit fields */ 174 #define STM32H7_CALFACT_D_SHIFT 16 175 #define STM32H7_CALFACT_D_MASK GENMASK(26, 16) 176 #define STM32H7_CALFACT_S_SHIFT 0 177 #define STM32H7_CALFACT_S_MASK GENMASK(10, 0) 178 179 /* STM32H7_ADC_CALFACT2 - bit fields */ 180 #define STM32H7_LINCALFACT_SHIFT 0 181 #define STM32H7_LINCALFACT_MASK GENMASK(29, 0) 182 183 /* STM32H7_ADC_CSR - bit fields */ 184 #define STM32H7_OVR_SLV BIT(20) 185 #define STM32H7_EOC_SLV BIT(18) 186 #define STM32H7_OVR_MST BIT(4) 187 #define STM32H7_EOC_MST BIT(2) 188 189 /* STM32H7_ADC_CCR - bit fields */ 190 #define STM32H7_VBATEN BIT(24) 191 #define STM32H7_VREFEN BIT(22) 192 #define STM32H7_PRESC_SHIFT 18 193 #define STM32H7_PRESC_MASK GENMASK(21, 18) 194 #define STM32H7_CKMODE_SHIFT 16 195 #define STM32H7_CKMODE_MASK GENMASK(17, 16) 196 197 /* STM32MP1_ADC2_OR - bit fields */ 198 #define STM32MP1_VDDCOREEN BIT(0) 199 200 /* STM32MP1_ADC_HWCFGR0 - bit fields */ 201 #define STM32MP1_ADCNUM_SHIFT 0 202 #define STM32MP1_ADCNUM_MASK GENMASK(3, 0) 203 #define STM32MP1_MULPIPE_SHIFT 4 204 #define STM32MP1_MULPIPE_MASK GENMASK(7, 4) 205 #define STM32MP1_OPBITS_SHIFT 8 206 #define STM32MP1_OPBITS_MASK GENMASK(11, 8) 207 #define STM32MP1_IDLEVALUE_SHIFT 12 208 #define STM32MP1_IDLEVALUE_MASK GENMASK(15, 12) 209 210 /* STM32MP1_ADC_VERR - bit fields */ 211 #define STM32MP1_MINREV_SHIFT 0 212 #define STM32MP1_MINREV_MASK GENMASK(3, 0) 213 #define STM32MP1_MAJREV_SHIFT 4 214 #define STM32MP1_MAJREV_MASK GENMASK(7, 4) 215 216 /* STM32MP1_ADC_IPDR - bit fields */ 217 #define STM32MP1_IPIDR_MASK GENMASK(31, 0) 218 219 /* STM32MP1_ADC_SIDR - bit fields */ 220 #define STM32MP1_SIDR_MASK GENMASK(31, 0) 221 222 /* STM32MP13_ADC_CFGR specific bit fields */ 223 #define STM32MP13_DMAEN BIT(0) 224 #define STM32MP13_DMACFG BIT(1) 225 #define STM32MP13_DFSDMCFG BIT(2) 226 #define STM32MP13_RES_SHIFT 3 227 #define STM32MP13_RES_MASK GENMASK(4, 3) 228 229 /* STM32MP13_ADC_DIFSEL - bit fields */ 230 #define STM32MP13_DIFSEL_MASK GENMASK(18, 0) 231 232 /* STM32MP13_ADC_CALFACT - bit fields */ 233 #define STM32MP13_CALFACT_D_SHIFT 16 234 #define STM32MP13_CALFACT_D_MASK GENMASK(22, 16) 235 #define STM32MP13_CALFACT_S_SHIFT 0 236 #define STM32MP13_CALFACT_S_MASK GENMASK(6, 0) 237 238 /* STM32MP13_ADC2_OR - bit fields */ 239 #define STM32MP13_OP2 BIT(2) 240 #define STM32MP13_OP1 BIT(1) 241 #define STM32MP13_OP0 BIT(0) 242 243 #define STM32MP15_IPIDR_NUMBER 0x00110005 244 #define STM32MP13_IPIDR_NUMBER 0x00110006 245 246 /** 247 * struct stm32_adc_common - stm32 ADC driver common data (for all instances) 248 * @base: control registers base cpu addr 249 * @phys_base: control registers base physical addr 250 * @rate: clock rate used for analog circuitry 251 * @vref_mv: vref voltage (mv) 252 * @lock: spinlock 253 */ 254 struct stm32_adc_common { 255 void __iomem *base; 256 phys_addr_t phys_base; 257 unsigned long rate; 258 int vref_mv; 259 spinlock_t lock; /* lock for common register */ 260 }; 261 262 #endif 263