1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/interrupt.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdesc.h> 17 #include <linux/irqdomain.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/property.h> 25 #include <linux/regmap.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/slab.h> 28 #include <linux/units.h> 29 30 #include "stm32-adc-core.h" 31 32 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 33 34 /* SYSCFG registers */ 35 #define STM32MP1_SYSCFG_PMCSETR 0x04 36 #define STM32MP1_SYSCFG_PMCCLRR 0x44 37 38 /* SYSCFG bit fields */ 39 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) 40 41 /* SYSCFG capability flags */ 42 #define HAS_VBOOSTER BIT(0) 43 #define HAS_ANASWVDD BIT(1) 44 45 /** 46 * struct stm32_adc_common_regs - stm32 common registers 47 * @csr: common status register offset 48 * @ccr: common control register offset 49 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n 50 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n 51 * @ier: interrupt enable register offset for each adc 52 * @eocie_msk: end of conversion interrupt enable mask in @ier 53 */ 54 struct stm32_adc_common_regs { 55 u32 csr; 56 u32 ccr; 57 u32 eoc_msk[STM32_ADC_MAX_ADCS]; 58 u32 ovr_msk[STM32_ADC_MAX_ADCS]; 59 u32 ier; 60 u32 eocie_msk; 61 }; 62 63 struct stm32_adc_priv; 64 65 /** 66 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data 67 * @regs: common registers for all instances 68 * @clk_sel: clock selection routine 69 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 70 * @ipid: adc identification number 71 * @has_syscfg: SYSCFG capability flags 72 * @num_irqs: number of interrupt lines 73 * @num_adcs: maximum number of ADC instances in the common registers 74 */ 75 struct stm32_adc_priv_cfg { 76 const struct stm32_adc_common_regs *regs; 77 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 78 u32 max_clk_rate_hz; 79 u32 ipid; 80 unsigned int has_syscfg; 81 unsigned int num_irqs; 82 unsigned int num_adcs; 83 }; 84 85 /** 86 * struct stm32_adc_priv - stm32 ADC core private data 87 * @irq: irq(s) for ADC block 88 * @nb_adc_max: actual maximum number of instance per ADC block 89 * @domain: irq domain reference 90 * @aclk: clock reference for the analog circuitry 91 * @bclk: bus clock common for all ADCs, depends on part used 92 * @max_clk_rate: desired maximum clock rate 93 * @booster: booster supply reference 94 * @vdd: vdd supply reference 95 * @vdda: vdda analog supply reference 96 * @vref: regulator reference 97 * @vdd_uv: vdd supply voltage (microvolts) 98 * @vdda_uv: vdda supply voltage (microvolts) 99 * @cfg: compatible configuration data 100 * @common: common data for all ADC instances 101 * @ccr_bak: backup CCR in low power mode 102 * @syscfg: reference to syscon, system control registers 103 */ 104 struct stm32_adc_priv { 105 int irq[STM32_ADC_MAX_ADCS]; 106 unsigned int nb_adc_max; 107 struct irq_domain *domain; 108 struct clk *aclk; 109 struct clk *bclk; 110 u32 max_clk_rate; 111 struct regulator *booster; 112 struct regulator *vdd; 113 struct regulator *vdda; 114 struct regulator *vref; 115 int vdd_uv; 116 int vdda_uv; 117 const struct stm32_adc_priv_cfg *cfg; 118 struct stm32_adc_common common; 119 u32 ccr_bak; 120 struct regmap *syscfg; 121 }; 122 123 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 124 { 125 return container_of(com, struct stm32_adc_priv, common); 126 } 127 128 /* STM32F4 ADC internal common clock prescaler division ratios */ 129 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 130 131 /** 132 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 133 * @pdev: platform device 134 * @priv: stm32 ADC core private data 135 * Select clock prescaler used for analog conversions, before using ADC. 136 */ 137 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 138 struct stm32_adc_priv *priv) 139 { 140 unsigned long rate; 141 u32 val; 142 int i; 143 144 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 145 if (!priv->aclk) { 146 dev_err(&pdev->dev, "No 'adc' clock found\n"); 147 return -ENOENT; 148 } 149 150 rate = clk_get_rate(priv->aclk); 151 if (!rate) { 152 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 153 return -EINVAL; 154 } 155 156 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 157 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate) 158 break; 159 } 160 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 161 dev_err(&pdev->dev, "adc clk selection failed\n"); 162 return -EINVAL; 163 } 164 165 priv->common.rate = rate / stm32f4_pclk_div[i]; 166 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 167 val &= ~STM32F4_ADC_ADCPRE_MASK; 168 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 169 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 170 171 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 172 priv->common.rate / 1000); 173 174 return 0; 175 } 176 177 /** 178 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 179 * @ckmode: ADC clock mode, Async or sync with prescaler. 180 * @presc: prescaler bitfield for async clock mode 181 * @div: prescaler division ratio 182 */ 183 struct stm32h7_adc_ck_spec { 184 u32 ckmode; 185 u32 presc; 186 int div; 187 }; 188 189 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 190 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 191 { 0, 0, 1 }, 192 { 0, 1, 2 }, 193 { 0, 2, 4 }, 194 { 0, 3, 6 }, 195 { 0, 4, 8 }, 196 { 0, 5, 10 }, 197 { 0, 6, 12 }, 198 { 0, 7, 16 }, 199 { 0, 8, 32 }, 200 { 0, 9, 64 }, 201 { 0, 10, 128 }, 202 { 0, 11, 256 }, 203 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 204 { 1, 0, 1 }, 205 { 2, 0, 2 }, 206 { 3, 0, 4 }, 207 }; 208 209 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 210 struct stm32_adc_priv *priv) 211 { 212 u32 ckmode, presc, val; 213 unsigned long rate; 214 int i, div, duty; 215 216 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 217 if (!priv->bclk) { 218 dev_err(&pdev->dev, "No 'bus' clock found\n"); 219 return -ENOENT; 220 } 221 222 /* 223 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 224 * So, choice is to have bus clock mandatory and adc clock optional. 225 * If optional 'adc' clock has been found, then try to use it first. 226 */ 227 if (priv->aclk) { 228 /* 229 * Asynchronous clock modes (e.g. ckmode == 0) 230 * From spec: PLL output musn't exceed max rate 231 */ 232 rate = clk_get_rate(priv->aclk); 233 if (!rate) { 234 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 235 return -EINVAL; 236 } 237 238 /* If duty is an error, kindly use at least /2 divider */ 239 duty = clk_get_scaled_duty_cycle(priv->aclk, 100); 240 if (duty < 0) 241 dev_warn(&pdev->dev, "adc clock duty: %d\n", duty); 242 243 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 244 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 245 presc = stm32h7_adc_ckmodes_spec[i].presc; 246 div = stm32h7_adc_ckmodes_spec[i].div; 247 248 if (ckmode) 249 continue; 250 251 /* 252 * For proper operation, clock duty cycle range is 49% 253 * to 51%. Apply at least /2 prescaler otherwise. 254 */ 255 if (div == 1 && (duty < 49 || duty > 51)) 256 continue; 257 258 if ((rate / div) <= priv->max_clk_rate) 259 goto out; 260 } 261 } 262 263 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 264 rate = clk_get_rate(priv->bclk); 265 if (!rate) { 266 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 267 return -EINVAL; 268 } 269 270 duty = clk_get_scaled_duty_cycle(priv->bclk, 100); 271 if (duty < 0) 272 dev_warn(&pdev->dev, "bus clock duty: %d\n", duty); 273 274 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 275 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 276 presc = stm32h7_adc_ckmodes_spec[i].presc; 277 div = stm32h7_adc_ckmodes_spec[i].div; 278 279 if (!ckmode) 280 continue; 281 282 if (div == 1 && (duty < 49 || duty > 51)) 283 continue; 284 285 if ((rate / div) <= priv->max_clk_rate) 286 goto out; 287 } 288 289 dev_err(&pdev->dev, "adc clk selection failed\n"); 290 return -EINVAL; 291 292 out: 293 /* rate used later by each ADC instance to control BOOST mode */ 294 priv->common.rate = rate / div; 295 296 /* Set common clock mode and prescaler */ 297 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 298 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 299 val |= ckmode << STM32H7_CKMODE_SHIFT; 300 val |= presc << STM32H7_PRESC_SHIFT; 301 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 302 303 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 304 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 305 306 return 0; 307 } 308 309 /* STM32F4 common registers definitions */ 310 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 311 .csr = STM32F4_ADC_CSR, 312 .ccr = STM32F4_ADC_CCR, 313 .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3 }, 314 .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3 }, 315 .ier = STM32F4_ADC_CR1, 316 .eocie_msk = STM32F4_EOCIE, 317 }; 318 319 /* STM32H7 common registers definitions */ 320 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 321 .csr = STM32H7_ADC_CSR, 322 .ccr = STM32H7_ADC_CCR, 323 .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV }, 324 .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV }, 325 .ier = STM32H7_ADC_IER, 326 .eocie_msk = STM32H7_EOCIE, 327 }; 328 329 /* STM32MP13 common registers definitions */ 330 static const struct stm32_adc_common_regs stm32mp13_adc_common_regs = { 331 .csr = STM32H7_ADC_CSR, 332 .ccr = STM32H7_ADC_CCR, 333 .eoc_msk = { STM32H7_EOC_MST }, 334 .ovr_msk = { STM32H7_OVR_MST }, 335 .ier = STM32H7_ADC_IER, 336 .eocie_msk = STM32H7_EOCIE, 337 }; 338 339 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { 340 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, 341 }; 342 343 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, 344 unsigned int adc) 345 { 346 u32 ier, offset = stm32_adc_offset[adc]; 347 348 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); 349 350 return ier & priv->cfg->regs->eocie_msk; 351 } 352 353 /* ADC common interrupt for all instances */ 354 static void stm32_adc_irq_handler(struct irq_desc *desc) 355 { 356 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 357 struct irq_chip *chip = irq_desc_get_chip(desc); 358 int i; 359 u32 status; 360 361 chained_irq_enter(chip, desc); 362 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 363 364 /* 365 * End of conversion may be handled by using IRQ or DMA. There may be a 366 * race here when two conversions complete at the same time on several 367 * ADCs. EOC may be read 'set' for several ADCs, with: 368 * - an ADC configured to use DMA (EOC triggers the DMA request, and 369 * is then automatically cleared by DR read in hardware) 370 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must 371 * be called in this case) 372 * So both EOC status bit in CSR and EOCIE control bit must be checked 373 * before invoking the interrupt handler (e.g. call ISR only for 374 * IRQ-enabled ADCs). 375 */ 376 for (i = 0; i < priv->nb_adc_max; i++) { 377 if ((status & priv->cfg->regs->eoc_msk[i] && 378 stm32_adc_eoc_enabled(priv, i)) || 379 (status & priv->cfg->regs->ovr_msk[i])) 380 generic_handle_domain_irq(priv->domain, i); 381 } 382 383 chained_irq_exit(chip, desc); 384 }; 385 386 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 387 irq_hw_number_t hwirq) 388 { 389 irq_set_chip_data(irq, d->host_data); 390 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 391 392 return 0; 393 } 394 395 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 396 { 397 irq_set_chip_and_handler(irq, NULL, NULL); 398 irq_set_chip_data(irq, NULL); 399 } 400 401 static const struct irq_domain_ops stm32_adc_domain_ops = { 402 .map = stm32_adc_domain_map, 403 .unmap = stm32_adc_domain_unmap, 404 .xlate = irq_domain_xlate_onecell, 405 }; 406 407 static int stm32_adc_irq_probe(struct platform_device *pdev, 408 struct stm32_adc_priv *priv) 409 { 410 unsigned int i; 411 412 /* 413 * Interrupt(s) must be provided, depending on the compatible: 414 * - stm32f4/h7 shares a common interrupt line. 415 * - stm32mp1, has one line per ADC 416 */ 417 for (i = 0; i < priv->cfg->num_irqs; i++) { 418 priv->irq[i] = platform_get_irq(pdev, i); 419 if (priv->irq[i] < 0) 420 return priv->irq[i]; 421 } 422 423 priv->domain = irq_domain_create_simple(dev_fwnode(&pdev->dev), 424 STM32_ADC_MAX_ADCS, 0, 425 &stm32_adc_domain_ops, 426 priv); 427 if (!priv->domain) { 428 dev_err(&pdev->dev, "Failed to add irq domain\n"); 429 return -ENOMEM; 430 } 431 432 for (i = 0; i < priv->cfg->num_irqs; i++) 433 irq_set_chained_handler_and_data(priv->irq[i], 434 stm32_adc_irq_handler, priv); 435 436 return 0; 437 } 438 439 static void stm32_adc_irq_remove(struct platform_device *pdev, 440 struct stm32_adc_priv *priv) 441 { 442 int hwirq; 443 unsigned int i; 444 445 for (hwirq = 0; hwirq < priv->nb_adc_max; hwirq++) 446 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 447 irq_domain_remove(priv->domain); 448 449 for (i = 0; i < priv->cfg->num_irqs; i++) 450 irq_set_chained_handler(priv->irq[i], NULL); 451 } 452 453 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, 454 struct device *dev) 455 { 456 int ret; 457 458 /* 459 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog 460 * switches (via PCSEL) which have reduced performances when their 461 * supply is below 2.7V (vdda by default): 462 * - Voltage booster can be used, to get full ADC performances 463 * (increases power consumption). 464 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). 465 * 466 * Recommended settings for ANASWVDD and EN_BOOSTER: 467 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) 468 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 469 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) 470 */ 471 if (priv->vdda_uv < 2700000) { 472 if (priv->syscfg && priv->vdd_uv > 2700000) { 473 ret = regulator_enable(priv->vdd); 474 if (ret < 0) { 475 dev_err(dev, "vdd enable failed %d\n", ret); 476 return ret; 477 } 478 479 ret = regmap_write(priv->syscfg, 480 STM32MP1_SYSCFG_PMCSETR, 481 STM32MP1_SYSCFG_ANASWVDD_MASK); 482 if (ret < 0) { 483 regulator_disable(priv->vdd); 484 dev_err(dev, "vdd select failed, %d\n", ret); 485 return ret; 486 } 487 dev_dbg(dev, "analog switches supplied by vdd\n"); 488 489 return 0; 490 } 491 492 if (priv->booster) { 493 /* 494 * This is optional, as this is a trade-off between 495 * analog performance and power consumption. 496 */ 497 ret = regulator_enable(priv->booster); 498 if (ret < 0) { 499 dev_err(dev, "booster enable failed %d\n", ret); 500 return ret; 501 } 502 dev_dbg(dev, "analog switches supplied by booster\n"); 503 504 return 0; 505 } 506 } 507 508 /* Fallback using vdda (default), nothing to do */ 509 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n", 510 priv->vdda_uv); 511 512 return 0; 513 } 514 515 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv) 516 { 517 if (priv->vdda_uv < 2700000) { 518 if (priv->syscfg && priv->vdd_uv > 2700000) { 519 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, 520 STM32MP1_SYSCFG_ANASWVDD_MASK); 521 regulator_disable(priv->vdd); 522 return; 523 } 524 if (priv->booster) 525 regulator_disable(priv->booster); 526 } 527 } 528 529 static int stm32_adc_core_hw_start(struct device *dev) 530 { 531 struct stm32_adc_common *common = dev_get_drvdata(dev); 532 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 533 int ret; 534 535 ret = regulator_enable(priv->vdda); 536 if (ret < 0) { 537 dev_err(dev, "vdda enable failed %d\n", ret); 538 return ret; 539 } 540 541 ret = regulator_get_voltage(priv->vdda); 542 if (ret < 0) { 543 dev_err(dev, "vdda get voltage failed, %d\n", ret); 544 goto err_vdda_disable; 545 } 546 priv->vdda_uv = ret; 547 548 ret = stm32_adc_core_switches_supply_en(priv, dev); 549 if (ret < 0) 550 goto err_vdda_disable; 551 552 ret = regulator_enable(priv->vref); 553 if (ret < 0) { 554 dev_err(dev, "vref enable failed\n"); 555 goto err_switches_dis; 556 } 557 558 ret = clk_prepare_enable(priv->bclk); 559 if (ret < 0) { 560 dev_err(dev, "bus clk enable failed\n"); 561 goto err_regulator_disable; 562 } 563 564 ret = clk_prepare_enable(priv->aclk); 565 if (ret < 0) { 566 dev_err(dev, "adc clk enable failed\n"); 567 goto err_bclk_disable; 568 } 569 570 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 571 572 return 0; 573 574 err_bclk_disable: 575 clk_disable_unprepare(priv->bclk); 576 err_regulator_disable: 577 regulator_disable(priv->vref); 578 err_switches_dis: 579 stm32_adc_core_switches_supply_dis(priv); 580 err_vdda_disable: 581 regulator_disable(priv->vdda); 582 583 return ret; 584 } 585 586 static void stm32_adc_core_hw_stop(struct device *dev) 587 { 588 struct stm32_adc_common *common = dev_get_drvdata(dev); 589 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 590 591 /* Backup CCR that may be lost (depends on power state to achieve) */ 592 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 593 clk_disable_unprepare(priv->aclk); 594 clk_disable_unprepare(priv->bclk); 595 regulator_disable(priv->vref); 596 stm32_adc_core_switches_supply_dis(priv); 597 regulator_disable(priv->vdda); 598 } 599 600 static int stm32_adc_core_switches_probe(struct device *dev, 601 struct stm32_adc_priv *priv) 602 { 603 struct device_node *np = dev->of_node; 604 int ret; 605 606 /* Analog switches supply can be controlled by syscfg (optional) */ 607 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 608 if (IS_ERR(priv->syscfg)) { 609 ret = PTR_ERR(priv->syscfg); 610 if (ret != -ENODEV) 611 return dev_err_probe(dev, ret, "Can't probe syscfg\n"); 612 613 priv->syscfg = NULL; 614 } 615 616 /* Booster can be used to supply analog switches (optional) */ 617 if (priv->cfg->has_syscfg & HAS_VBOOSTER) { 618 priv->booster = devm_regulator_get_optional(dev, "booster"); 619 if (IS_ERR(priv->booster)) { 620 ret = PTR_ERR(priv->booster); 621 if (ret != -ENODEV) 622 return dev_err_probe(dev, ret, "can't get booster\n"); 623 624 priv->booster = NULL; 625 } 626 } 627 628 /* Vdd can be used to supply analog switches (optional) */ 629 if (priv->cfg->has_syscfg & HAS_ANASWVDD) { 630 priv->vdd = devm_regulator_get_optional(dev, "vdd"); 631 if (IS_ERR(priv->vdd)) { 632 ret = PTR_ERR(priv->vdd); 633 if (ret != -ENODEV) 634 return dev_err_probe(dev, ret, "can't get vdd\n"); 635 636 priv->vdd = NULL; 637 } 638 } 639 640 if (priv->vdd) { 641 ret = regulator_enable(priv->vdd); 642 if (ret < 0) { 643 dev_err(dev, "vdd enable failed %d\n", ret); 644 return ret; 645 } 646 647 ret = regulator_get_voltage(priv->vdd); 648 if (ret < 0) { 649 dev_err(dev, "vdd get voltage failed %d\n", ret); 650 regulator_disable(priv->vdd); 651 return ret; 652 } 653 priv->vdd_uv = ret; 654 655 regulator_disable(priv->vdd); 656 } 657 658 return 0; 659 } 660 661 static int stm32_adc_probe_identification(struct platform_device *pdev, 662 struct stm32_adc_priv *priv) 663 { 664 struct device_node *np = pdev->dev.of_node; 665 struct device_node *child; 666 const char *compat; 667 int ret, count = 0; 668 u32 id, val; 669 670 if (!priv->cfg->ipid) 671 return 0; 672 673 id = FIELD_GET(STM32MP1_IPIDR_MASK, 674 readl_relaxed(priv->common.base + STM32MP1_ADC_IPDR)); 675 if (id != priv->cfg->ipid) { 676 dev_err(&pdev->dev, "Unexpected IP version: 0x%x", id); 677 return -EINVAL; 678 } 679 680 for_each_child_of_node(np, child) { 681 ret = of_property_read_string(child, "compatible", &compat); 682 if (ret) 683 continue; 684 /* Count child nodes with stm32 adc compatible */ 685 if (strstr(compat, "st,stm32") && strstr(compat, "adc")) 686 count++; 687 } 688 689 val = readl_relaxed(priv->common.base + STM32MP1_ADC_HWCFGR0); 690 priv->nb_adc_max = FIELD_GET(STM32MP1_ADCNUM_MASK, val); 691 if (count > priv->nb_adc_max) { 692 dev_err(&pdev->dev, "Unexpected child number: %d", count); 693 return -EINVAL; 694 } 695 696 val = readl_relaxed(priv->common.base + STM32MP1_ADC_VERR); 697 dev_dbg(&pdev->dev, "ADC version: %lu.%lu\n", 698 FIELD_GET(STM32MP1_MAJREV_MASK, val), 699 FIELD_GET(STM32MP1_MINREV_MASK, val)); 700 701 return 0; 702 } 703 704 static int stm32_adc_probe(struct platform_device *pdev) 705 { 706 struct stm32_adc_priv *priv; 707 struct device *dev = &pdev->dev; 708 struct device_node *np = pdev->dev.of_node; 709 struct resource *res; 710 u32 max_rate; 711 int ret; 712 713 if (!pdev->dev.of_node) 714 return -ENODEV; 715 716 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 717 if (!priv) 718 return -ENOMEM; 719 platform_set_drvdata(pdev, &priv->common); 720 721 priv->cfg = device_get_match_data(dev); 722 priv->nb_adc_max = priv->cfg->num_adcs; 723 spin_lock_init(&priv->common.lock); 724 725 priv->common.base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 726 if (IS_ERR(priv->common.base)) 727 return PTR_ERR(priv->common.base); 728 priv->common.phys_base = res->start; 729 730 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); 731 if (IS_ERR(priv->vdda)) 732 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda), 733 "vdda get failed\n"); 734 735 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 736 if (IS_ERR(priv->vref)) 737 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), 738 "vref get failed\n"); 739 740 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc"); 741 if (IS_ERR(priv->aclk)) 742 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk), 743 "Can't get 'adc' clock\n"); 744 745 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus"); 746 if (IS_ERR(priv->bclk)) 747 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk), 748 "Can't get 'bus' clock\n"); 749 750 ret = stm32_adc_core_switches_probe(dev, priv); 751 if (ret) 752 return ret; 753 754 pm_runtime_get_noresume(dev); 755 pm_runtime_set_active(dev); 756 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 757 pm_runtime_use_autosuspend(dev); 758 pm_runtime_enable(dev); 759 760 ret = stm32_adc_core_hw_start(dev); 761 if (ret) 762 goto err_pm_stop; 763 764 ret = stm32_adc_probe_identification(pdev, priv); 765 if (ret < 0) 766 goto err_hw_stop; 767 768 ret = regulator_get_voltage(priv->vref); 769 if (ret < 0) { 770 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 771 goto err_hw_stop; 772 } 773 priv->common.vref_mv = ret / 1000; 774 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 775 776 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz", 777 &max_rate); 778 if (!ret) 779 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz); 780 else 781 priv->max_clk_rate = priv->cfg->max_clk_rate_hz; 782 783 ret = priv->cfg->clk_sel(pdev, priv); 784 if (ret < 0) 785 goto err_hw_stop; 786 787 ret = stm32_adc_irq_probe(pdev, priv); 788 if (ret < 0) 789 goto err_hw_stop; 790 791 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 792 if (ret < 0) { 793 dev_err(&pdev->dev, "failed to populate DT children\n"); 794 goto err_irq_remove; 795 } 796 797 pm_runtime_mark_last_busy(dev); 798 pm_runtime_put_autosuspend(dev); 799 800 return 0; 801 802 err_irq_remove: 803 stm32_adc_irq_remove(pdev, priv); 804 err_hw_stop: 805 stm32_adc_core_hw_stop(dev); 806 err_pm_stop: 807 pm_runtime_disable(dev); 808 pm_runtime_set_suspended(dev); 809 pm_runtime_put_noidle(dev); 810 811 return ret; 812 } 813 814 static void stm32_adc_remove(struct platform_device *pdev) 815 { 816 struct stm32_adc_common *common = platform_get_drvdata(pdev); 817 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 818 819 pm_runtime_get_sync(&pdev->dev); 820 of_platform_depopulate(&pdev->dev); 821 stm32_adc_irq_remove(pdev, priv); 822 stm32_adc_core_hw_stop(&pdev->dev); 823 pm_runtime_disable(&pdev->dev); 824 pm_runtime_set_suspended(&pdev->dev); 825 pm_runtime_put_noidle(&pdev->dev); 826 } 827 828 static int stm32_adc_core_runtime_suspend(struct device *dev) 829 { 830 stm32_adc_core_hw_stop(dev); 831 832 return 0; 833 } 834 835 static int stm32_adc_core_runtime_resume(struct device *dev) 836 { 837 return stm32_adc_core_hw_start(dev); 838 } 839 840 static int stm32_adc_core_runtime_idle(struct device *dev) 841 { 842 pm_runtime_mark_last_busy(dev); 843 844 return 0; 845 } 846 847 static DEFINE_RUNTIME_DEV_PM_OPS(stm32_adc_core_pm_ops, 848 stm32_adc_core_runtime_suspend, 849 stm32_adc_core_runtime_resume, 850 stm32_adc_core_runtime_idle); 851 852 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 853 .regs = &stm32f4_adc_common_regs, 854 .clk_sel = stm32f4_adc_clk_sel, 855 .max_clk_rate_hz = 36000000, 856 .num_irqs = 1, 857 .num_adcs = 3, 858 }; 859 860 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 861 .regs = &stm32h7_adc_common_regs, 862 .clk_sel = stm32h7_adc_clk_sel, 863 .max_clk_rate_hz = 36000000, 864 .has_syscfg = HAS_VBOOSTER, 865 .num_irqs = 1, 866 .num_adcs = 2, 867 }; 868 869 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 870 .regs = &stm32h7_adc_common_regs, 871 .clk_sel = stm32h7_adc_clk_sel, 872 .max_clk_rate_hz = 36000000, 873 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, 874 .ipid = STM32MP15_IPIDR_NUMBER, 875 .num_irqs = 2, 876 }; 877 878 static const struct stm32_adc_priv_cfg stm32mp13_adc_priv_cfg = { 879 .regs = &stm32mp13_adc_common_regs, 880 .clk_sel = stm32h7_adc_clk_sel, 881 .max_clk_rate_hz = 75 * HZ_PER_MHZ, 882 .ipid = STM32MP13_IPIDR_NUMBER, 883 .num_irqs = 1, 884 }; 885 886 static const struct of_device_id stm32_adc_of_match[] = { 887 { 888 .compatible = "st,stm32f4-adc-core", 889 .data = (void *)&stm32f4_adc_priv_cfg 890 }, { 891 .compatible = "st,stm32h7-adc-core", 892 .data = (void *)&stm32h7_adc_priv_cfg 893 }, { 894 .compatible = "st,stm32mp1-adc-core", 895 .data = (void *)&stm32mp1_adc_priv_cfg 896 }, { 897 .compatible = "st,stm32mp13-adc-core", 898 .data = (void *)&stm32mp13_adc_priv_cfg 899 }, { 900 }, 901 }; 902 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 903 904 static struct platform_driver stm32_adc_driver = { 905 .probe = stm32_adc_probe, 906 .remove = stm32_adc_remove, 907 .driver = { 908 .name = "stm32-adc-core", 909 .of_match_table = stm32_adc_of_match, 910 .pm = pm_ptr(&stm32_adc_core_pm_ops), 911 }, 912 }; 913 module_platform_driver(stm32_adc_driver); 914 915 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 916 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 917 MODULE_LICENSE("GPL v2"); 918 MODULE_ALIAS("platform:stm32-adc-core"); 919