1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ST SPEAr ADC driver 4 * 5 * Copyright 2012 Stefan Roese <sr@denx.de> 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/dev_printk.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/math.h> 18 #include <linux/module.h> 19 #include <linux/mutex.h> 20 #include <linux/platform_device.h> 21 #include <linux/property.h> 22 #include <linux/types.h> 23 24 #include <linux/iio/iio.h> 25 #include <linux/iio/types.h> 26 27 /* SPEAR registers definitions */ 28 #define SPEAR600_ADC_SCAN_RATE_LO(x) ((x) & 0xFFFF) 29 #define SPEAR600_ADC_SCAN_RATE_HI(x) (((x) >> 0x10) & 0xFFFF) 30 #define SPEAR_ADC_CLK_LOW(x) (((x) & 0xf) << 0) 31 #define SPEAR_ADC_CLK_HIGH(x) (((x) & 0xf) << 4) 32 33 /* Bit definitions for SPEAR_ADC_STATUS */ 34 #define SPEAR_ADC_STATUS_START_CONVERSION BIT(0) 35 #define SPEAR_ADC_STATUS_CHANNEL_NUM_MASK GENMASK(3, 1) 36 #define SPEAR_ADC_STATUS_ADC_ENABLE BIT(4) 37 #define SPEAR_ADC_STATUS_AVG_SAMPLE_MASK GENMASK(8, 5) 38 #define SPEAR_ADC_STATUS_VREF_INTERNAL BIT(9) 39 40 #define SPEAR_ADC_DATA_MASK 0x03ff 41 #define SPEAR_ADC_DATA_BITS 10 42 43 #define SPEAR_ADC_MOD_NAME "spear-adc" 44 45 #define SPEAR_ADC_CHANNEL_NUM 8 46 47 #define SPEAR_ADC_CLK_MIN 2500000 48 #define SPEAR_ADC_CLK_MAX 20000000 49 50 struct adc_regs_spear3xx { 51 u32 status; 52 u32 average; 53 u32 scan_rate; 54 u32 clk; /* Not avail for 1340 & 1310 */ 55 u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM]; 56 u32 ch_data[SPEAR_ADC_CHANNEL_NUM]; 57 }; 58 59 struct chan_data { 60 u32 lsb; 61 u32 msb; 62 }; 63 64 struct adc_regs_spear6xx { 65 u32 status; 66 u32 pad[2]; 67 u32 clk; 68 u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM]; 69 struct chan_data ch_data[SPEAR_ADC_CHANNEL_NUM]; 70 u32 scan_rate_lo; 71 u32 scan_rate_hi; 72 struct chan_data average; 73 }; 74 75 struct spear_adc_state { 76 struct device *dev; 77 struct adc_regs_spear3xx __iomem *adc_base_spear3xx; 78 struct adc_regs_spear6xx __iomem *adc_base_spear6xx; 79 struct clk *clk; 80 struct completion completion; 81 /* 82 * Lock to protect the device state during a potential concurrent 83 * read access from userspace. Reading a raw value requires a sequence 84 * of register writes, then a wait for a completion callback, 85 * and finally a register read, during which userspace could issue 86 * another read request. This lock protects a read access from 87 * occurring before another one has finished. 88 */ 89 struct mutex lock; 90 u32 current_clk; 91 u32 sampling_freq; 92 u32 avg_samples; 93 u32 vref_external; 94 u32 value; 95 }; 96 97 /* 98 * Functions to access some SPEAr ADC register. Abstracted into 99 * static inline functions, because of different register offsets 100 * on different SoC variants (SPEAr300 vs SPEAr600 etc). 101 */ 102 static void spear_adc_set_status(struct spear_adc_state *st, u32 val) 103 { 104 __raw_writel(val, &st->adc_base_spear6xx->status); 105 } 106 107 static void spear_adc_set_clk(struct spear_adc_state *st, u32 val) 108 { 109 u32 clk_high, clk_low, count; 110 u32 apb_clk = clk_get_rate(st->clk); 111 112 count = DIV_ROUND_UP(apb_clk, val); 113 clk_low = count / 2; 114 clk_high = count - clk_low; 115 st->current_clk = apb_clk / count; 116 117 __raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high), 118 &st->adc_base_spear6xx->clk); 119 } 120 121 static void spear_adc_set_ctrl(struct spear_adc_state *st, int n, 122 u32 val) 123 { 124 __raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]); 125 } 126 127 static u32 spear_adc_get_average(struct spear_adc_state *st) 128 { 129 if (device_is_compatible(st->dev, "st,spear600-adc")) { 130 return __raw_readl(&st->adc_base_spear6xx->average.msb) & 131 SPEAR_ADC_DATA_MASK; 132 } else { 133 return __raw_readl(&st->adc_base_spear3xx->average) & 134 SPEAR_ADC_DATA_MASK; 135 } 136 } 137 138 static void spear_adc_set_scanrate(struct spear_adc_state *st, u32 rate) 139 { 140 if (device_is_compatible(st->dev, "st,spear600-adc")) { 141 __raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate), 142 &st->adc_base_spear6xx->scan_rate_lo); 143 __raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate), 144 &st->adc_base_spear6xx->scan_rate_hi); 145 } else { 146 __raw_writel(rate, &st->adc_base_spear3xx->scan_rate); 147 } 148 } 149 150 static int spear_adc_read_raw(struct iio_dev *indio_dev, 151 struct iio_chan_spec const *chan, 152 int *val, 153 int *val2, 154 long mask) 155 { 156 struct spear_adc_state *st = iio_priv(indio_dev); 157 u32 status; 158 159 switch (mask) { 160 case IIO_CHAN_INFO_RAW: 161 mutex_lock(&st->lock); 162 163 status = FIELD_PREP(SPEAR_ADC_STATUS_CHANNEL_NUM_MASK, chan->channel) | 164 FIELD_PREP(SPEAR_ADC_STATUS_AVG_SAMPLE_MASK, st->avg_samples) | 165 SPEAR_ADC_STATUS_START_CONVERSION | 166 SPEAR_ADC_STATUS_ADC_ENABLE; 167 if (st->vref_external == 0) 168 status |= SPEAR_ADC_STATUS_VREF_INTERNAL; 169 170 spear_adc_set_status(st, status); 171 wait_for_completion(&st->completion); /* set by ISR */ 172 *val = st->value; 173 174 mutex_unlock(&st->lock); 175 176 return IIO_VAL_INT; 177 178 case IIO_CHAN_INFO_SCALE: 179 *val = st->vref_external; 180 *val2 = SPEAR_ADC_DATA_BITS; 181 return IIO_VAL_FRACTIONAL_LOG2; 182 case IIO_CHAN_INFO_SAMP_FREQ: 183 *val = st->current_clk; 184 return IIO_VAL_INT; 185 } 186 187 return -EINVAL; 188 } 189 190 static int spear_adc_write_raw(struct iio_dev *indio_dev, 191 struct iio_chan_spec const *chan, 192 int val, 193 int val2, 194 long mask) 195 { 196 struct spear_adc_state *st = iio_priv(indio_dev); 197 int ret = 0; 198 199 if (mask != IIO_CHAN_INFO_SAMP_FREQ) 200 return -EINVAL; 201 202 mutex_lock(&st->lock); 203 204 if ((val < SPEAR_ADC_CLK_MIN) || 205 (val > SPEAR_ADC_CLK_MAX) || 206 (val2 != 0)) { 207 ret = -EINVAL; 208 goto out; 209 } 210 211 spear_adc_set_clk(st, val); 212 213 out: 214 mutex_unlock(&st->lock); 215 return ret; 216 } 217 218 #define SPEAR_ADC_CHAN(idx) { \ 219 .type = IIO_VOLTAGE, \ 220 .indexed = 1, \ 221 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 222 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 223 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 224 .channel = idx, \ 225 } 226 227 static const struct iio_chan_spec spear_adc_iio_channels[] = { 228 SPEAR_ADC_CHAN(0), 229 SPEAR_ADC_CHAN(1), 230 SPEAR_ADC_CHAN(2), 231 SPEAR_ADC_CHAN(3), 232 SPEAR_ADC_CHAN(4), 233 SPEAR_ADC_CHAN(5), 234 SPEAR_ADC_CHAN(6), 235 SPEAR_ADC_CHAN(7), 236 }; 237 238 static irqreturn_t spear_adc_isr(int irq, void *dev_id) 239 { 240 struct spear_adc_state *st = dev_id; 241 242 /* Read value to clear IRQ */ 243 st->value = spear_adc_get_average(st); 244 complete(&st->completion); 245 246 return IRQ_HANDLED; 247 } 248 249 static int spear_adc_configure(struct spear_adc_state *st) 250 { 251 int i; 252 253 /* Reset ADC core */ 254 spear_adc_set_status(st, 0); 255 __raw_writel(0, &st->adc_base_spear6xx->clk); 256 for (i = 0; i < 8; i++) 257 spear_adc_set_ctrl(st, i, 0); 258 spear_adc_set_scanrate(st, 0); 259 260 spear_adc_set_clk(st, st->sampling_freq); 261 262 return 0; 263 } 264 265 static const struct iio_info spear_adc_info = { 266 .read_raw = &spear_adc_read_raw, 267 .write_raw = &spear_adc_write_raw, 268 }; 269 270 static int spear_adc_probe(struct platform_device *pdev) 271 { 272 struct device *dev = &pdev->dev; 273 struct spear_adc_state *st; 274 struct iio_dev *indio_dev = NULL; 275 int ret = -ENODEV; 276 int irq; 277 278 indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state)); 279 if (!indio_dev) 280 return -ENOMEM; 281 282 st = iio_priv(indio_dev); 283 st->dev = dev; 284 285 init_completion(&st->completion); 286 mutex_init(&st->lock); 287 288 /* 289 * SPEAr600 has a different register layout than other SPEAr SoC's 290 * (e.g. SPEAr3xx). Let's provide two register base addresses 291 * to support multi-arch kernels. 292 */ 293 st->adc_base_spear6xx = devm_platform_ioremap_resource(pdev, 0); 294 if (IS_ERR(st->adc_base_spear6xx)) 295 return PTR_ERR(st->adc_base_spear6xx); 296 297 st->adc_base_spear3xx = 298 (struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx; 299 300 st->clk = devm_clk_get_enabled(dev, NULL); 301 if (IS_ERR(st->clk)) 302 return dev_err_probe(dev, PTR_ERR(st->clk), 303 "failed enabling clock\n"); 304 305 irq = platform_get_irq(pdev, 0); 306 if (irq < 0) 307 return irq; 308 309 ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME, 310 st); 311 if (ret < 0) 312 return dev_err_probe(dev, ret, "failed requesting interrupt\n"); 313 314 if (device_property_read_u32(dev, "sampling-frequency", &st->sampling_freq)) 315 return dev_err_probe(dev, -EINVAL, 316 "sampling-frequency missing in DT\n"); 317 318 /* 319 * Optional avg_samples defaults to 0, resulting in single data 320 * conversion 321 */ 322 device_property_read_u32(dev, "average-samples", &st->avg_samples); 323 324 /* 325 * Optional vref_external defaults to 0, resulting in internal vref 326 * selection 327 */ 328 device_property_read_u32(dev, "vref-external", &st->vref_external); 329 330 spear_adc_configure(st); 331 332 indio_dev->name = SPEAR_ADC_MOD_NAME; 333 indio_dev->info = &spear_adc_info; 334 indio_dev->modes = INDIO_DIRECT_MODE; 335 indio_dev->channels = spear_adc_iio_channels; 336 indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels); 337 338 ret = devm_iio_device_register(dev, indio_dev); 339 if (ret) 340 return ret; 341 342 dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq); 343 344 return 0; 345 } 346 347 static const struct of_device_id spear_adc_dt_ids[] = { 348 { .compatible = "st,spear600-adc", }, 349 { } 350 }; 351 MODULE_DEVICE_TABLE(of, spear_adc_dt_ids); 352 353 static struct platform_driver spear_adc_driver = { 354 .probe = spear_adc_probe, 355 .driver = { 356 .name = SPEAR_ADC_MOD_NAME, 357 .of_match_table = spear_adc_dt_ids, 358 }, 359 }; 360 361 module_platform_driver(spear_adc_driver); 362 363 MODULE_AUTHOR("Stefan Roese <sr@denx.de>"); 364 MODULE_DESCRIPTION("SPEAr ADC driver"); 365 MODULE_LICENSE("GPL"); 366