1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/G2L A/D Converter driver 4 * 5 * Copyright (c) 2021 Renesas Electronics Europe GmbH 6 * 7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/cleanup.h> 12 #include <linux/completion.h> 13 #include <linux/delay.h> 14 #include <linux/iio/iio.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/property.h> 23 #include <linux/reset.h> 24 25 #define DRIVER_NAME "rzg2l-adc" 26 27 #define RZG2L_ADM(n) ((n) * 0x4) 28 #define RZG2L_ADM0_ADCE BIT(0) 29 #define RZG2L_ADM0_ADBSY BIT(1) 30 #define RZG2L_ADM0_PWDWNB BIT(2) 31 #define RZG2L_ADM0_SRESB BIT(15) 32 #define RZG2L_ADM1_TRG BIT(0) 33 #define RZG2L_ADM1_MS BIT(2) 34 #define RZG2L_ADM1_BS BIT(4) 35 #define RZG2L_ADM1_EGA_MASK GENMASK(13, 12) 36 #define RZG2L_ADM3_ADIL_MASK GENMASK(31, 24) 37 #define RZG2L_ADM3_ADCMP_MASK GENMASK(23, 16) 38 39 #define RZG2L_ADINT 0x20 40 #define RZG2L_ADINT_CSEEN BIT(16) 41 #define RZG2L_ADINT_INTS BIT(31) 42 43 #define RZG2L_ADSTS 0x24 44 #define RZG2L_ADSTS_CSEST BIT(16) 45 46 #define RZG2L_ADIVC 0x28 47 #define RZG2L_ADIVC_DIVADC_MASK GENMASK(8, 0) 48 #define RZG2L_ADIVC_DIVADC_4 FIELD_PREP(RZG2L_ADIVC_DIVADC_MASK, 0x4) 49 50 #define RZG2L_ADFIL 0x2c 51 52 #define RZG2L_ADCR(n) (0x30 + ((n) * 0x4)) 53 #define RZG2L_ADCR_AD_MASK GENMASK(11, 0) 54 55 #define RZG2L_ADC_MAX_CHANNELS 9 56 #define RZG2L_ADC_TIMEOUT usecs_to_jiffies(1 * 4) 57 58 /** 59 * struct rzg2l_adc_hw_params - ADC hardware specific parameters 60 * @default_adsmp: default ADC sampling period (see ADM3 register); index 0 is 61 * used for voltage channels, index 1 is used for temperature channel 62 * @adsmp_mask: ADC sampling period mask (see ADM3 register) 63 * @adint_inten_mask: conversion end interrupt mask (see ADINT register) 64 * @default_adcmp: default ADC cmp (see ADM3 register) 65 * @num_channels: number of supported channels 66 * @adivc: specifies if ADVIC register is available 67 */ 68 struct rzg2l_adc_hw_params { 69 u16 default_adsmp[2]; 70 u16 adsmp_mask; 71 u16 adint_inten_mask; 72 u8 default_adcmp; 73 u8 num_channels; 74 bool adivc; 75 }; 76 77 struct rzg2l_adc_data { 78 const struct iio_chan_spec *channels; 79 u8 num_channels; 80 }; 81 82 struct rzg2l_adc { 83 void __iomem *base; 84 struct reset_control *presetn; 85 struct reset_control *adrstn; 86 const struct rzg2l_adc_data *data; 87 const struct rzg2l_adc_hw_params *hw_params; 88 struct completion completion; 89 struct mutex lock; 90 u16 last_val[RZG2L_ADC_MAX_CHANNELS]; 91 bool was_rpm_active; 92 }; 93 94 /** 95 * struct rzg2l_adc_channel - ADC channel descriptor 96 * @name: ADC channel name 97 * @type: ADC channel type 98 */ 99 struct rzg2l_adc_channel { 100 const char * const name; 101 enum iio_chan_type type; 102 }; 103 104 static const struct rzg2l_adc_channel rzg2l_adc_channels[] = { 105 { "adc0", IIO_VOLTAGE }, 106 { "adc1", IIO_VOLTAGE }, 107 { "adc2", IIO_VOLTAGE }, 108 { "adc3", IIO_VOLTAGE }, 109 { "adc4", IIO_VOLTAGE }, 110 { "adc5", IIO_VOLTAGE }, 111 { "adc6", IIO_VOLTAGE }, 112 { "adc7", IIO_VOLTAGE }, 113 { "adc8", IIO_TEMP }, 114 }; 115 116 static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg) 117 { 118 return readl(adc->base + reg); 119 } 120 121 static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val) 122 { 123 writel(val, adc->base + reg); 124 } 125 126 static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on) 127 { 128 u32 reg; 129 130 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); 131 if (on) 132 reg |= RZG2L_ADM0_PWDWNB; 133 else 134 reg &= ~RZG2L_ADM0_PWDWNB; 135 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); 136 udelay(2); 137 } 138 139 static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start) 140 { 141 int ret; 142 u32 reg; 143 144 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); 145 if (start) 146 reg |= RZG2L_ADM0_ADCE; 147 else 148 reg &= ~RZG2L_ADM0_ADCE; 149 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); 150 151 if (start) 152 return; 153 154 ret = read_poll_timeout(rzg2l_adc_readl, reg, !(reg & (RZG2L_ADM0_ADBSY | RZG2L_ADM0_ADCE)), 155 200, 1000, true, adc, RZG2L_ADM(0)); 156 if (ret) 157 pr_err("%s stopping ADC timed out\n", __func__); 158 } 159 160 static void rzg2l_set_trigger(struct rzg2l_adc *adc) 161 { 162 u32 reg; 163 164 /* 165 * Setup ADM1 for SW trigger 166 * EGA[13:12] - Set 00 to indicate hardware trigger is invalid 167 * BS[4] - Enable 1-buffer mode 168 * MS[1] - Enable Select mode 169 * TRG[0] - Enable software trigger mode 170 */ 171 reg = rzg2l_adc_readl(adc, RZG2L_ADM(1)); 172 reg &= ~RZG2L_ADM1_EGA_MASK; 173 reg &= ~RZG2L_ADM1_BS; 174 reg &= ~RZG2L_ADM1_TRG; 175 reg |= RZG2L_ADM1_MS; 176 rzg2l_adc_writel(adc, RZG2L_ADM(1), reg); 177 } 178 179 static u8 rzg2l_adc_ch_to_adsmp_index(u8 ch) 180 { 181 if (rzg2l_adc_channels[ch].type == IIO_VOLTAGE) 182 return 0; 183 184 return 1; 185 } 186 187 static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch) 188 { 189 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params; 190 u8 index = rzg2l_adc_ch_to_adsmp_index(ch); 191 u32 reg; 192 193 if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY) 194 return -EBUSY; 195 196 rzg2l_set_trigger(adc); 197 198 /* Select analog input channel subjected to conversion. */ 199 reg = rzg2l_adc_readl(adc, RZG2L_ADM(2)); 200 reg &= ~GENMASK(hw_params->num_channels - 1, 0); 201 reg |= BIT(ch); 202 rzg2l_adc_writel(adc, RZG2L_ADM(2), reg); 203 204 reg = rzg2l_adc_readl(adc, RZG2L_ADM(3)); 205 reg &= ~hw_params->adsmp_mask; 206 reg |= hw_params->default_adsmp[index]; 207 rzg2l_adc_writel(adc, RZG2L_ADM(3), reg); 208 209 /* 210 * Setup ADINT 211 * INTS[31] - Select pulse signal 212 * CSEEN[16] - Enable channel select error interrupt 213 * INTEN[7:0] - Select channel interrupt 214 */ 215 reg = rzg2l_adc_readl(adc, RZG2L_ADINT); 216 reg &= ~RZG2L_ADINT_INTS; 217 reg &= ~hw_params->adint_inten_mask; 218 reg |= (RZG2L_ADINT_CSEEN | BIT(ch)); 219 rzg2l_adc_writel(adc, RZG2L_ADINT, reg); 220 221 return 0; 222 } 223 224 static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch) 225 { 226 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params; 227 struct device *dev = indio_dev->dev.parent; 228 int ret; 229 230 ret = pm_runtime_resume_and_get(dev); 231 if (ret) 232 return ret; 233 234 ret = rzg2l_adc_conversion_setup(adc, ch); 235 if (ret) 236 goto rpm_put; 237 238 reinit_completion(&adc->completion); 239 240 rzg2l_adc_start_stop(adc, true); 241 242 if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) { 243 rzg2l_adc_writel(adc, RZG2L_ADINT, 244 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~hw_params->adint_inten_mask); 245 ret = -ETIMEDOUT; 246 } 247 248 rzg2l_adc_start_stop(adc, false); 249 250 rpm_put: 251 pm_runtime_mark_last_busy(dev); 252 pm_runtime_put_autosuspend(dev); 253 return ret; 254 } 255 256 static int rzg2l_adc_read_raw(struct iio_dev *indio_dev, 257 struct iio_chan_spec const *chan, 258 int *val, int *val2, long mask) 259 { 260 struct rzg2l_adc *adc = iio_priv(indio_dev); 261 int ret; 262 263 switch (mask) { 264 case IIO_CHAN_INFO_RAW: { 265 if (chan->type != IIO_VOLTAGE && chan->type != IIO_TEMP) 266 return -EINVAL; 267 268 guard(mutex)(&adc->lock); 269 270 ret = rzg2l_adc_conversion(indio_dev, adc, chan->channel); 271 if (ret) 272 return ret; 273 274 *val = adc->last_val[chan->channel]; 275 276 return IIO_VAL_INT; 277 } 278 279 default: 280 return -EINVAL; 281 } 282 } 283 284 static int rzg2l_adc_read_label(struct iio_dev *iio_dev, 285 const struct iio_chan_spec *chan, 286 char *label) 287 { 288 return sysfs_emit(label, "%s\n", rzg2l_adc_channels[chan->channel].name); 289 } 290 291 static const struct iio_info rzg2l_adc_iio_info = { 292 .read_raw = rzg2l_adc_read_raw, 293 .read_label = rzg2l_adc_read_label, 294 }; 295 296 static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id) 297 { 298 struct rzg2l_adc *adc = dev_id; 299 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params; 300 unsigned long intst; 301 u32 reg; 302 int ch; 303 304 reg = rzg2l_adc_readl(adc, RZG2L_ADSTS); 305 306 /* A/D conversion channel select error interrupt */ 307 if (reg & RZG2L_ADSTS_CSEST) { 308 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg); 309 return IRQ_HANDLED; 310 } 311 312 intst = reg & GENMASK(hw_params->num_channels - 1, 0); 313 if (!intst) 314 return IRQ_NONE; 315 316 for_each_set_bit(ch, &intst, hw_params->num_channels) 317 adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK; 318 319 /* clear the channel interrupt */ 320 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg); 321 322 complete(&adc->completion); 323 324 return IRQ_HANDLED; 325 } 326 327 static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc) 328 { 329 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params; 330 struct iio_chan_spec *chan_array; 331 struct rzg2l_adc_data *data; 332 unsigned int channel; 333 int num_channels; 334 int ret; 335 u8 i; 336 337 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 338 if (!data) 339 return -ENOMEM; 340 341 num_channels = device_get_child_node_count(&pdev->dev); 342 if (!num_channels) 343 return dev_err_probe(&pdev->dev, -ENODEV, "no channel children\n"); 344 345 if (num_channels > hw_params->num_channels) 346 return dev_err_probe(&pdev->dev, -EINVAL, 347 "num of channel children out of range\n"); 348 349 chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array), 350 GFP_KERNEL); 351 if (!chan_array) 352 return -ENOMEM; 353 354 i = 0; 355 device_for_each_child_node_scoped(&pdev->dev, fwnode) { 356 ret = fwnode_property_read_u32(fwnode, "reg", &channel); 357 if (ret) 358 return ret; 359 360 if (channel >= hw_params->num_channels) 361 return -EINVAL; 362 363 chan_array[i].type = rzg2l_adc_channels[channel].type; 364 chan_array[i].indexed = 1; 365 chan_array[i].channel = channel; 366 chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 367 chan_array[i].datasheet_name = rzg2l_adc_channels[channel].name; 368 i++; 369 } 370 371 data->num_channels = num_channels; 372 data->channels = chan_array; 373 adc->data = data; 374 375 return 0; 376 } 377 378 static int rzg2l_adc_hw_init(struct device *dev, struct rzg2l_adc *adc) 379 { 380 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params; 381 u32 reg; 382 int ret; 383 384 ret = pm_runtime_resume_and_get(dev); 385 if (ret) 386 return ret; 387 388 /* SW reset */ 389 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0)); 390 reg |= RZG2L_ADM0_SRESB; 391 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg); 392 393 ret = read_poll_timeout(rzg2l_adc_readl, reg, reg & RZG2L_ADM0_SRESB, 394 200, 1000, false, adc, RZG2L_ADM(0)); 395 if (ret) 396 goto exit_hw_init; 397 398 if (hw_params->adivc) { 399 /* Only division by 4 can be set */ 400 reg = rzg2l_adc_readl(adc, RZG2L_ADIVC); 401 reg &= ~RZG2L_ADIVC_DIVADC_MASK; 402 reg |= RZG2L_ADIVC_DIVADC_4; 403 rzg2l_adc_writel(adc, RZG2L_ADIVC, reg); 404 } 405 406 /* 407 * Setup AMD3 408 * ADIL[31:24] - Should be always set to 0 409 * ADCMP[23:16] - Should be always set to 0xe 410 * ADSMP[15:0] - Set default (0x578) sampling period 411 */ 412 reg = rzg2l_adc_readl(adc, RZG2L_ADM(3)); 413 reg &= ~RZG2L_ADM3_ADIL_MASK; 414 reg &= ~RZG2L_ADM3_ADCMP_MASK; 415 reg &= ~hw_params->adsmp_mask; 416 reg |= FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, hw_params->default_adcmp) | 417 hw_params->default_adsmp[0]; 418 419 rzg2l_adc_writel(adc, RZG2L_ADM(3), reg); 420 421 exit_hw_init: 422 pm_runtime_mark_last_busy(dev); 423 pm_runtime_put_autosuspend(dev); 424 return ret; 425 } 426 427 static int rzg2l_adc_probe(struct platform_device *pdev) 428 { 429 struct device *dev = &pdev->dev; 430 struct iio_dev *indio_dev; 431 struct rzg2l_adc *adc; 432 int ret; 433 int irq; 434 435 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 436 if (!indio_dev) 437 return -ENOMEM; 438 439 adc = iio_priv(indio_dev); 440 441 adc->hw_params = device_get_match_data(dev); 442 if (!adc->hw_params || adc->hw_params->num_channels > RZG2L_ADC_MAX_CHANNELS) 443 return -EINVAL; 444 445 ret = rzg2l_adc_parse_properties(pdev, adc); 446 if (ret) 447 return ret; 448 449 mutex_init(&adc->lock); 450 451 adc->base = devm_platform_ioremap_resource(pdev, 0); 452 if (IS_ERR(adc->base)) 453 return PTR_ERR(adc->base); 454 455 adc->adrstn = devm_reset_control_get_exclusive_deasserted(dev, "adrst-n"); 456 if (IS_ERR(adc->adrstn)) 457 return dev_err_probe(dev, PTR_ERR(adc->adrstn), 458 "failed to get/deassert adrst-n\n"); 459 460 adc->presetn = devm_reset_control_get_exclusive_deasserted(dev, "presetn"); 461 if (IS_ERR(adc->presetn)) 462 return dev_err_probe(dev, PTR_ERR(adc->presetn), 463 "failed to get/deassert presetn\n"); 464 465 pm_runtime_set_autosuspend_delay(dev, 300); 466 pm_runtime_use_autosuspend(dev); 467 ret = devm_pm_runtime_enable(dev); 468 if (ret) 469 return ret; 470 471 platform_set_drvdata(pdev, indio_dev); 472 473 ret = rzg2l_adc_hw_init(dev, adc); 474 if (ret) 475 return dev_err_probe(&pdev->dev, ret, 476 "failed to initialize ADC HW\n"); 477 478 irq = platform_get_irq(pdev, 0); 479 if (irq < 0) 480 return irq; 481 482 ret = devm_request_irq(dev, irq, rzg2l_adc_isr, 483 0, dev_name(dev), adc); 484 if (ret < 0) 485 return ret; 486 487 init_completion(&adc->completion); 488 489 indio_dev->name = DRIVER_NAME; 490 indio_dev->info = &rzg2l_adc_iio_info; 491 indio_dev->modes = INDIO_DIRECT_MODE; 492 indio_dev->channels = adc->data->channels; 493 indio_dev->num_channels = adc->data->num_channels; 494 495 return devm_iio_device_register(dev, indio_dev); 496 } 497 498 static const struct rzg2l_adc_hw_params rzg2l_hw_params = { 499 .num_channels = 8, 500 .default_adcmp = 0xe, 501 .default_adsmp = { 0x578 }, 502 .adsmp_mask = GENMASK(15, 0), 503 .adint_inten_mask = GENMASK(7, 0), 504 .adivc = true 505 }; 506 507 static const struct rzg2l_adc_hw_params rzg3s_hw_params = { 508 .num_channels = 9, 509 .default_adcmp = 0x1d, 510 .default_adsmp = { 0x7f, 0xff }, 511 .adsmp_mask = GENMASK(7, 0), 512 .adint_inten_mask = GENMASK(11, 0), 513 }; 514 515 static const struct of_device_id rzg2l_adc_match[] = { 516 { .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params }, 517 { .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params }, 518 { /* sentinel */ } 519 }; 520 MODULE_DEVICE_TABLE(of, rzg2l_adc_match); 521 522 static int rzg2l_adc_pm_runtime_suspend(struct device *dev) 523 { 524 struct iio_dev *indio_dev = dev_get_drvdata(dev); 525 struct rzg2l_adc *adc = iio_priv(indio_dev); 526 527 rzg2l_adc_pwr(adc, false); 528 529 return 0; 530 } 531 532 static int rzg2l_adc_pm_runtime_resume(struct device *dev) 533 { 534 struct iio_dev *indio_dev = dev_get_drvdata(dev); 535 struct rzg2l_adc *adc = iio_priv(indio_dev); 536 537 rzg2l_adc_pwr(adc, true); 538 539 return 0; 540 } 541 542 static int rzg2l_adc_suspend(struct device *dev) 543 { 544 struct iio_dev *indio_dev = dev_get_drvdata(dev); 545 struct rzg2l_adc *adc = iio_priv(indio_dev); 546 struct reset_control_bulk_data resets[] = { 547 { .rstc = adc->presetn }, 548 { .rstc = adc->adrstn }, 549 }; 550 int ret; 551 552 if (pm_runtime_suspended(dev)) { 553 adc->was_rpm_active = false; 554 } else { 555 ret = pm_runtime_force_suspend(dev); 556 if (ret) 557 return ret; 558 adc->was_rpm_active = true; 559 } 560 561 ret = reset_control_bulk_assert(ARRAY_SIZE(resets), resets); 562 if (ret) 563 goto rpm_restore; 564 565 return 0; 566 567 rpm_restore: 568 if (adc->was_rpm_active) 569 pm_runtime_force_resume(dev); 570 571 return ret; 572 } 573 574 static int rzg2l_adc_resume(struct device *dev) 575 { 576 struct iio_dev *indio_dev = dev_get_drvdata(dev); 577 struct rzg2l_adc *adc = iio_priv(indio_dev); 578 struct reset_control_bulk_data resets[] = { 579 { .rstc = adc->adrstn }, 580 { .rstc = adc->presetn }, 581 }; 582 int ret; 583 584 ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); 585 if (ret) 586 return ret; 587 588 if (adc->was_rpm_active) { 589 ret = pm_runtime_force_resume(dev); 590 if (ret) 591 goto resets_restore; 592 } 593 594 ret = rzg2l_adc_hw_init(dev, adc); 595 if (ret) 596 goto rpm_restore; 597 598 return 0; 599 600 rpm_restore: 601 if (adc->was_rpm_active) { 602 pm_runtime_mark_last_busy(dev); 603 pm_runtime_put_autosuspend(dev); 604 } 605 resets_restore: 606 reset_control_bulk_assert(ARRAY_SIZE(resets), resets); 607 return ret; 608 } 609 610 static const struct dev_pm_ops rzg2l_adc_pm_ops = { 611 RUNTIME_PM_OPS(rzg2l_adc_pm_runtime_suspend, rzg2l_adc_pm_runtime_resume, NULL) 612 SYSTEM_SLEEP_PM_OPS(rzg2l_adc_suspend, rzg2l_adc_resume) 613 }; 614 615 static struct platform_driver rzg2l_adc_driver = { 616 .probe = rzg2l_adc_probe, 617 .driver = { 618 .name = DRIVER_NAME, 619 .of_match_table = rzg2l_adc_match, 620 .pm = pm_ptr(&rzg2l_adc_pm_ops), 621 }, 622 }; 623 624 module_platform_driver(rzg2l_adc_driver); 625 626 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 627 MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver"); 628 MODULE_LICENSE("GPL v2"); 629