1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ROHM ADC driver for BD79124 ADC/GPO device 4 * https://fscdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bd79124muf-c-e.pdf 5 * 6 * Copyright (c) 2025, ROHM Semiconductor. 7 */ 8 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/bitmap.h> 12 #include <linux/bits.h> 13 #include <linux/device.h> 14 #include <linux/delay.h> 15 #include <linux/devm-helpers.h> 16 #include <linux/err.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/i2c.h> 19 #include <linux/interrupt.h> 20 #include <linux/irqreturn.h> 21 #include <linux/module.h> 22 #include <linux/mod_devicetable.h> 23 #include <linux/regmap.h> 24 #include <linux/types.h> 25 26 #include <asm/byteorder.h> 27 28 #include <linux/iio/events.h> 29 #include <linux/iio/iio.h> 30 #include <linux/iio/adc-helpers.h> 31 32 #define BD79124_I2C_MULTI_READ 0x30 33 #define BD79124_I2C_MULTI_WRITE 0x28 34 #define BD79124_REG_MAX 0xaf 35 36 #define BD79124_REG_SYSTEM_STATUS 0x00 37 #define BD79124_REG_GEN_CFG 0x01 38 #define BD79124_REG_OPMODE_CFG 0x04 39 #define BD79124_REG_PINCFG 0x05 40 #define BD79124_REG_GPO_VAL 0x0B 41 #define BD79124_REG_SEQ_CFG 0x10 42 #define BD79124_REG_MANUAL_CHANNELS 0x11 43 #define BD79124_REG_AUTO_CHANNELS 0x12 44 #define BD79124_REG_ALERT_CH_SEL 0x14 45 #define BD79124_REG_EVENT_FLAG 0x18 46 #define BD79124_REG_EVENT_FLAG_HI 0x1a 47 #define BD79124_REG_EVENT_FLAG_LO 0x1c 48 #define BD79124_REG_HYSTERESIS_CH0 0x20 49 #define BD79124_REG_EVENTCOUNT_CH0 0x22 50 #define BD79124_REG_RECENT_CH0_LSB 0xa0 51 #define BD79124_REG_RECENT_CH7_MSB 0xaf 52 53 #define BD79124_ADC_BITS 12 54 55 /* Masks for the BD79124_REG_OPMODE_CFG */ 56 #define BD79124_MSK_CONV_MODE GENMASK(6, 5) 57 #define BD79124_CONV_MODE_MANSEQ 0 58 #define BD79124_CONV_MODE_AUTO 1 59 #define BD79124_MSK_AUTO_INTERVAL GENMASK(1, 0) 60 #define BD79124_INTERVAL_750_US 0 61 62 /* Masks for the BD79124_REG_GEN_CFG */ 63 #define BD79124_MSK_DWC_EN BIT(4) 64 #define BD79124_MSK_STATS_EN BIT(5) 65 66 /* Masks for the BD79124_REG_SEQ_CFG */ 67 #define BD79124_MSK_SEQ_START BIT(4) 68 #define BD79124_MSK_SEQ_MODE GENMASK(1, 0) 69 #define BD79124_MSK_SEQ_MANUAL 0 70 #define BD79124_MSK_SEQ_SEQ 1 71 72 #define BD79124_MSK_HYSTERESIS GENMASK(3, 0) 73 #define BD79124_LOW_LIMIT_MIN 0 74 #define BD79124_HIGH_LIMIT_MAX GENMASK(11, 0) 75 76 /* 77 * The high limit, low limit and last measurement result are each stored in 78 * 2 consequtive registers. 4 bits are in the high bits of the first register 79 * and 8 bits in the next register. 80 * 81 * These macros return the address of the first reg for the given channel. 82 */ 83 #define BD79124_GET_HIGH_LIMIT_REG(ch) (BD79124_REG_HYSTERESIS_CH0 + (ch) * 4) 84 #define BD79124_GET_LOW_LIMIT_REG(ch) (BD79124_REG_EVENTCOUNT_CH0 + (ch) * 4) 85 #define BD79124_GET_LIMIT_REG(ch, dir) ((dir) == IIO_EV_DIR_RISING ? \ 86 BD79124_GET_HIGH_LIMIT_REG(ch) : BD79124_GET_LOW_LIMIT_REG(ch)) 87 #define BD79124_GET_RECENT_RES_REG(ch) (BD79124_REG_RECENT_CH0_LSB + (ch) * 2) 88 89 /* 90 * The hysteresis for a channel is stored in the same register where the 91 * 4 bits of high limit reside. 92 */ 93 #define BD79124_GET_HYSTERESIS_REG(ch) BD79124_GET_HIGH_LIMIT_REG(ch) 94 95 #define BD79124_MAX_NUM_CHANNELS 8 96 97 struct bd79124_data { 98 s64 timestamp; 99 struct regmap *map; 100 struct device *dev; 101 int vmax; 102 /* 103 * Keep measurement status so read_raw() knows if the measurement needs 104 * to be started. 105 */ 106 int alarm_monitored[BD79124_MAX_NUM_CHANNELS]; 107 /* 108 * The BD79124 does not allow disabling/enabling limit separately for 109 * one direction only. Hence, we do the disabling by changing the limit 110 * to maximum/minimum measurable value. This means we need to cache 111 * the limit in order to maintain it over the time limit is disabled. 112 */ 113 u16 alarm_r_limit[BD79124_MAX_NUM_CHANNELS]; 114 u16 alarm_f_limit[BD79124_MAX_NUM_CHANNELS]; 115 /* Bitmask of disabled events (for rate limiting) for each channel. */ 116 int alarm_suppressed[BD79124_MAX_NUM_CHANNELS]; 117 /* 118 * The BD79124 is configured to run the measurements in the background. 119 * This is done for the event monitoring as well as for the read_raw(). 120 * Protect the measurement starting/stopping using a mutex. 121 */ 122 struct mutex mutex; 123 struct delayed_work alm_enable_work; 124 struct gpio_chip gc; 125 u8 gpio_valid_mask; 126 }; 127 128 static const struct regmap_range bd79124_ro_ranges[] = { 129 regmap_reg_range(BD79124_REG_EVENT_FLAG, BD79124_REG_EVENT_FLAG), 130 regmap_reg_range(BD79124_REG_RECENT_CH0_LSB, BD79124_REG_RECENT_CH7_MSB), 131 }; 132 133 static const struct regmap_access_table bd79124_ro_regs = { 134 .no_ranges = &bd79124_ro_ranges[0], 135 .n_no_ranges = ARRAY_SIZE(bd79124_ro_ranges), 136 }; 137 138 static const struct regmap_range bd79124_volatile_ranges[] = { 139 regmap_reg_range(BD79124_REG_RECENT_CH0_LSB, BD79124_REG_RECENT_CH7_MSB), 140 regmap_reg_range(BD79124_REG_EVENT_FLAG, BD79124_REG_EVENT_FLAG), 141 regmap_reg_range(BD79124_REG_EVENT_FLAG_HI, BD79124_REG_EVENT_FLAG_HI), 142 regmap_reg_range(BD79124_REG_EVENT_FLAG_LO, BD79124_REG_EVENT_FLAG_LO), 143 regmap_reg_range(BD79124_REG_SYSTEM_STATUS, BD79124_REG_SYSTEM_STATUS), 144 }; 145 146 static const struct regmap_access_table bd79124_volatile_regs = { 147 .yes_ranges = &bd79124_volatile_ranges[0], 148 .n_yes_ranges = ARRAY_SIZE(bd79124_volatile_ranges), 149 }; 150 151 static const struct regmap_range bd79124_precious_ranges[] = { 152 regmap_reg_range(BD79124_REG_EVENT_FLAG_HI, BD79124_REG_EVENT_FLAG_HI), 153 regmap_reg_range(BD79124_REG_EVENT_FLAG_LO, BD79124_REG_EVENT_FLAG_LO), 154 }; 155 156 static const struct regmap_access_table bd79124_precious_regs = { 157 .yes_ranges = &bd79124_precious_ranges[0], 158 .n_yes_ranges = ARRAY_SIZE(bd79124_precious_ranges), 159 }; 160 161 static const struct regmap_config bd79124_regmap = { 162 .reg_bits = 16, 163 .val_bits = 8, 164 .read_flag_mask = BD79124_I2C_MULTI_READ, 165 .write_flag_mask = BD79124_I2C_MULTI_WRITE, 166 .max_register = BD79124_REG_MAX, 167 .cache_type = REGCACHE_MAPLE, 168 .volatile_table = &bd79124_volatile_regs, 169 .wr_table = &bd79124_ro_regs, 170 .precious_table = &bd79124_precious_regs, 171 }; 172 173 static int bd79124gpo_direction_get(struct gpio_chip *gc, unsigned int offset) 174 { 175 return GPIO_LINE_DIRECTION_OUT; 176 } 177 178 static int bd79124gpo_set(struct gpio_chip *gc, unsigned int offset, int value) 179 { 180 struct bd79124_data *data = gpiochip_get_data(gc); 181 182 return regmap_assign_bits(data->map, BD79124_REG_GPO_VAL, BIT(offset), 183 value); 184 } 185 186 static int bd79124gpo_set_multiple(struct gpio_chip *gc, unsigned long *mask, 187 unsigned long *bits) 188 { 189 unsigned int all_gpos; 190 int ret; 191 struct bd79124_data *data = gpiochip_get_data(gc); 192 193 /* 194 * Ensure all GPIOs in 'mask' are set to be GPIOs 195 * The valid_mask was not obeyed by the gpiolib in all cases prior the 196 * https://lore.kernel.org/all/cd5e067b80e1bb590027bc3bfa817e7f794f21c3.1741180097.git.mazziesaccount@gmail.com/ 197 * 198 * Keep this check here for a couple of cycles. 199 */ 200 ret = regmap_read(data->map, BD79124_REG_PINCFG, &all_gpos); 201 if (ret) 202 return ret; 203 204 if (all_gpos ^ *mask) { 205 dev_dbg(data->dev, "Invalid mux config. Can't set value.\n"); 206 207 return -EINVAL; 208 } 209 210 return regmap_update_bits(data->map, BD79124_REG_GPO_VAL, *mask, *bits); 211 } 212 213 static int bd79124_init_valid_mask(struct gpio_chip *gc, 214 unsigned long *valid_mask, 215 unsigned int ngpios) 216 { 217 struct bd79124_data *data = gpiochip_get_data(gc); 218 219 *valid_mask = data->gpio_valid_mask; 220 221 return 0; 222 } 223 224 /* Template for GPIO chip */ 225 static const struct gpio_chip bd79124gpo_chip = { 226 .label = "bd79124-gpo", 227 .get_direction = bd79124gpo_direction_get, 228 .set = bd79124gpo_set, 229 .set_multiple = bd79124gpo_set_multiple, 230 .init_valid_mask = bd79124_init_valid_mask, 231 .can_sleep = true, 232 .ngpio = 8, 233 .base = -1, 234 }; 235 236 struct bd79124_raw { 237 u8 val_bit3_0; /* Is set in high bits of the byte */ 238 u8 val_bit11_4; 239 }; 240 #define BD79124_RAW_TO_INT(r) ((r.val_bit11_4 << 4) | (r.val_bit3_0 >> 4)) 241 #define BD79124_INT_TO_RAW(val) { \ 242 .val_bit11_4 = (val) >> 4, \ 243 .val_bit3_0 = (val) << 4, \ 244 } 245 246 /* 247 * The high and low limits as well as the recent result values are stored in 248 * the same way in 2 consequent registers. The first register contains 4 bits 249 * of the value. These bits are stored in the high bits [7:4] of register, but 250 * they represent the low bits [3:0] of the value. 251 * The value bits [11:4] are stored in the next register. 252 * 253 * Read data from register and convert to integer. 254 */ 255 static int bd79124_read_reg_to_int(struct bd79124_data *data, int reg, 256 unsigned int *val) 257 { 258 int ret; 259 struct bd79124_raw raw; 260 261 ret = regmap_bulk_read(data->map, reg, &raw, sizeof(raw)); 262 if (ret) { 263 dev_dbg(data->dev, "bulk_read failed %d\n", ret); 264 265 return ret; 266 } 267 268 *val = BD79124_RAW_TO_INT(raw); 269 270 return 0; 271 } 272 273 /* 274 * The high and low limits as well as the recent result values are stored in 275 * the same way in 2 consequent registers. The first register contains 4 bits 276 * of the value. These bits are stored in the high bits [7:4] of register, but 277 * they represent the low bits [3:0] of the value. 278 * The value bits [11:4] are stored in the next register. 279 * 280 * Convert the integer to register format and write it using rmw cycle. 281 */ 282 static int bd79124_write_int_to_reg(struct bd79124_data *data, int reg, 283 unsigned int val) 284 { 285 struct bd79124_raw raw = BD79124_INT_TO_RAW(val); 286 unsigned int tmp; 287 int ret; 288 289 ret = regmap_read(data->map, reg, &tmp); 290 if (ret) 291 return ret; 292 293 raw.val_bit3_0 |= (tmp & 0xf); 294 295 return regmap_bulk_write(data->map, reg, &raw, sizeof(raw)); 296 } 297 298 static const struct iio_event_spec bd79124_events[] = { 299 { 300 .type = IIO_EV_TYPE_THRESH, 301 .dir = IIO_EV_DIR_RISING, 302 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 303 BIT(IIO_EV_INFO_ENABLE), 304 }, 305 { 306 .type = IIO_EV_TYPE_THRESH, 307 .dir = IIO_EV_DIR_FALLING, 308 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 309 BIT(IIO_EV_INFO_ENABLE), 310 }, 311 { 312 .type = IIO_EV_TYPE_THRESH, 313 .dir = IIO_EV_DIR_EITHER, 314 .mask_separate = BIT(IIO_EV_INFO_HYSTERESIS), 315 }, 316 }; 317 318 static const struct iio_chan_spec bd79124_chan_template_noirq = { 319 .type = IIO_VOLTAGE, 320 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 321 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 322 .indexed = 1, 323 }; 324 325 static const struct iio_chan_spec bd79124_chan_template = { 326 .type = IIO_VOLTAGE, 327 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 328 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 329 .indexed = 1, 330 .event_spec = bd79124_events, 331 .num_event_specs = ARRAY_SIZE(bd79124_events), 332 }; 333 334 static int bd79124_read_event_value(struct iio_dev *iio_dev, 335 const struct iio_chan_spec *chan, 336 enum iio_event_type type, 337 enum iio_event_direction dir, 338 enum iio_event_info info, int *val, 339 int *val2) 340 { 341 struct bd79124_data *data = iio_priv(iio_dev); 342 int ret, reg; 343 344 if (chan->channel >= BD79124_MAX_NUM_CHANNELS) 345 return -EINVAL; 346 347 switch (info) { 348 case IIO_EV_INFO_VALUE: 349 if (dir == IIO_EV_DIR_RISING) 350 *val = data->alarm_r_limit[chan->channel]; 351 else if (dir == IIO_EV_DIR_FALLING) 352 *val = data->alarm_f_limit[chan->channel]; 353 else 354 return -EINVAL; 355 356 return IIO_VAL_INT; 357 358 case IIO_EV_INFO_HYSTERESIS: 359 reg = BD79124_GET_HYSTERESIS_REG(chan->channel); 360 ret = regmap_read(data->map, reg, val); 361 if (ret) 362 return ret; 363 364 *val &= BD79124_MSK_HYSTERESIS; 365 /* 366 * The data-sheet says the hysteresis register value needs to be 367 * shifted left by 3. 368 */ 369 *val <<= 3; 370 371 return IIO_VAL_INT; 372 373 default: 374 return -EINVAL; 375 } 376 } 377 378 static int bd79124_start_measurement(struct bd79124_data *data, int chan) 379 { 380 unsigned int val, regval; 381 int ret; 382 383 /* See if already started */ 384 ret = regmap_read(data->map, BD79124_REG_AUTO_CHANNELS, &val); 385 if (val & BIT(chan)) 386 return 0; 387 388 /* 389 * The sequencer must be stopped when channels are added/removed from 390 * the list of the measured channels to ensure the new channel 391 * configuration is used. 392 */ 393 ret = regmap_clear_bits(data->map, BD79124_REG_SEQ_CFG, 394 BD79124_MSK_SEQ_START); 395 if (ret) 396 return ret; 397 398 ret = regmap_write(data->map, BD79124_REG_AUTO_CHANNELS, val | BIT(chan)); 399 if (ret) 400 return ret; 401 402 ret = regmap_set_bits(data->map, BD79124_REG_SEQ_CFG, 403 BD79124_MSK_SEQ_START); 404 if (ret) 405 return ret; 406 407 /* 408 * Start the measurement at the background. Don't bother checking if 409 * it was started, regmap has cache. 410 */ 411 regval = FIELD_PREP(BD79124_MSK_CONV_MODE, BD79124_CONV_MODE_AUTO); 412 413 return regmap_update_bits(data->map, BD79124_REG_OPMODE_CFG, 414 BD79124_MSK_CONV_MODE, regval); 415 } 416 417 static int bd79124_stop_measurement(struct bd79124_data *data, int chan) 418 { 419 unsigned int enabled_chans; 420 int ret; 421 422 /* See if already stopped */ 423 ret = regmap_read(data->map, BD79124_REG_AUTO_CHANNELS, &enabled_chans); 424 if (!(enabled_chans & BIT(chan))) 425 return 0; 426 427 ret = regmap_clear_bits(data->map, BD79124_REG_SEQ_CFG, 428 BD79124_MSK_SEQ_START); 429 430 /* Clear the channel from the measured channels */ 431 enabled_chans &= ~BIT(chan); 432 ret = regmap_write(data->map, BD79124_REG_AUTO_CHANNELS, 433 enabled_chans); 434 if (ret) 435 return ret; 436 437 /* 438 * Stop background conversion for power saving if it was the last 439 * channel. 440 */ 441 if (!enabled_chans) { 442 int regval = FIELD_PREP(BD79124_MSK_CONV_MODE, 443 BD79124_CONV_MODE_MANSEQ); 444 445 ret = regmap_update_bits(data->map, BD79124_REG_OPMODE_CFG, 446 BD79124_MSK_CONV_MODE, regval); 447 if (ret) 448 return ret; 449 } 450 451 return regmap_set_bits(data->map, BD79124_REG_SEQ_CFG, 452 BD79124_MSK_SEQ_START); 453 } 454 455 static int bd79124_read_event_config(struct iio_dev *iio_dev, 456 const struct iio_chan_spec *chan, 457 enum iio_event_type type, 458 enum iio_event_direction dir) 459 { 460 struct bd79124_data *data = iio_priv(iio_dev); 461 462 if (chan->channel >= BD79124_MAX_NUM_CHANNELS) 463 return -EINVAL; 464 465 return !!(data->alarm_monitored[chan->channel] & BIT(dir)); 466 } 467 468 static int bd79124_disable_event(struct bd79124_data *data, 469 enum iio_event_direction dir, int channel) 470 { 471 int dir_bit = BIT(dir); 472 int reg; 473 unsigned int limit; 474 475 guard(mutex)(&data->mutex); 476 477 /* 478 * Set thresholds either to 0 or to 2^12 - 1 as appropriate to prevent 479 * alerts and thus disable event generation. 480 */ 481 if (dir == IIO_EV_DIR_RISING) { 482 reg = BD79124_GET_HIGH_LIMIT_REG(channel); 483 limit = BD79124_HIGH_LIMIT_MAX; 484 } else if (dir == IIO_EV_DIR_FALLING) { 485 reg = BD79124_GET_LOW_LIMIT_REG(channel); 486 limit = BD79124_LOW_LIMIT_MIN; 487 } else { 488 return -EINVAL; 489 } 490 491 data->alarm_monitored[channel] &= ~dir_bit; 492 493 /* 494 * Stop measurement if there is no more events to monitor. 495 * We don't bother checking the retval because the limit 496 * setting should in any case effectively disable the alarm. 497 */ 498 if (!data->alarm_monitored[channel]) { 499 bd79124_stop_measurement(data, channel); 500 regmap_clear_bits(data->map, BD79124_REG_ALERT_CH_SEL, 501 BIT(channel)); 502 } 503 504 return bd79124_write_int_to_reg(data, reg, limit); 505 } 506 507 static int bd79124_enable_event(struct bd79124_data *data, 508 enum iio_event_direction dir, 509 unsigned int channel) 510 { 511 int dir_bit = BIT(dir); 512 int reg, ret; 513 u16 *limit; 514 515 guard(mutex)(&data->mutex); 516 ret = bd79124_start_measurement(data, channel); 517 if (ret) 518 return ret; 519 520 data->alarm_monitored[channel] |= dir_bit; 521 522 /* Add the channel to the list of monitored channels */ 523 ret = regmap_set_bits(data->map, BD79124_REG_ALERT_CH_SEL, BIT(channel)); 524 if (ret) 525 return ret; 526 527 if (dir == IIO_EV_DIR_RISING) { 528 limit = &data->alarm_f_limit[channel]; 529 reg = BD79124_GET_HIGH_LIMIT_REG(channel); 530 } else { 531 limit = &data->alarm_f_limit[channel]; 532 reg = BD79124_GET_LOW_LIMIT_REG(channel); 533 } 534 /* 535 * Don't write the new limit to the hardware if we are in the 536 * rate-limit period. The timer which re-enables the event will set 537 * the limit. 538 */ 539 if (!(data->alarm_suppressed[channel] & dir_bit)) { 540 ret = bd79124_write_int_to_reg(data, reg, *limit); 541 if (ret) 542 return ret; 543 } 544 545 /* 546 * Enable comparator. Trust the regmap cache, no need to check 547 * if it was already enabled. 548 * 549 * We could do this in the hw-init, but there may be users who 550 * never enable alarms and for them it makes sense to not 551 * enable the comparator at probe. 552 */ 553 return regmap_set_bits(data->map, BD79124_REG_GEN_CFG, 554 BD79124_MSK_DWC_EN); 555 } 556 557 static int bd79124_write_event_config(struct iio_dev *iio_dev, 558 const struct iio_chan_spec *chan, 559 enum iio_event_type type, 560 enum iio_event_direction dir, bool state) 561 { 562 struct bd79124_data *data = iio_priv(iio_dev); 563 564 if (chan->channel >= BD79124_MAX_NUM_CHANNELS) 565 return -EINVAL; 566 567 if (state) 568 return bd79124_enable_event(data, dir, chan->channel); 569 570 return bd79124_disable_event(data, dir, chan->channel); 571 } 572 573 static int bd79124_write_event_value(struct iio_dev *iio_dev, 574 const struct iio_chan_spec *chan, 575 enum iio_event_type type, 576 enum iio_event_direction dir, 577 enum iio_event_info info, int val, 578 int val2) 579 { 580 struct bd79124_data *data = iio_priv(iio_dev); 581 int reg; 582 583 if (chan->channel >= BD79124_MAX_NUM_CHANNELS) 584 return -EINVAL; 585 586 switch (info) { 587 case IIO_EV_INFO_VALUE: 588 { 589 guard(mutex)(&data->mutex); 590 591 if (dir == IIO_EV_DIR_RISING) { 592 data->alarm_r_limit[chan->channel] = val; 593 reg = BD79124_GET_HIGH_LIMIT_REG(chan->channel); 594 } else if (dir == IIO_EV_DIR_FALLING) { 595 data->alarm_f_limit[chan->channel] = val; 596 reg = BD79124_GET_LOW_LIMIT_REG(chan->channel); 597 } else { 598 return -EINVAL; 599 } 600 /* 601 * We don't want to enable the alarm if it is not enabled or 602 * if it is suppressed. In that case skip writing to the 603 * register. 604 */ 605 if (!(data->alarm_monitored[chan->channel] & BIT(dir)) || 606 data->alarm_suppressed[chan->channel] & BIT(dir)) 607 return 0; 608 609 return bd79124_write_int_to_reg(data, reg, val); 610 } 611 case IIO_EV_INFO_HYSTERESIS: 612 reg = BD79124_GET_HYSTERESIS_REG(chan->channel); 613 val >>= 3; 614 615 return regmap_update_bits(data->map, reg, BD79124_MSK_HYSTERESIS, 616 val); 617 default: 618 return -EINVAL; 619 } 620 } 621 622 static int bd79124_single_chan_seq(struct bd79124_data *data, int chan, unsigned int *old) 623 { 624 int ret; 625 626 ret = regmap_clear_bits(data->map, BD79124_REG_SEQ_CFG, 627 BD79124_MSK_SEQ_START); 628 if (ret) 629 return ret; 630 631 /* 632 * It may be we have some channels monitored for alarms so we want to 633 * cache the old config and return it when the single channel 634 * measurement has been completed. 635 */ 636 ret = regmap_read(data->map, BD79124_REG_AUTO_CHANNELS, old); 637 if (ret) 638 return ret; 639 640 ret = regmap_write(data->map, BD79124_REG_AUTO_CHANNELS, BIT(chan)); 641 if (ret) 642 return ret; 643 644 /* Restart the sequencer */ 645 return regmap_set_bits(data->map, BD79124_REG_SEQ_CFG, 646 BD79124_MSK_SEQ_START); 647 } 648 649 static int bd79124_single_chan_seq_end(struct bd79124_data *data, unsigned int old) 650 { 651 int ret; 652 653 ret = regmap_clear_bits(data->map, BD79124_REG_SEQ_CFG, 654 BD79124_MSK_SEQ_START); 655 if (ret) 656 return ret; 657 658 ret = regmap_write(data->map, BD79124_REG_AUTO_CHANNELS, old); 659 if (ret) 660 return ret; 661 662 return regmap_set_bits(data->map, BD79124_REG_SEQ_CFG, 663 BD79124_MSK_SEQ_START); 664 } 665 666 static int bd79124_read_raw(struct iio_dev *iio_dev, 667 struct iio_chan_spec const *chan, 668 int *val, int *val2, long m) 669 { 670 struct bd79124_data *data = iio_priv(iio_dev); 671 int ret; 672 673 if (chan->channel >= BD79124_MAX_NUM_CHANNELS) 674 return -EINVAL; 675 676 switch (m) { 677 case IIO_CHAN_INFO_RAW: 678 { 679 unsigned int old_chan_cfg, regval; 680 int tmp; 681 682 guard(mutex)(&data->mutex); 683 684 /* 685 * Start the automatic conversion. This is needed here if no 686 * events have been enabled. 687 */ 688 regval = FIELD_PREP(BD79124_MSK_CONV_MODE, 689 BD79124_CONV_MODE_AUTO); 690 ret = regmap_update_bits(data->map, BD79124_REG_OPMODE_CFG, 691 BD79124_MSK_CONV_MODE, regval); 692 if (ret) 693 return ret; 694 695 ret = bd79124_single_chan_seq(data, chan->channel, &old_chan_cfg); 696 if (ret) 697 return ret; 698 699 /* The maximum conversion time is 6 uS. */ 700 udelay(6); 701 702 ret = bd79124_read_reg_to_int(data, 703 BD79124_GET_RECENT_RES_REG(chan->channel), val); 704 /* 705 * Return the old chan config even if data reading failed in 706 * order to re-enable the event monitoring. 707 */ 708 tmp = bd79124_single_chan_seq_end(data, old_chan_cfg); 709 if (tmp) 710 dev_err(data->dev, 711 "Failed to return config. Alarms may be disabled\n"); 712 713 if (ret) 714 return ret; 715 716 return IIO_VAL_INT; 717 } 718 case IIO_CHAN_INFO_SCALE: 719 *val = data->vmax / 1000; 720 *val2 = BD79124_ADC_BITS; 721 return IIO_VAL_FRACTIONAL_LOG2; 722 default: 723 return -EINVAL; 724 } 725 } 726 727 static const struct iio_info bd79124_info = { 728 .read_raw = bd79124_read_raw, 729 .read_event_config = &bd79124_read_event_config, 730 .write_event_config = &bd79124_write_event_config, 731 .read_event_value = &bd79124_read_event_value, 732 .write_event_value = &bd79124_write_event_value, 733 }; 734 735 static void bd79124_re_enable_lo(struct bd79124_data *data, unsigned int channel) 736 { 737 int ret, evbit = BIT(IIO_EV_DIR_FALLING); 738 739 /* 740 * We should not re-enable the event if user has disabled it while 741 * rate-limiting was enabled. 742 */ 743 if (!(data->alarm_suppressed[channel] & evbit)) 744 return; 745 746 data->alarm_suppressed[channel] &= ~evbit; 747 748 if (!(data->alarm_monitored[channel] & evbit)) 749 return; 750 751 ret = bd79124_write_int_to_reg(data, BD79124_GET_LOW_LIMIT_REG(channel), 752 data->alarm_f_limit[channel]); 753 if (ret) 754 dev_warn(data->dev, "Low limit enabling failed for channel%d\n", 755 channel); 756 } 757 758 static void bd79124_re_enable_hi(struct bd79124_data *data, unsigned int channel) 759 { 760 int ret, evbit = BIT(IIO_EV_DIR_RISING); 761 762 /* 763 * We should not re-enable the event if user has disabled it while 764 * rate-limiting was enabled. 765 */ 766 if (!(data->alarm_suppressed[channel] & evbit)) 767 return; 768 769 data->alarm_suppressed[channel] &= ~evbit; 770 771 if (!(data->alarm_monitored[channel] & evbit)) 772 return; 773 774 ret = bd79124_write_int_to_reg(data, BD79124_GET_HIGH_LIMIT_REG(channel), 775 data->alarm_r_limit[channel]); 776 if (ret) 777 dev_warn(data->dev, "High limit enabling failed for channel%d\n", 778 channel); 779 } 780 781 static void bd79124_alm_enable_worker(struct work_struct *work) 782 { 783 int i; 784 struct bd79124_data *data = container_of(work, struct bd79124_data, 785 alm_enable_work.work); 786 787 /* Take the mutex so there is no race with user disabling the alarm */ 788 guard(mutex)(&data->mutex); 789 for (i = 0; i < BD79124_MAX_NUM_CHANNELS; i++) { 790 bd79124_re_enable_hi(data, i); 791 bd79124_re_enable_lo(data, i); 792 } 793 } 794 795 static int __bd79124_event_ratelimit(struct bd79124_data *data, int reg, 796 unsigned int limit) 797 { 798 int ret; 799 800 if (limit > BD79124_HIGH_LIMIT_MAX) 801 return -EINVAL; 802 803 ret = bd79124_write_int_to_reg(data, reg, limit); 804 if (ret) 805 return ret; 806 807 /* 808 * We use 1 sec 'grace period'. At the moment I see no reason to make 809 * this user configurable. We need an ABI for this if configuration is 810 * needed. 811 */ 812 schedule_delayed_work(&data->alm_enable_work, msecs_to_jiffies(1000)); 813 814 return 0; 815 } 816 817 static int bd79124_event_ratelimit_hi(struct bd79124_data *data, 818 unsigned int channel) 819 { 820 guard(mutex)(&data->mutex); 821 data->alarm_suppressed[channel] |= BIT(IIO_EV_DIR_RISING); 822 823 return __bd79124_event_ratelimit(data, 824 BD79124_GET_HIGH_LIMIT_REG(channel), 825 BD79124_HIGH_LIMIT_MAX); 826 } 827 828 static int bd79124_event_ratelimit_lo(struct bd79124_data *data, 829 unsigned int channel) 830 { 831 guard(mutex)(&data->mutex); 832 data->alarm_suppressed[channel] |= BIT(IIO_EV_DIR_FALLING); 833 834 return __bd79124_event_ratelimit(data, 835 BD79124_GET_LOW_LIMIT_REG(channel), 836 BD79124_LOW_LIMIT_MIN); 837 } 838 839 static irqreturn_t bd79124_event_handler(int irq, void *priv) 840 { 841 unsigned int i_hi, i_lo; 842 int i, ret; 843 struct iio_dev *iio_dev = priv; 844 struct bd79124_data *data = iio_priv(iio_dev); 845 846 /* 847 * Return IRQ_NONE if bailing-out without acking. This allows the IRQ 848 * subsystem to disable the offending IRQ line if we get a hardware 849 * problem. This behaviour has saved my poor bottom a few times in the 850 * past as, instead of getting unusably unresponsive, the system has 851 * spilled out the magic words "...nobody cared". 852 */ 853 ret = regmap_read(data->map, BD79124_REG_EVENT_FLAG_HI, &i_hi); 854 if (ret) 855 return IRQ_NONE; 856 857 ret = regmap_read(data->map, BD79124_REG_EVENT_FLAG_LO, &i_lo); 858 if (ret) 859 return IRQ_NONE; 860 861 if (!i_lo && !i_hi) 862 return IRQ_NONE; 863 864 for (i = 0; i < BD79124_MAX_NUM_CHANNELS; i++) { 865 u64 ecode; 866 867 if (BIT(i) & i_hi) { 868 ecode = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i, 869 IIO_EV_TYPE_THRESH, 870 IIO_EV_DIR_RISING); 871 872 iio_push_event(iio_dev, ecode, data->timestamp); 873 /* 874 * The BD79124 keeps the IRQ asserted for as long as 875 * the voltage exceeds the threshold. It causes the IRQ 876 * to keep firing. 877 * 878 * Disable the event for the channel and schedule the 879 * re-enabling the event later to prevent storm of 880 * events. 881 */ 882 ret = bd79124_event_ratelimit_hi(data, i); 883 if (ret) 884 return IRQ_NONE; 885 } 886 if (BIT(i) & i_lo) { 887 ecode = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i, 888 IIO_EV_TYPE_THRESH, 889 IIO_EV_DIR_FALLING); 890 891 iio_push_event(iio_dev, ecode, data->timestamp); 892 ret = bd79124_event_ratelimit_lo(data, i); 893 if (ret) 894 return IRQ_NONE; 895 } 896 } 897 898 ret = regmap_write(data->map, BD79124_REG_EVENT_FLAG_HI, i_hi); 899 if (ret) 900 return IRQ_NONE; 901 902 ret = regmap_write(data->map, BD79124_REG_EVENT_FLAG_LO, i_lo); 903 if (ret) 904 return IRQ_NONE; 905 906 return IRQ_HANDLED; 907 } 908 909 static irqreturn_t bd79124_irq_handler(int irq, void *priv) 910 { 911 struct iio_dev *iio_dev = priv; 912 struct bd79124_data *data = iio_priv(iio_dev); 913 914 data->timestamp = iio_get_time_ns(iio_dev); 915 916 return IRQ_WAKE_THREAD; 917 } 918 919 static int bd79124_chan_init(struct bd79124_data *data, int channel) 920 { 921 int ret; 922 923 ret = regmap_write(data->map, BD79124_GET_HIGH_LIMIT_REG(channel), 924 BD79124_HIGH_LIMIT_MAX); 925 if (ret) 926 return ret; 927 928 return regmap_write(data->map, BD79124_GET_LOW_LIMIT_REG(channel), 929 BD79124_LOW_LIMIT_MIN); 930 } 931 932 static int bd79124_get_gpio_pins(const struct iio_chan_spec *cs, int num_channels) 933 { 934 int i, gpio_channels; 935 936 /* 937 * Let's initialize the mux config to say that all 8 channels are 938 * GPIOs. Then we can just loop through the iio_chan_spec and clear the 939 * bits for found ADC channels. 940 */ 941 gpio_channels = GENMASK(7, 0); 942 for (i = 0; i < num_channels; i++) 943 gpio_channels &= ~BIT(cs[i].channel); 944 945 return gpio_channels; 946 } 947 948 static int bd79124_hw_init(struct bd79124_data *data) 949 { 950 unsigned int regval; 951 int ret, i; 952 953 for (i = 0; i < BD79124_MAX_NUM_CHANNELS; i++) { 954 ret = bd79124_chan_init(data, i); 955 if (ret) 956 return ret; 957 data->alarm_r_limit[i] = BD79124_HIGH_LIMIT_MAX; 958 } 959 /* Stop auto sequencer */ 960 ret = regmap_clear_bits(data->map, BD79124_REG_SEQ_CFG, 961 BD79124_MSK_SEQ_START); 962 if (ret) 963 return ret; 964 965 /* Enable writing the measured values to the regsters */ 966 ret = regmap_set_bits(data->map, BD79124_REG_GEN_CFG, 967 BD79124_MSK_STATS_EN); 968 if (ret) 969 return ret; 970 971 /* Set no channels to be auto-measured */ 972 ret = regmap_write(data->map, BD79124_REG_AUTO_CHANNELS, 0x0); 973 if (ret) 974 return ret; 975 976 /* Set no channels to be manually measured */ 977 ret = regmap_write(data->map, BD79124_REG_MANUAL_CHANNELS, 0x0); 978 if (ret) 979 return ret; 980 981 regval = FIELD_PREP(BD79124_MSK_AUTO_INTERVAL, BD79124_INTERVAL_750_US); 982 ret = regmap_update_bits(data->map, BD79124_REG_OPMODE_CFG, 983 BD79124_MSK_AUTO_INTERVAL, regval); 984 if (ret) 985 return ret; 986 987 /* Sequencer mode to auto */ 988 ret = regmap_set_bits(data->map, BD79124_REG_SEQ_CFG, 989 BD79124_MSK_SEQ_SEQ); 990 if (ret) 991 return ret; 992 993 /* Don't start the measurement */ 994 regval = FIELD_PREP(BD79124_MSK_CONV_MODE, BD79124_CONV_MODE_MANSEQ); 995 return regmap_update_bits(data->map, BD79124_REG_OPMODE_CFG, 996 BD79124_MSK_CONV_MODE, regval); 997 } 998 999 static int bd79124_probe(struct i2c_client *i2c) 1000 { 1001 struct bd79124_data *data; 1002 struct iio_dev *iio_dev; 1003 const struct iio_chan_spec *template; 1004 struct iio_chan_spec *cs; 1005 struct device *dev = &i2c->dev; 1006 unsigned int gpio_pins; 1007 int ret; 1008 1009 iio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1010 if (!iio_dev) 1011 return -ENOMEM; 1012 1013 data = iio_priv(iio_dev); 1014 data->dev = dev; 1015 data->map = devm_regmap_init_i2c(i2c, &bd79124_regmap); 1016 if (IS_ERR(data->map)) 1017 return dev_err_probe(dev, PTR_ERR(data->map), 1018 "Failed to initialize Regmap\n"); 1019 1020 ret = devm_regulator_get_enable_read_voltage(dev, "vdd"); 1021 if (ret < 0) 1022 return dev_err_probe(dev, ret, "Failed to get the Vdd\n"); 1023 1024 data->vmax = ret; 1025 1026 ret = devm_regulator_get_enable(dev, "iovdd"); 1027 if (ret < 0) 1028 return dev_err_probe(dev, ret, "Failed to enable I/O voltage\n"); 1029 1030 ret = devm_delayed_work_autocancel(dev, &data->alm_enable_work, 1031 bd79124_alm_enable_worker); 1032 if (ret) 1033 return ret; 1034 1035 if (i2c->irq) { 1036 template = &bd79124_chan_template; 1037 } else { 1038 template = &bd79124_chan_template_noirq; 1039 dev_dbg(dev, "No IRQ found, events disabled\n"); 1040 } 1041 1042 ret = devm_mutex_init(dev, &data->mutex); 1043 if (ret) 1044 return ret; 1045 1046 ret = devm_iio_adc_device_alloc_chaninfo_se(dev, template, 1047 BD79124_MAX_NUM_CHANNELS - 1, &cs); 1048 if (ret < 0) { 1049 /* Register all pins as GPOs if there are no ADC channels */ 1050 if (ret == -ENOENT) 1051 goto register_gpios; 1052 return ret; 1053 } 1054 iio_dev->channels = cs; 1055 iio_dev->num_channels = ret; 1056 iio_dev->info = &bd79124_info; 1057 iio_dev->name = "bd79124"; 1058 iio_dev->modes = INDIO_DIRECT_MODE; 1059 1060 ret = bd79124_hw_init(data); 1061 if (ret) 1062 return ret; 1063 1064 if (i2c->irq > 0) { 1065 ret = devm_request_threaded_irq(dev, i2c->irq, 1066 bd79124_irq_handler, &bd79124_event_handler, 1067 IRQF_ONESHOT, "adc-thresh-alert", iio_dev); 1068 if (ret) 1069 return dev_err_probe(data->dev, ret, 1070 "Failed to register IRQ\n"); 1071 } 1072 1073 ret = devm_iio_device_register(data->dev, iio_dev); 1074 if (ret) 1075 return dev_err_probe(data->dev, ret, "Failed to register ADC\n"); 1076 1077 register_gpios: 1078 gpio_pins = bd79124_get_gpio_pins(iio_dev->channels, 1079 iio_dev->num_channels); 1080 1081 /* 1082 * The mux should default to "all ADCs", but better to not trust it. 1083 * Thus we do set the mux even when we have only ADCs and no GPOs. 1084 */ 1085 ret = regmap_write(data->map, BD79124_REG_PINCFG, gpio_pins); 1086 if (ret) 1087 return ret; 1088 1089 /* No GPOs if all channels are reserved for ADC, so we're done. */ 1090 if (!gpio_pins) 1091 return 0; 1092 1093 data->gpio_valid_mask = gpio_pins; 1094 data->gc = bd79124gpo_chip; 1095 data->gc.parent = dev; 1096 1097 return devm_gpiochip_add_data(dev, &data->gc, data); 1098 } 1099 1100 static const struct of_device_id bd79124_of_match[] = { 1101 { .compatible = "rohm,bd79124" }, 1102 { } 1103 }; 1104 MODULE_DEVICE_TABLE(of, bd79124_of_match); 1105 1106 static const struct i2c_device_id bd79124_id[] = { 1107 { "bd79124" }, 1108 { } 1109 }; 1110 MODULE_DEVICE_TABLE(i2c, bd79124_id); 1111 1112 static struct i2c_driver bd79124_driver = { 1113 .driver = { 1114 .name = "bd79124", 1115 .of_match_table = bd79124_of_match, 1116 }, 1117 .probe = bd79124_probe, 1118 .id_table = bd79124_id, 1119 }; 1120 module_i2c_driver(bd79124_driver); 1121 1122 MODULE_AUTHOR("Matti Vaittinen <mazziesaccount@gmail.com>"); 1123 MODULE_DESCRIPTION("Driver for ROHM BD79124 ADC"); 1124 MODULE_LICENSE("GPL"); 1125 MODULE_IMPORT_NS("IIO_DRIVER"); 1126