1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ROHM ADC driver for BD79112 signal monitoring hub. 4 * Copyright (C) 2025, ROHM Semiconductor. 5 * 6 * SPI communication derived from ad7923.c and ti-ads7950.c 7 */ 8 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/bitops.h> 12 #include <linux/bits.h> 13 #include <linux/dev_printk.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/module.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/spi/spi.h> 22 #include <linux/types.h> 23 #include <asm/byteorder.h> 24 25 #include <linux/iio/adc-helpers.h> 26 #include <linux/iio/iio.h> 27 28 #define BD79112_MAX_NUM_CHANNELS 32 29 30 struct bd79112_data { 31 struct spi_device *spi; 32 struct regmap *map; 33 struct device *dev; 34 struct gpio_chip gc; 35 unsigned long gpio_valid_mask; 36 unsigned int vref_mv; 37 struct spi_transfer read_xfer[2]; 38 struct spi_transfer write_xfer; 39 struct spi_message read_msg; 40 struct spi_message write_msg; 41 /* 16-bit TX, valid data in high byte */ 42 u8 read_tx[2] __aligned(IIO_DMA_MINALIGN); 43 /* 8-bit address followed by 8-bit data */ 44 u8 reg_write_tx[2]; 45 /* 12-bit of ADC data or 8 bit of reg data */ 46 __be16 read_rx; 47 }; 48 49 /* 50 * The ADC data is read issuing SPI-command matching the channel number. 51 * We treat this as a register address. 52 */ 53 #define BD79112_REG_AGIO0A 0x00 54 #define BD79112_REG_AGIO15B 0x1f 55 56 /* 57 * ADC STATUS_FLAG appended to ADC data will be set, if the ADC result is being 58 * read for a channel, which input pin is muxed to be a GPIO. 59 */ 60 #define BD79112_ADC_STATUS_FLAG BIT(14) 61 62 /* 63 * The BD79112 requires "R/W bit" to be set for SPI register (not ADC data) 64 * reads and an "IOSET bit" to be set for read/write operations (which aren't 65 * reading the ADC data). 66 */ 67 #define BD79112_BIT_RW BIT(4) 68 #define BD79112_BIT_IO BIT(5) 69 70 #define BD79112_REG_GPI_VALUE_B8_15 (BD79112_BIT_IO | 0x0) 71 #define BD79112_REG_GPI_VALUE_B0_B7 (BD79112_BIT_IO | 0x1) 72 #define BD79112_REG_GPI_VALUE_A8_15 (BD79112_BIT_IO | 0x2) 73 #define BD79112_REG_GPI_VALUE_A0_A7 (BD79112_BIT_IO | 0x3) 74 75 #define BD79112_REG_GPI_EN_B7_B15 (BD79112_BIT_IO | 0x4) 76 #define BD79112_REG_GPI_EN_B0_B7 (BD79112_BIT_IO | 0x5) 77 #define BD79112_REG_GPI_EN_A8_A15 (BD79112_BIT_IO | 0x6) 78 #define BD79112_REG_GPI_EN_A0_A7 (BD79112_BIT_IO | 0x7) 79 80 #define BD79112_REG_GPO_EN_B7_B15 (BD79112_BIT_IO | 0x8) 81 #define BD79112_REG_GPO_EN_B0_B7 (BD79112_BIT_IO | 0x9) 82 #define BD79112_REG_GPO_EN_A8_A15 (BD79112_BIT_IO | 0xa) 83 #define BD79112_REG_GPO_EN_A0_A7 (BD79112_BIT_IO | 0xb) 84 85 #define BD79112_NUM_GPIO_EN_REGS 8 86 #define BD79112_FIRST_GPIO_EN_REG BD79112_REG_GPI_EN_B7_B15 87 88 #define BD79112_REG_GPO_VALUE_B8_15 (BD79112_BIT_IO | 0xc) 89 #define BD79112_REG_GPO_VALUE_B0_B7 (BD79112_BIT_IO | 0xd) 90 #define BD79112_REG_GPO_VALUE_A8_15 (BD79112_BIT_IO | 0xe) 91 #define BD79112_REG_GPO_VALUE_A0_A7 (BD79112_BIT_IO | 0xf) 92 93 #define BD79112_REG_MAX BD79112_REG_GPO_VALUE_A0_A7 94 95 /* 96 * Read transaction consists of two 16-bit sequences separated by CSB. 97 * For register read, 'IOSET' bit must be set. For ADC read, IOSET is cleared 98 * and ADDR equals the channel number (0 ... 31). 99 * 100 * First 16-bit sequence, MOSI as below, MISO data ignored: 101 * - SCK: | 1 | 2 | 3 | 4 | 5 .. 8 | 9 .. 16 | 102 * - MOSI:| 0 | 0 | IOSET | RW (1) | ADDR | 8'b0 | 103 * 104 * CSB released and re-acquired between these sequences 105 * 106 * Second 16-bit sequence, MISO as below, MOSI data ignored: 107 * For Register read data is 8 bits: 108 * - SCK: | 1 .. 8 | 9 .. 16 | 109 * - MISO:| 8'b0 | 8-bit data | 110 * 111 * For ADC read data is 12 bits: 112 * - SCK: | 1 | 2 | 3 4 | 4 .. 16 | 113 * - MISO:| 0 | STATUS_FLAG | 2'b0 | 12-bit data | 114 * The 'STATUS_FLAG' is set if the read input pin was configured as a GPIO. 115 */ 116 static int bd79112_reg_read(void *context, unsigned int reg, unsigned int *val) 117 { 118 struct bd79112_data *data = context; 119 int ret; 120 121 if (reg & BD79112_BIT_IO) 122 reg |= BD79112_BIT_RW; 123 124 data->read_tx[0] = reg; 125 126 ret = spi_sync(data->spi, &data->read_msg); 127 if (!ret) 128 *val = be16_to_cpu(data->read_rx); 129 130 return ret; 131 } 132 133 /* 134 * Write, single 16-bit sequence (broken down below): 135 * 136 * First 8-bit, MOSI as below, MISO data ignored: 137 * - SCK: | 1 | 2 | 3 | 4 | 5 .. 8 | 138 * - MOSI:| 0 | 0 |IOSET| RW(0) | ADDR | 139 * 140 * Last 8 SCK cycles (b8 ... b15), MISO contains register data, MOSI ignored. 141 * - SCK: | 9 .. 16 | 142 * - MISO:| data | 143 */ 144 static int bd79112_reg_write(void *context, unsigned int reg, unsigned int val) 145 { 146 struct bd79112_data *data = context; 147 148 data->reg_write_tx[0] = reg; 149 data->reg_write_tx[1] = val; 150 151 return spi_sync(data->spi, &data->write_msg); 152 } 153 154 static int _get_gpio_reg(unsigned int offset, unsigned int base) 155 { 156 int regoffset = offset / 8; 157 158 if (offset > 31) 159 return -EINVAL; 160 161 return base - regoffset; 162 } 163 164 #define GET_GPIO_BIT(offset) BIT((offset) % 8) 165 #define GET_GPO_EN_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPO_EN_A0_A7) 166 #define GET_GPI_EN_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPI_EN_A0_A7) 167 #define GET_GPO_VAL_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPO_VALUE_A0_A7) 168 #define GET_GPI_VAL_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPI_VALUE_A0_A7) 169 170 static const struct regmap_range bd71815_volatile_ro_ranges[] = { 171 { 172 /* Read ADC data */ 173 .range_min = BD79112_REG_AGIO0A, 174 .range_max = BD79112_REG_AGIO15B, 175 }, { 176 /* GPI state */ 177 .range_min = BD79112_REG_GPI_VALUE_B8_15, 178 .range_max = BD79112_REG_GPI_VALUE_A0_A7, 179 }, 180 }; 181 182 static const struct regmap_access_table bd79112_volatile_regs = { 183 .yes_ranges = &bd71815_volatile_ro_ranges[0], 184 .n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ro_ranges), 185 }; 186 187 static const struct regmap_access_table bd79112_ro_regs = { 188 .no_ranges = &bd71815_volatile_ro_ranges[0], 189 .n_no_ranges = ARRAY_SIZE(bd71815_volatile_ro_ranges), 190 }; 191 192 static const struct regmap_config bd79112_regmap = { 193 .reg_read = bd79112_reg_read, 194 .reg_write = bd79112_reg_write, 195 .volatile_table = &bd79112_volatile_regs, 196 .wr_table = &bd79112_ro_regs, 197 .cache_type = REGCACHE_MAPLE, 198 .max_register = BD79112_REG_MAX, 199 }; 200 201 static int bd79112_read_raw(struct iio_dev *indio_dev, 202 struct iio_chan_spec const *chan, int *val, 203 int *val2, long m) 204 { 205 struct bd79112_data *data = iio_priv(indio_dev); 206 int ret; 207 208 switch (m) { 209 case IIO_CHAN_INFO_RAW: 210 ret = regmap_read(data->map, chan->channel, val); 211 if (ret < 0) 212 return ret; 213 214 return IIO_VAL_INT; 215 216 case IIO_CHAN_INFO_SCALE: 217 *val = data->vref_mv; 218 *val2 = 12; 219 220 return IIO_VAL_FRACTIONAL_LOG2; 221 default: 222 return -EINVAL; 223 } 224 } 225 226 static const struct iio_info bd79112_info = { 227 .read_raw = bd79112_read_raw, 228 }; 229 230 static const struct iio_chan_spec bd79112_chan_template = { 231 .type = IIO_VOLTAGE, 232 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 233 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), 234 .indexed = 1, 235 }; 236 237 static int bd79112_gpio_init_valid_mask(struct gpio_chip *gc, 238 unsigned long *valid_mask, 239 unsigned int ngpios) 240 { 241 struct bd79112_data *data = gpiochip_get_data(gc); 242 243 *valid_mask = data->gpio_valid_mask; 244 245 return 0; 246 } 247 248 static int bd79112_gpio_dir_get(struct gpio_chip *gc, unsigned int offset) 249 { 250 struct bd79112_data *data = gpiochip_get_data(gc); 251 unsigned int reg, bit, val; 252 int ret; 253 254 bit = GET_GPIO_BIT(offset); 255 reg = GET_GPO_EN_REG(offset); 256 257 ret = regmap_read(data->map, reg, &val); 258 if (ret) 259 return ret; 260 261 if (bit & val) 262 return GPIO_LINE_DIRECTION_OUT; 263 264 reg = GET_GPI_EN_REG(offset); 265 ret = regmap_read(data->map, reg, &val); 266 if (ret) 267 return ret; 268 269 if (bit & val) 270 return GPIO_LINE_DIRECTION_IN; 271 272 /* 273 * Ouch. Seems the pin is ADC input - shouldn't happen as changing mux 274 * at runtime is not supported and non GPIO pins should be invalidated 275 * by the valid_mask at probe. Maybe someone wrote a register bypassing 276 * the driver? 277 */ 278 dev_err(data->dev, "Pin not a GPIO\n"); 279 280 return -EINVAL; 281 } 282 283 static int bd79112_gpio_get(struct gpio_chip *gc, unsigned int offset) 284 { 285 struct bd79112_data *data = gpiochip_get_data(gc); 286 unsigned int reg, bit, val; 287 int ret; 288 289 bit = GET_GPIO_BIT(offset); 290 reg = GET_GPI_VAL_REG(offset); 291 292 ret = regmap_read(data->map, reg, &val); 293 if (ret) 294 return ret; 295 296 return !!(val & bit); 297 } 298 299 static int bd79112_gpio_set(struct gpio_chip *gc, unsigned int offset, 300 int value) 301 { 302 struct bd79112_data *data = gpiochip_get_data(gc); 303 unsigned int reg, bit; 304 305 bit = GET_GPIO_BIT(offset); 306 reg = GET_GPO_VAL_REG(offset); 307 308 return regmap_assign_bits(data->map, reg, bit, value); 309 } 310 311 static int bd79112_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 312 unsigned long *bits) 313 { 314 struct bd79112_data *data = gpiochip_get_data(gc); 315 unsigned long i, bank_mask; 316 317 for_each_set_clump8(i, bank_mask, mask, gc->ngpio) { 318 unsigned long bank_bits; 319 unsigned int reg; 320 int ret; 321 322 bank_bits = bitmap_get_value8(bits, i); 323 reg = BD79112_REG_GPO_VALUE_A0_A7 - i / 8; 324 ret = regmap_update_bits(data->map, reg, bank_mask, bank_bits); 325 if (ret) 326 return ret; 327 } 328 329 return 0; 330 } 331 332 static int bd79112_gpio_dir_set(struct bd79112_data *data, unsigned int offset, 333 int dir) 334 { 335 unsigned int gpi_reg, gpo_reg, bit; 336 int ret; 337 338 bit = GET_GPIO_BIT(offset); 339 gpi_reg = GET_GPI_EN_REG(offset); 340 gpo_reg = GET_GPO_EN_REG(offset); 341 342 if (dir == GPIO_LINE_DIRECTION_OUT) { 343 ret = regmap_clear_bits(data->map, gpi_reg, bit); 344 if (ret) 345 return ret; 346 347 return regmap_set_bits(data->map, gpo_reg, bit); 348 } 349 350 ret = regmap_set_bits(data->map, gpi_reg, bit); 351 if (ret) 352 return ret; 353 354 return regmap_clear_bits(data->map, gpo_reg, bit); 355 } 356 357 static int bd79112_gpio_input(struct gpio_chip *gc, unsigned int offset) 358 { 359 struct bd79112_data *data = gpiochip_get_data(gc); 360 361 return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_IN); 362 } 363 364 static int bd79112_gpio_output(struct gpio_chip *gc, unsigned int offset, 365 int value) 366 { 367 struct bd79112_data *data = gpiochip_get_data(gc); 368 int ret; 369 370 ret = bd79112_gpio_set(gc, offset, value); 371 if (ret) 372 return ret; 373 374 return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_OUT); 375 } 376 377 static const struct gpio_chip bd79112_gpio_chip = { 378 .label = "bd79112-gpio", 379 .get_direction = bd79112_gpio_dir_get, 380 .direction_input = bd79112_gpio_input, 381 .direction_output = bd79112_gpio_output, 382 .get = bd79112_gpio_get, 383 .set = bd79112_gpio_set, 384 .set_multiple = bd79112_gpio_set_multiple, 385 .init_valid_mask = bd79112_gpio_init_valid_mask, 386 .can_sleep = true, 387 .ngpio = 32, 388 .base = -1, 389 }; 390 391 static unsigned int bd79112_get_gpio_pins(const struct iio_chan_spec *cs, int num_channels) 392 { 393 unsigned int i, gpio_channels; 394 395 /* 396 * Let's initialize the mux config to say that all 32 channels are 397 * GPIOs. Then we can just loop through the iio_chan_spec and clear the 398 * bits for found ADC channels. 399 */ 400 gpio_channels = GENMASK(31, 0); 401 for (i = 0; i < num_channels; i++) 402 gpio_channels &= ~BIT(cs[i].channel); 403 404 return gpio_channels; 405 } 406 407 /* ADC channels as named in the data-sheet */ 408 static const char * const bd79112_chan_names[] = { 409 "AGIO0A", "AGIO1A", "AGIO2A", "AGIO3A", /* 0 - 3 */ 410 "AGIO4A", "AGIO5A", "AGIO6A", "AGIO7A", /* 4 - 7 */ 411 "AGIO8A", "AGIO9A", "AGIO10A", "AGIO11A", /* 8 - 11 */ 412 "AGIO12A", "AGIO13A", "AGIO14A", "AGIO15A", /* 12 - 15 */ 413 "AGIO0B", "AGIO1B", "AGIO2B", "AGIO3B", /* 16 - 19 */ 414 "AGIO4B", "AGIO5B", "AGIO6B", "AGIO7B", /* 20 - 23 */ 415 "AGIO8B", "AGIO9B", "AGIO10B", "AGIO11B", /* 24 - 27 */ 416 "AGIO12B", "AGIO13B", "AGIO14B", "AGIO15B", /* 28 - 31 */ 417 }; 418 419 static int bd79112_probe(struct spi_device *spi) 420 { 421 struct bd79112_data *data; 422 struct iio_dev *iio_dev; 423 struct iio_chan_spec *cs; 424 struct device *dev = &spi->dev; 425 unsigned long gpio_pins, pin; 426 unsigned int i; 427 int ret; 428 429 iio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 430 if (!iio_dev) 431 return -ENOMEM; 432 433 data = iio_priv(iio_dev); 434 data->spi = spi; 435 data->dev = dev; 436 data->map = devm_regmap_init(dev, NULL, data, &bd79112_regmap); 437 if (IS_ERR(data->map)) 438 return dev_err_probe(dev, PTR_ERR(data->map), 439 "Failed to initialize Regmap\n"); 440 441 ret = devm_regulator_get_enable_read_voltage(dev, "vdd"); 442 if (ret < 0) 443 return dev_err_probe(dev, ret, "Failed to get the Vdd\n"); 444 445 data->vref_mv = ret / 1000; 446 447 ret = devm_regulator_get_enable(dev, "iovdd"); 448 if (ret < 0) 449 return dev_err_probe(dev, ret, "Failed to enable I/O voltage\n"); 450 451 data->read_xfer[0].tx_buf = &data->read_tx[0]; 452 data->read_xfer[0].len = sizeof(data->read_tx); 453 data->read_xfer[0].cs_change = 1; 454 data->read_xfer[1].rx_buf = &data->read_rx; 455 data->read_xfer[1].len = sizeof(data->read_rx); 456 spi_message_init_with_transfers(&data->read_msg, data->read_xfer, 2); 457 ret = devm_spi_optimize_message(dev, spi, &data->read_msg); 458 if (ret < 0) 459 return dev_err_probe(dev, ret, 460 "Failed to optimize SPI read message\n"); 461 462 data->write_xfer.tx_buf = &data->reg_write_tx[0]; 463 data->write_xfer.len = sizeof(data->reg_write_tx); 464 spi_message_init_with_transfers(&data->write_msg, &data->write_xfer, 1); 465 ret = devm_spi_optimize_message(dev, spi, &data->write_msg); 466 if (ret < 0) 467 return dev_err_probe(dev, ret, 468 "Failed to optimize SPI write message\n"); 469 470 ret = devm_iio_adc_device_alloc_chaninfo_se(dev, &bd79112_chan_template, 471 BD79112_MAX_NUM_CHANNELS - 1, 472 &cs); 473 474 /* Register all pins as GPIOs if there are no ADC channels */ 475 if (ret == -ENOENT) 476 goto register_gpios; 477 478 if (ret < 0) 479 return ret; 480 481 iio_dev->num_channels = ret; 482 iio_dev->channels = cs; 483 484 for (i = 0; i < iio_dev->num_channels; i++) 485 cs[i].datasheet_name = bd79112_chan_names[cs[i].channel]; 486 487 iio_dev->info = &bd79112_info; 488 iio_dev->name = "bd79112"; 489 iio_dev->modes = INDIO_DIRECT_MODE; 490 491 /* 492 * Ensure all channels are ADCs. This allows us to register the IIO 493 * device early (before checking which pins are to be used for GPIO) 494 * without having to worry about some pins being initially used for 495 * GPIO. 496 */ 497 for (i = 0; i < BD79112_NUM_GPIO_EN_REGS; i++) { 498 ret = regmap_write(data->map, BD79112_FIRST_GPIO_EN_REG + i, 0); 499 if (ret) 500 return dev_err_probe(dev, ret, 501 "Failed to initialize channels\n"); 502 } 503 504 ret = devm_iio_device_register(data->dev, iio_dev); 505 if (ret) 506 return dev_err_probe(data->dev, ret, "Failed to register ADC\n"); 507 508 register_gpios: 509 gpio_pins = bd79112_get_gpio_pins(iio_dev->channels, 510 iio_dev->num_channels); 511 512 /* If all channels are reserved for ADC, then we're done. */ 513 if (!gpio_pins) 514 return 0; 515 516 /* Default all the GPIO pins to GPI */ 517 for_each_set_bit(pin, &gpio_pins, BD79112_MAX_NUM_CHANNELS) { 518 ret = bd79112_gpio_dir_set(data, pin, GPIO_LINE_DIRECTION_IN); 519 if (ret) 520 return dev_err_probe(dev, ret, 521 "Failed to mark pin as GPI\n"); 522 } 523 524 data->gpio_valid_mask = gpio_pins; 525 data->gc = bd79112_gpio_chip; 526 data->gc.parent = dev; 527 528 return devm_gpiochip_add_data(dev, &data->gc, data); 529 } 530 531 static const struct of_device_id bd79112_of_match[] = { 532 { .compatible = "rohm,bd79112" }, 533 { } 534 }; 535 MODULE_DEVICE_TABLE(of, bd79112_of_match); 536 537 static const struct spi_device_id bd79112_id[] = { 538 { "bd79112" }, 539 { } 540 }; 541 MODULE_DEVICE_TABLE(spi, bd79112_id); 542 543 static struct spi_driver bd79112_driver = { 544 .driver = { 545 .name = "bd79112", 546 .of_match_table = bd79112_of_match, 547 }, 548 .probe = bd79112_probe, 549 .id_table = bd79112_id, 550 }; 551 module_spi_driver(bd79112_driver); 552 553 MODULE_AUTHOR("Matti Vaittinen <mazziesaccount@gmail.com>"); 554 MODULE_DESCRIPTION("Driver for ROHM BD79112 ADC/GPIO"); 555 MODULE_LICENSE("GPL"); 556 MODULE_IMPORT_NS("IIO_DRIVER"); 557