1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/bits.h> 4 #include <linux/delay.h> 5 #include <linux/irq.h> 6 #include <linux/kernel.h> 7 #include <linux/ktime.h> 8 #include <linux/module.h> 9 #include <linux/mutex.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <linux/iio/buffer.h> 14 #include <linux/iio/iio.h> 15 #include <linux/iio/trigger_consumer.h> 16 #include <linux/iio/triggered_buffer.h> 17 18 #include <asm/unaligned.h> 19 20 #define MT6360_REG_PMUCHGCTRL3 0x313 21 #define MT6360_REG_PMUADCCFG 0x356 22 #define MT6360_REG_PMUADCIDLET 0x358 23 #define MT6360_REG_PMUADCRPT1 0x35A 24 25 /* PMUCHGCTRL3 0x313 */ 26 #define MT6360_AICR_MASK GENMASK(7, 2) 27 #define MT6360_AICR_SHFT 2 28 #define MT6360_AICR_400MA 0x6 29 /* PMUADCCFG 0x356 */ 30 #define MT6360_ADCEN_MASK BIT(15) 31 /* PMUADCRPT1 0x35A */ 32 #define MT6360_PREFERCH_MASK GENMASK(7, 4) 33 #define MT6360_PREFERCH_SHFT 4 34 #define MT6360_RPTCH_MASK GENMASK(3, 0) 35 #define MT6360_NO_PREFER 15 36 37 /* Time in ms */ 38 #define ADC_WAIT_TIME_MS 25 39 #define ADC_CONV_TIMEOUT_MS 100 40 #define ADC_LOOP_TIME_US 2000 41 42 enum { 43 MT6360_CHAN_USBID = 0, 44 MT6360_CHAN_VBUSDIV5, 45 MT6360_CHAN_VBUSDIV2, 46 MT6360_CHAN_VSYS, 47 MT6360_CHAN_VBAT, 48 MT6360_CHAN_IBUS, 49 MT6360_CHAN_IBAT, 50 MT6360_CHAN_CHG_VDDP, 51 MT6360_CHAN_TEMP_JC, 52 MT6360_CHAN_VREF_TS, 53 MT6360_CHAN_TS, 54 MT6360_CHAN_MAX 55 }; 56 57 struct mt6360_adc_data { 58 struct device *dev; 59 struct regmap *regmap; 60 /* Due to only one set of ADC control, this lock is used to prevent the race condition */ 61 struct mutex adc_lock; 62 ktime_t last_off_timestamps[MT6360_CHAN_MAX]; 63 }; 64 65 static int mt6360_adc_read_channel(struct mt6360_adc_data *mad, int channel, int *val) 66 { 67 __be16 adc_enable; 68 u8 rpt[3]; 69 ktime_t predict_end_t, timeout; 70 unsigned int pre_wait_time; 71 int ret; 72 73 mutex_lock(&mad->adc_lock); 74 75 /* Select the preferred ADC channel */ 76 ret = regmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK, 77 channel << MT6360_PREFERCH_SHFT); 78 if (ret) 79 goto out_adc_lock; 80 81 adc_enable = cpu_to_be16(MT6360_ADCEN_MASK | BIT(channel)); 82 ret = regmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable)); 83 if (ret) 84 goto out_adc_lock; 85 86 predict_end_t = ktime_add_ms(mad->last_off_timestamps[channel], 2 * ADC_WAIT_TIME_MS); 87 88 if (ktime_after(ktime_get(), predict_end_t)) 89 pre_wait_time = ADC_WAIT_TIME_MS; 90 else 91 pre_wait_time = 3 * ADC_WAIT_TIME_MS; 92 93 if (msleep_interruptible(pre_wait_time)) { 94 ret = -ERESTARTSYS; 95 goto out_adc_conv; 96 } 97 98 timeout = ktime_add_ms(ktime_get(), ADC_CONV_TIMEOUT_MS); 99 while (true) { 100 ret = regmap_raw_read(mad->regmap, MT6360_REG_PMUADCRPT1, rpt, sizeof(rpt)); 101 if (ret) 102 goto out_adc_conv; 103 104 /* 105 * There are two functions, ZCV and TypeC OTP, running ADC VBAT and TS in 106 * background, and ADC samples are taken on a fixed frequency no matter read the 107 * previous one or not. 108 * To avoid conflict, We set minimum time threshold after enable ADC and 109 * check report channel is the same. 110 * The worst case is run the same ADC twice and background function is also running, 111 * ADC conversion sequence is desire channel before start ADC, background ADC, 112 * desire channel after start ADC. 113 * So the minimum correct data is three times of typical conversion time. 114 */ 115 if ((rpt[0] & MT6360_RPTCH_MASK) == channel) 116 break; 117 118 if (ktime_compare(ktime_get(), timeout) > 0) { 119 ret = -ETIMEDOUT; 120 goto out_adc_conv; 121 } 122 123 usleep_range(ADC_LOOP_TIME_US / 2, ADC_LOOP_TIME_US); 124 } 125 126 *val = rpt[1] << 8 | rpt[2]; 127 ret = IIO_VAL_INT; 128 129 out_adc_conv: 130 /* Only keep ADC enable */ 131 adc_enable = cpu_to_be16(MT6360_ADCEN_MASK); 132 regmap_raw_write(mad->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable)); 133 mad->last_off_timestamps[channel] = ktime_get(); 134 /* Config prefer channel to NO_PREFER */ 135 regmap_update_bits(mad->regmap, MT6360_REG_PMUADCRPT1, MT6360_PREFERCH_MASK, 136 MT6360_NO_PREFER << MT6360_PREFERCH_SHFT); 137 out_adc_lock: 138 mutex_unlock(&mad->adc_lock); 139 140 return ret; 141 } 142 143 static int mt6360_adc_read_scale(struct mt6360_adc_data *mad, int channel, int *val, int *val2) 144 { 145 unsigned int regval; 146 int ret; 147 148 switch (channel) { 149 case MT6360_CHAN_USBID: 150 case MT6360_CHAN_VSYS: 151 case MT6360_CHAN_VBAT: 152 case MT6360_CHAN_CHG_VDDP: 153 case MT6360_CHAN_VREF_TS: 154 case MT6360_CHAN_TS: 155 *val = 1250; 156 return IIO_VAL_INT; 157 case MT6360_CHAN_VBUSDIV5: 158 *val = 6250; 159 return IIO_VAL_INT; 160 case MT6360_CHAN_VBUSDIV2: 161 case MT6360_CHAN_IBUS: 162 case MT6360_CHAN_IBAT: 163 *val = 2500; 164 165 if (channel == MT6360_CHAN_IBUS) { 166 /* IBUS will be affected by input current limit for the different Ron */ 167 /* Check whether the config is <400mA or not */ 168 ret = regmap_read(mad->regmap, MT6360_REG_PMUCHGCTRL3, ®val); 169 if (ret) 170 return ret; 171 172 regval = (regval & MT6360_AICR_MASK) >> MT6360_AICR_SHFT; 173 if (regval < MT6360_AICR_400MA) 174 *val = 1900; 175 } 176 177 return IIO_VAL_INT; 178 case MT6360_CHAN_TEMP_JC: 179 *val = 105; 180 *val2 = 100; 181 return IIO_VAL_FRACTIONAL; 182 } 183 184 return -EINVAL; 185 } 186 187 static int mt6360_adc_read_offset(struct mt6360_adc_data *mad, int channel, int *val) 188 { 189 *val = (channel == MT6360_CHAN_TEMP_JC) ? -80 : 0; 190 return IIO_VAL_INT; 191 } 192 193 static int mt6360_adc_read_raw(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, 194 int *val, int *val2, long mask) 195 { 196 struct mt6360_adc_data *mad = iio_priv(iio_dev); 197 198 switch (mask) { 199 case IIO_CHAN_INFO_RAW: 200 return mt6360_adc_read_channel(mad, chan->channel, val); 201 case IIO_CHAN_INFO_SCALE: 202 return mt6360_adc_read_scale(mad, chan->channel, val, val2); 203 case IIO_CHAN_INFO_OFFSET: 204 return mt6360_adc_read_offset(mad, chan->channel, val); 205 } 206 207 return -EINVAL; 208 } 209 210 static const char *mt6360_channel_labels[MT6360_CHAN_MAX] = { 211 "usbid", "vbusdiv5", "vbusdiv2", "vsys", "vbat", "ibus", "ibat", "chg_vddp", 212 "temp_jc", "vref_ts", "ts", 213 }; 214 215 static int mt6360_adc_read_label(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, 216 char *label) 217 { 218 return snprintf(label, PAGE_SIZE, "%s\n", mt6360_channel_labels[chan->channel]); 219 } 220 221 static const struct iio_info mt6360_adc_iio_info = { 222 .read_raw = mt6360_adc_read_raw, 223 .read_label = mt6360_adc_read_label, 224 }; 225 226 #define MT6360_ADC_CHAN(_idx, _type) { \ 227 .type = _type, \ 228 .channel = MT6360_CHAN_##_idx, \ 229 .scan_index = MT6360_CHAN_##_idx, \ 230 .datasheet_name = #_idx, \ 231 .scan_type = { \ 232 .sign = 'u', \ 233 .realbits = 16, \ 234 .storagebits = 16, \ 235 .endianness = IIO_CPU, \ 236 }, \ 237 .indexed = 1, \ 238 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 239 BIT(IIO_CHAN_INFO_SCALE) | \ 240 BIT(IIO_CHAN_INFO_OFFSET), \ 241 } 242 243 static const struct iio_chan_spec mt6360_adc_channels[] = { 244 MT6360_ADC_CHAN(USBID, IIO_VOLTAGE), 245 MT6360_ADC_CHAN(VBUSDIV5, IIO_VOLTAGE), 246 MT6360_ADC_CHAN(VBUSDIV2, IIO_VOLTAGE), 247 MT6360_ADC_CHAN(VSYS, IIO_VOLTAGE), 248 MT6360_ADC_CHAN(VBAT, IIO_VOLTAGE), 249 MT6360_ADC_CHAN(IBUS, IIO_CURRENT), 250 MT6360_ADC_CHAN(IBAT, IIO_CURRENT), 251 MT6360_ADC_CHAN(CHG_VDDP, IIO_VOLTAGE), 252 MT6360_ADC_CHAN(TEMP_JC, IIO_TEMP), 253 MT6360_ADC_CHAN(VREF_TS, IIO_VOLTAGE), 254 MT6360_ADC_CHAN(TS, IIO_VOLTAGE), 255 IIO_CHAN_SOFT_TIMESTAMP(MT6360_CHAN_MAX), 256 }; 257 258 static irqreturn_t mt6360_adc_trigger_handler(int irq, void *p) 259 { 260 struct iio_poll_func *pf = p; 261 struct iio_dev *indio_dev = pf->indio_dev; 262 struct mt6360_adc_data *mad = iio_priv(indio_dev); 263 struct { 264 u16 values[MT6360_CHAN_MAX]; 265 int64_t timestamp; 266 } data __aligned(8); 267 int i = 0, bit, val, ret; 268 269 memset(&data, 0, sizeof(data)); 270 for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->masklength) { 271 ret = mt6360_adc_read_channel(mad, bit, &val); 272 if (ret < 0) { 273 dev_warn(&indio_dev->dev, "Failed to get channel %d conversion val\n", bit); 274 goto out; 275 } 276 277 data.values[i++] = val; 278 } 279 iio_push_to_buffers_with_timestamp(indio_dev, &data, iio_get_time_ns(indio_dev)); 280 out: 281 iio_trigger_notify_done(indio_dev->trig); 282 283 return IRQ_HANDLED; 284 } 285 286 static inline int mt6360_adc_reset(struct mt6360_adc_data *info) 287 { 288 __be16 adc_enable; 289 ktime_t all_off_time; 290 int i, ret; 291 292 /* Clear ADC idle wait time to 0 */ 293 ret = regmap_write(info->regmap, MT6360_REG_PMUADCIDLET, 0); 294 if (ret) 295 return ret; 296 297 /* Only keep ADC enable, but keep all channels off */ 298 adc_enable = cpu_to_be16(MT6360_ADCEN_MASK); 299 ret = regmap_raw_write(info->regmap, MT6360_REG_PMUADCCFG, &adc_enable, sizeof(adc_enable)); 300 if (ret) 301 return ret; 302 303 /* Reset all channel off time to the current one */ 304 all_off_time = ktime_get(); 305 for (i = 0; i < MT6360_CHAN_MAX; i++) 306 info->last_off_timestamps[i] = all_off_time; 307 308 return 0; 309 } 310 311 static int mt6360_adc_probe(struct platform_device *pdev) 312 { 313 struct mt6360_adc_data *mad; 314 struct regmap *regmap; 315 struct iio_dev *indio_dev; 316 int ret; 317 318 regmap = dev_get_regmap(pdev->dev.parent, NULL); 319 if (!regmap) { 320 dev_err(&pdev->dev, "Failed to get parent regmap\n"); 321 return -ENODEV; 322 } 323 324 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*mad)); 325 if (!indio_dev) 326 return -ENOMEM; 327 328 mad = iio_priv(indio_dev); 329 mad->dev = &pdev->dev; 330 mad->regmap = regmap; 331 mutex_init(&mad->adc_lock); 332 333 ret = mt6360_adc_reset(mad); 334 if (ret < 0) { 335 dev_err(&pdev->dev, "Failed to reset adc\n"); 336 return ret; 337 } 338 339 indio_dev->name = dev_name(&pdev->dev); 340 indio_dev->dev.parent = &pdev->dev; 341 indio_dev->info = &mt6360_adc_iio_info; 342 indio_dev->modes = INDIO_DIRECT_MODE; 343 indio_dev->channels = mt6360_adc_channels; 344 indio_dev->num_channels = ARRAY_SIZE(mt6360_adc_channels); 345 346 ret = devm_iio_triggered_buffer_setup(&pdev->dev, indio_dev, NULL, 347 mt6360_adc_trigger_handler, NULL); 348 if (ret) { 349 dev_err(&pdev->dev, "Failed to allocate iio trigger buffer\n"); 350 return ret; 351 } 352 353 return devm_iio_device_register(&pdev->dev, indio_dev); 354 } 355 356 static const struct of_device_id __maybe_unused mt6360_adc_of_id[] = { 357 { .compatible = "mediatek,mt6360-adc", }, 358 {} 359 }; 360 MODULE_DEVICE_TABLE(of, mt6360_adc_of_id); 361 362 static struct platform_driver mt6360_adc_driver = { 363 .driver = { 364 .name = "mt6360-adc", 365 .of_match_table = mt6360_adc_of_id, 366 }, 367 .probe = mt6360_adc_probe, 368 }; 369 module_platform_driver(mt6360_adc_driver); 370 371 MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>"); 372 MODULE_DESCRIPTION("MT6360 ADC Driver"); 373 MODULE_LICENSE("GPL v2"); 374