1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter 4 * 5 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/delay.h> 12 #include <linux/io.h> 13 #include <linux/iio/iio.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/nvmem-consumer.h> 17 #include <linux/interrupt.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/mfd/syscon.h> 24 25 #define MESON_SAR_ADC_REG0 0x00 26 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31) 27 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28) 28 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30) 29 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29) 30 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28) 31 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27) 32 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26) 33 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21) 34 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19) 35 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16) 36 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15) 37 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14) 38 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12) 39 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10) 40 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9) 41 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4) 42 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3) 43 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2) 44 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1) 45 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0) 46 47 #define MESON_SAR_ADC_CHAN_LIST 0x04 48 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24) 49 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \ 50 (GENMASK(2, 0) << ((_chan) * 3)) 51 52 #define MESON_SAR_ADC_AVG_CNTL 0x08 53 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \ 54 (16 + ((_chan) * 2)) 55 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \ 56 (GENMASK(17, 16) << ((_chan) * 2)) 57 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \ 58 (0 + ((_chan) * 2)) 59 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \ 60 (GENMASK(1, 0) << ((_chan) * 2)) 61 62 #define MESON_SAR_ADC_REG3 0x0c 63 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31) 64 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30) 65 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28) 66 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27) 67 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26) 68 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23) 69 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22) 70 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21) 71 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18) 72 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16) 73 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10 74 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6 75 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8) 76 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0) 77 78 #define MESON_SAR_ADC_DELAY 0x10 79 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24) 80 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15) 81 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14) 82 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16) 83 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8) 84 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0) 85 86 #define MESON_SAR_ADC_LAST_RD 0x14 87 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16) 88 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0) 89 90 #define MESON_SAR_ADC_FIFO_RD 0x18 91 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12) 92 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0) 93 94 #define MESON_SAR_ADC_AUX_SW 0x1c 95 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \ 96 (8 + (((_chan) - 2) * 3)) 97 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6) 98 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5) 99 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4) 100 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3) 101 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2) 102 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1) 103 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0) 104 105 #define MESON_SAR_ADC_CHAN_10_SW 0x20 106 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23) 107 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22) 108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21) 109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20) 110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19) 111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18) 112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17) 113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16) 114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7) 115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6) 116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5) 117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4) 118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3) 119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2) 120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1) 121 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0) 122 123 #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24 124 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26) 125 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23) 126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22) 127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21) 128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20) 129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19) 130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18) 131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17) 132 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16) 133 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7) 134 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6) 135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5) 136 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4) 137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3) 138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2) 139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1) 140 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0) 141 142 #define MESON_SAR_ADC_DELTA_10 0x28 143 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27) 144 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26) 145 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16) 146 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15) 147 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11) 148 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10) 149 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0) 150 151 /* 152 * NOTE: registers from here are undocumented (the vendor Linux kernel driver 153 * and u-boot source served as reference). These only seem to be relevant on 154 * GXBB and newer. 155 */ 156 #define MESON_SAR_ADC_REG11 0x2c 157 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13) 158 #define MESON_SAR_ADC_REG11_CMV_SEL BIT(6) 159 #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5) 160 #define MESON_SAR_ADC_REG11_EOC BIT(1) 161 #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0) 162 163 #define MESON_SAR_ADC_REG12 0x30 164 #define MESON_SAR_ADC_REG12_MPLL0_UNKNOWN BIT(0) 165 #define MESON_SAR_ADC_REG12_MPLL1_UNKNOWN BIT(1) 166 #define MESON_SAR_ADC_REG12_MPLL2_UNKNOWN BIT(2) 167 168 #define MESON_SAR_ADC_REG13 0x34 169 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8) 170 171 #define MESON_SAR_ADC_MAX_FIFO_SIZE 32 172 #define MESON_SAR_ADC_TIMEOUT 100 /* ms */ 173 #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6 174 #define MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL 7 175 #define MESON_SAR_ADC_TEMP_OFFSET 27 176 177 /* temperature sensor calibration information in eFuse */ 178 #define MESON_SAR_ADC_EFUSE_BYTES 4 179 #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0) 180 #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7) 181 182 #define MESON_HHI_DPLL_TOP_0 0x318 183 #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9) 184 185 /* for use with IIO_VAL_INT_PLUS_MICRO */ 186 #define MILLION 1000000 187 188 #define MESON_SAR_ADC_CHAN(_chan) { \ 189 .type = IIO_VOLTAGE, \ 190 .indexed = 1, \ 191 .channel = _chan, \ 192 .address = _chan, \ 193 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 194 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ 195 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 196 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 197 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 198 .datasheet_name = "SAR_ADC_CH"#_chan, \ 199 } 200 201 #define MESON_SAR_ADC_TEMP_CHAN(_chan) { \ 202 .type = IIO_TEMP, \ 203 .channel = _chan, \ 204 .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \ 205 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 206 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ 207 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \ 208 BIT(IIO_CHAN_INFO_SCALE), \ 209 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 210 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 211 .datasheet_name = "TEMP_SENSOR", \ 212 } 213 214 #define MESON_SAR_ADC_MUX(_chan, _sel) { \ 215 .type = IIO_VOLTAGE, \ 216 .channel = _chan, \ 217 .indexed = 1, \ 218 .address = MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL, \ 219 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 220 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ 221 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 222 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 223 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 224 .datasheet_name = "SAR_ADC_MUX_"#_sel, \ 225 } 226 227 enum meson_sar_adc_vref_sel { 228 VREF_CALIBATION_VOLTAGE = 0, 229 VREF_VDDA = 1, 230 }; 231 232 enum meson_sar_adc_avg_mode { 233 NO_AVERAGING = 0x0, 234 MEAN_AVERAGING = 0x1, 235 MEDIAN_AVERAGING = 0x2, 236 }; 237 238 enum meson_sar_adc_num_samples { 239 ONE_SAMPLE = 0x0, 240 TWO_SAMPLES = 0x1, 241 FOUR_SAMPLES = 0x2, 242 EIGHT_SAMPLES = 0x3, 243 }; 244 245 enum meson_sar_adc_chan7_mux_sel { 246 CHAN7_MUX_VSS = 0x0, 247 CHAN7_MUX_VDD_DIV4 = 0x1, 248 CHAN7_MUX_VDD_DIV2 = 0x2, 249 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3, 250 CHAN7_MUX_VDD = 0x4, 251 CHAN7_MUX_CH7_INPUT = 0x7, 252 }; 253 254 enum meson_sar_adc_channel_index { 255 NUM_CHAN_0, 256 NUM_CHAN_1, 257 NUM_CHAN_2, 258 NUM_CHAN_3, 259 NUM_CHAN_4, 260 NUM_CHAN_5, 261 NUM_CHAN_6, 262 NUM_CHAN_7, 263 NUM_CHAN_TEMP, 264 NUM_MUX_0_VSS, 265 NUM_MUX_1_VDD_DIV4, 266 NUM_MUX_2_VDD_DIV2, 267 NUM_MUX_3_VDD_MUL3_DIV4, 268 NUM_MUX_4_VDD, 269 }; 270 271 static enum meson_sar_adc_chan7_mux_sel chan7_mux_values[] = { 272 CHAN7_MUX_VSS, 273 CHAN7_MUX_VDD_DIV4, 274 CHAN7_MUX_VDD_DIV2, 275 CHAN7_MUX_VDD_MUL3_DIV4, 276 CHAN7_MUX_VDD, 277 }; 278 279 static const char * const chan7_mux_names[] = { 280 [CHAN7_MUX_VSS] = "gnd", 281 [CHAN7_MUX_VDD_DIV4] = "0.25vdd", 282 [CHAN7_MUX_VDD_DIV2] = "0.5vdd", 283 [CHAN7_MUX_VDD_MUL3_DIV4] = "0.75vdd", 284 [CHAN7_MUX_VDD] = "vdd", 285 }; 286 287 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = { 288 MESON_SAR_ADC_CHAN(NUM_CHAN_0), 289 MESON_SAR_ADC_CHAN(NUM_CHAN_1), 290 MESON_SAR_ADC_CHAN(NUM_CHAN_2), 291 MESON_SAR_ADC_CHAN(NUM_CHAN_3), 292 MESON_SAR_ADC_CHAN(NUM_CHAN_4), 293 MESON_SAR_ADC_CHAN(NUM_CHAN_5), 294 MESON_SAR_ADC_CHAN(NUM_CHAN_6), 295 MESON_SAR_ADC_CHAN(NUM_CHAN_7), 296 MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0), 297 MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1), 298 MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2), 299 MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3), 300 MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4), 301 }; 302 303 static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = { 304 MESON_SAR_ADC_CHAN(NUM_CHAN_0), 305 MESON_SAR_ADC_CHAN(NUM_CHAN_1), 306 MESON_SAR_ADC_CHAN(NUM_CHAN_2), 307 MESON_SAR_ADC_CHAN(NUM_CHAN_3), 308 MESON_SAR_ADC_CHAN(NUM_CHAN_4), 309 MESON_SAR_ADC_CHAN(NUM_CHAN_5), 310 MESON_SAR_ADC_CHAN(NUM_CHAN_6), 311 MESON_SAR_ADC_CHAN(NUM_CHAN_7), 312 MESON_SAR_ADC_TEMP_CHAN(NUM_CHAN_TEMP), 313 MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0), 314 MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1), 315 MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2), 316 MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3), 317 MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4), 318 }; 319 320 struct meson_sar_adc_param { 321 bool has_bl30_integration; 322 unsigned long clock_rate; 323 unsigned int resolution; 324 const struct regmap_config *regmap_config; 325 u8 temperature_trimming_bits; 326 unsigned int temperature_multiplier; 327 unsigned int temperature_divider; 328 u8 disable_ring_counter; 329 bool has_vref_select; 330 u8 vref_select; 331 u8 cmv_select; 332 u8 adc_eoc; 333 enum meson_sar_adc_vref_sel vref_voltage; 334 bool enable_mpll_clock_workaround; 335 }; 336 337 struct meson_sar_adc_data { 338 const struct meson_sar_adc_param *param; 339 const char *name; 340 }; 341 342 struct meson_sar_adc_priv { 343 struct regmap *regmap; 344 struct regulator *vref; 345 const struct meson_sar_adc_param *param; 346 struct clk *clkin; 347 struct clk *core_clk; 348 struct clk *adc_sel_clk; 349 struct clk *adc_clk; 350 struct clk_gate clk_gate; 351 struct clk *adc_div_clk; 352 struct clk_divider clk_div; 353 struct completion done; 354 /* lock to protect against multiple access to the device */ 355 struct mutex lock; 356 int calibbias; 357 int calibscale; 358 struct regmap *tsc_regmap; 359 bool temperature_sensor_calibrated; 360 u8 temperature_sensor_coefficient; 361 u16 temperature_sensor_adc_val; 362 enum meson_sar_adc_chan7_mux_sel chan7_mux_sel; 363 }; 364 365 static const struct regmap_config meson_sar_adc_regmap_config_gxbb = { 366 .reg_bits = 8, 367 .val_bits = 32, 368 .reg_stride = 4, 369 .max_register = MESON_SAR_ADC_REG13, 370 }; 371 372 static const struct regmap_config meson_sar_adc_regmap_config_meson8 = { 373 .reg_bits = 8, 374 .val_bits = 32, 375 .reg_stride = 4, 376 .max_register = MESON_SAR_ADC_DELTA_10, 377 }; 378 379 static const struct iio_chan_spec * 380 find_channel_by_num(struct iio_dev *indio_dev, int num) 381 { 382 int i; 383 384 for (i = 0; i < indio_dev->num_channels; i++) 385 if (indio_dev->channels[i].channel == num) 386 return &indio_dev->channels[i]; 387 return NULL; 388 } 389 390 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev) 391 { 392 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 393 u32 regval; 394 395 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); 396 397 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); 398 } 399 400 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val) 401 { 402 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 403 int tmp; 404 405 /* use val_calib = scale * val_raw + offset calibration function */ 406 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias; 407 408 return clamp(tmp, 0, (1 << priv->param->resolution) - 1); 409 } 410 411 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev) 412 { 413 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 414 int val; 415 416 /* 417 * NOTE: we need a small delay before reading the status, otherwise 418 * the sample engine may not have started internally (which would 419 * seem to us that sampling is already finished). 420 */ 421 udelay(1); 422 return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val, 423 !FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, val), 424 1, 10000); 425 } 426 427 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev, 428 enum meson_sar_adc_chan7_mux_sel sel) 429 { 430 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 431 u32 regval; 432 433 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel); 434 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 435 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval); 436 437 usleep_range(10, 20); 438 439 priv->chan7_mux_sel = sel; 440 } 441 442 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, 443 const struct iio_chan_spec *chan, 444 int *val) 445 { 446 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 447 struct device *dev = indio_dev->dev.parent; 448 int regval, fifo_chan, fifo_val, count; 449 450 if (!wait_for_completion_timeout(&priv->done, 451 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT))) 452 return -ETIMEDOUT; 453 454 count = meson_sar_adc_get_fifo_count(indio_dev); 455 if (count != 1) { 456 dev_err(dev, "ADC FIFO has %d element(s) instead of one\n", count); 457 return -EINVAL; 458 } 459 460 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); 461 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval); 462 if (fifo_chan != chan->address) { 463 dev_err(dev, "ADC FIFO entry belongs to channel %d instead of %lu\n", 464 fifo_chan, chan->address); 465 return -EINVAL; 466 } 467 468 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval); 469 fifo_val &= GENMASK(priv->param->resolution - 1, 0); 470 *val = meson_sar_adc_calib_val(indio_dev, fifo_val); 471 472 return 0; 473 } 474 475 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev, 476 const struct iio_chan_spec *chan, 477 enum meson_sar_adc_avg_mode mode, 478 enum meson_sar_adc_num_samples samples) 479 { 480 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 481 int val, address = chan->address; 482 483 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address); 484 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, 485 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address), 486 val); 487 488 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address); 489 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, 490 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val); 491 } 492 493 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev, 494 const struct iio_chan_spec *chan) 495 { 496 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 497 u32 regval; 498 499 /* 500 * the SAR ADC engine allows sampling multiple channels at the same 501 * time. to keep it simple we're only working with one *internal* 502 * channel, which starts counting at index 0 (which means: count = 1). 503 */ 504 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0); 505 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 506 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval); 507 508 /* map channel index 0 to the channel which we want to read */ 509 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), 510 chan->address); 511 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 512 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval); 513 514 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, 515 chan->address); 516 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, 517 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, 518 regval); 519 520 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, 521 chan->address); 522 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, 523 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, 524 regval); 525 526 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) { 527 if (chan->type == IIO_TEMP) 528 regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL; 529 else 530 regval = 0; 531 532 regmap_update_bits(priv->regmap, 533 MESON_SAR_ADC_DELTA_10, 534 MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval); 535 } else if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL) { 536 enum meson_sar_adc_chan7_mux_sel sel; 537 538 if (chan->channel == NUM_CHAN_7) 539 sel = CHAN7_MUX_CH7_INPUT; 540 else 541 sel = chan7_mux_values[chan->channel - NUM_MUX_0_VSS]; 542 if (sel != priv->chan7_mux_sel) 543 meson_sar_adc_set_chan7_mux(indio_dev, sel); 544 } 545 } 546 547 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev) 548 { 549 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 550 551 reinit_completion(&priv->done); 552 553 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, 554 MESON_SAR_ADC_REG0_FIFO_IRQ_EN); 555 556 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, 557 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE); 558 559 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, 560 MESON_SAR_ADC_REG0_SAMPLING_START); 561 } 562 563 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev) 564 { 565 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 566 567 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0, 568 MESON_SAR_ADC_REG0_FIFO_IRQ_EN); 569 570 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, 571 MESON_SAR_ADC_REG0_SAMPLING_STOP); 572 573 /* wait until all modules are stopped */ 574 meson_sar_adc_wait_busy_clear(indio_dev); 575 576 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0, 577 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE); 578 } 579 580 static int meson_sar_adc_lock(struct iio_dev *indio_dev) 581 { 582 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 583 int val, ret; 584 585 mutex_lock(&priv->lock); 586 587 if (priv->param->has_bl30_integration) { 588 /* prevent BL30 from using the SAR ADC while we are using it */ 589 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELAY, 590 MESON_SAR_ADC_DELAY_KERNEL_BUSY); 591 592 udelay(1); 593 594 /* 595 * wait until BL30 releases it's lock (so we can use the SAR 596 * ADC) 597 */ 598 ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val, 599 !(val & MESON_SAR_ADC_DELAY_BL30_BUSY), 600 1, 10000); 601 if (ret) { 602 mutex_unlock(&priv->lock); 603 return ret; 604 } 605 } 606 607 return 0; 608 } 609 610 static void meson_sar_adc_unlock(struct iio_dev *indio_dev) 611 { 612 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 613 614 if (priv->param->has_bl30_integration) 615 /* allow BL30 to use the SAR ADC again */ 616 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELAY, 617 MESON_SAR_ADC_DELAY_KERNEL_BUSY); 618 619 mutex_unlock(&priv->lock); 620 } 621 622 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev) 623 { 624 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 625 unsigned int count, tmp; 626 627 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) { 628 if (!meson_sar_adc_get_fifo_count(indio_dev)) 629 break; 630 631 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp); 632 } 633 } 634 635 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev, 636 const struct iio_chan_spec *chan, 637 enum meson_sar_adc_avg_mode avg_mode, 638 enum meson_sar_adc_num_samples avg_samples, 639 int *val) 640 { 641 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 642 struct device *dev = indio_dev->dev.parent; 643 int ret; 644 645 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated) 646 return -ENOTSUPP; 647 648 ret = meson_sar_adc_lock(indio_dev); 649 if (ret) 650 return ret; 651 652 /* clear the FIFO to make sure we're not reading old values */ 653 meson_sar_adc_clear_fifo(indio_dev); 654 655 meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples); 656 657 meson_sar_adc_enable_channel(indio_dev, chan); 658 659 meson_sar_adc_start_sample_engine(indio_dev); 660 ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val); 661 meson_sar_adc_stop_sample_engine(indio_dev); 662 663 meson_sar_adc_unlock(indio_dev); 664 665 if (ret) { 666 dev_warn(dev, "failed to read sample for channel %lu: %d\n", 667 chan->address, ret); 668 return ret; 669 } 670 671 return IIO_VAL_INT; 672 } 673 674 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev, 675 const struct iio_chan_spec *chan, 676 int *val, int *val2, long mask) 677 { 678 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 679 struct device *dev = indio_dev->dev.parent; 680 int ret; 681 682 switch (mask) { 683 case IIO_CHAN_INFO_RAW: 684 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING, 685 ONE_SAMPLE, val); 686 687 case IIO_CHAN_INFO_AVERAGE_RAW: 688 return meson_sar_adc_get_sample(indio_dev, chan, 689 MEAN_AVERAGING, EIGHT_SAMPLES, 690 val); 691 692 case IIO_CHAN_INFO_SCALE: 693 if (chan->type == IIO_VOLTAGE) { 694 ret = regulator_get_voltage(priv->vref); 695 if (ret < 0) { 696 dev_err(dev, "failed to get vref voltage: %d\n", ret); 697 return ret; 698 } 699 700 *val = ret / 1000; 701 *val2 = priv->param->resolution; 702 return IIO_VAL_FRACTIONAL_LOG2; 703 } else if (chan->type == IIO_TEMP) { 704 /* SoC specific multiplier and divider */ 705 *val = priv->param->temperature_multiplier; 706 *val2 = priv->param->temperature_divider; 707 708 /* celsius to millicelsius */ 709 *val *= 1000; 710 711 return IIO_VAL_FRACTIONAL; 712 } else { 713 return -EINVAL; 714 } 715 716 case IIO_CHAN_INFO_CALIBBIAS: 717 *val = priv->calibbias; 718 return IIO_VAL_INT; 719 720 case IIO_CHAN_INFO_CALIBSCALE: 721 *val = priv->calibscale / MILLION; 722 *val2 = priv->calibscale % MILLION; 723 return IIO_VAL_INT_PLUS_MICRO; 724 725 case IIO_CHAN_INFO_OFFSET: 726 *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET * 727 priv->param->temperature_divider, 728 priv->param->temperature_multiplier); 729 *val -= priv->temperature_sensor_adc_val; 730 return IIO_VAL_INT; 731 732 default: 733 return -EINVAL; 734 } 735 } 736 737 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, 738 void __iomem *base) 739 { 740 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 741 struct device *dev = indio_dev->dev.parent; 742 struct clk_init_data init; 743 const char *clk_parents[1]; 744 745 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_div", dev_name(dev)); 746 if (!init.name) 747 return -ENOMEM; 748 749 init.flags = 0; 750 init.ops = &clk_divider_ops; 751 clk_parents[0] = __clk_get_name(priv->clkin); 752 init.parent_names = clk_parents; 753 init.num_parents = 1; 754 755 priv->clk_div.reg = base + MESON_SAR_ADC_REG3; 756 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT; 757 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH; 758 priv->clk_div.hw.init = &init; 759 priv->clk_div.flags = 0; 760 761 priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw); 762 if (WARN_ON(IS_ERR(priv->adc_div_clk))) 763 return PTR_ERR(priv->adc_div_clk); 764 765 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_en", dev_name(dev)); 766 if (!init.name) 767 return -ENOMEM; 768 769 init.flags = CLK_SET_RATE_PARENT; 770 init.ops = &clk_gate_ops; 771 clk_parents[0] = __clk_get_name(priv->adc_div_clk); 772 init.parent_names = clk_parents; 773 init.num_parents = 1; 774 775 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; 776 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN); 777 priv->clk_gate.hw.init = &init; 778 779 priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw); 780 if (WARN_ON(IS_ERR(priv->adc_clk))) 781 return PTR_ERR(priv->adc_clk); 782 783 return 0; 784 } 785 786 static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev) 787 { 788 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 789 u8 *buf, trimming_bits, trimming_mask, upper_adc_val; 790 struct device *dev = indio_dev->dev.parent; 791 struct nvmem_cell *temperature_calib; 792 size_t read_len; 793 int ret; 794 795 temperature_calib = devm_nvmem_cell_get(dev, "temperature_calib"); 796 if (IS_ERR(temperature_calib)) { 797 ret = PTR_ERR(temperature_calib); 798 799 /* 800 * leave the temperature sensor disabled if no calibration data 801 * was passed via nvmem-cells. 802 */ 803 if (ret == -ENODEV) 804 return 0; 805 806 return dev_err_probe(dev, ret, "failed to get temperature_calib cell\n"); 807 } 808 809 priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl"); 810 if (IS_ERR(priv->tsc_regmap)) 811 return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap), 812 "failed to get amlogic,hhi-sysctrl regmap\n"); 813 814 read_len = MESON_SAR_ADC_EFUSE_BYTES; 815 buf = nvmem_cell_read(temperature_calib, &read_len); 816 if (IS_ERR(buf)) 817 return dev_err_probe(dev, PTR_ERR(buf), "failed to read temperature_calib cell\n"); 818 if (read_len != MESON_SAR_ADC_EFUSE_BYTES) { 819 kfree(buf); 820 return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n"); 821 } 822 823 trimming_bits = priv->param->temperature_trimming_bits; 824 trimming_mask = BIT(trimming_bits) - 1; 825 826 priv->temperature_sensor_calibrated = 827 buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED; 828 priv->temperature_sensor_coefficient = buf[2] & trimming_mask; 829 830 upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL, 831 buf[3]); 832 833 priv->temperature_sensor_adc_val = buf[2]; 834 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE; 835 priv->temperature_sensor_adc_val >>= trimming_bits; 836 837 kfree(buf); 838 839 return 0; 840 } 841 842 static int meson_sar_adc_init(struct iio_dev *indio_dev) 843 { 844 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 845 struct device *dev = indio_dev->dev.parent; 846 int regval, i, ret; 847 848 /* 849 * make sure we start at CH7 input since the other muxes are only used 850 * for internal calibration. 851 */ 852 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT); 853 854 if (priv->param->has_bl30_integration) { 855 /* 856 * leave sampling delay and the input clocks as configured by 857 * BL30 to make sure BL30 gets the values it expects when 858 * reading the temperature sensor. 859 */ 860 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); 861 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) 862 return 0; 863 } 864 865 meson_sar_adc_stop_sample_engine(indio_dev); 866 867 /* 868 * disable this bit as seems to be only relevant for Meson6 (based 869 * on the vendor driver), which we don't support at the moment. 870 */ 871 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0, 872 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL); 873 874 /* disable all channels by default */ 875 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0); 876 877 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3, 878 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE); 879 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3, 880 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY); 881 882 /* delay between two samples = (10+1) * 1uS */ 883 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 884 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 885 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK, 886 10)); 887 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 888 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 889 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK, 890 0)); 891 892 /* delay between two samples = (10+1) * 1uS */ 893 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 894 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 895 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK, 896 10)); 897 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, 898 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 899 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK, 900 1)); 901 902 /* 903 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW 904 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1) 905 */ 906 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0); 907 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, 908 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 909 regval); 910 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1); 911 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, 912 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 913 regval); 914 915 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, 916 MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW); 917 918 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, 919 MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW); 920 921 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, 922 MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW); 923 924 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, 925 MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW); 926 927 /* 928 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW 929 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable 930 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and 931 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver. 932 */ 933 regval = 0; 934 for (i = 2; i <= 7; i++) 935 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i); 936 regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW; 937 regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW; 938 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval); 939 940 if (priv->temperature_sensor_calibrated) { 941 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 942 MESON_SAR_ADC_DELTA_10_TS_REVE1); 943 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 944 MESON_SAR_ADC_DELTA_10_TS_REVE0); 945 946 /* 947 * set bits [3:0] of the TSC (temperature sensor coefficient) 948 * to get the correct values when reading the temperature. 949 */ 950 regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK, 951 priv->temperature_sensor_coefficient); 952 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 953 MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval); 954 955 if (priv->param->temperature_trimming_bits == 5) { 956 if (priv->temperature_sensor_coefficient & BIT(4)) 957 regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4; 958 else 959 regval = 0; 960 961 /* 962 * bit [4] (the 5th bit when starting to count at 1) 963 * of the TSC is located in the HHI register area. 964 */ 965 regmap_update_bits(priv->tsc_regmap, 966 MESON_HHI_DPLL_TOP_0, 967 MESON_HHI_DPLL_TOP_0_TSC_BIT4, 968 regval); 969 } 970 } else { 971 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 972 MESON_SAR_ADC_DELTA_10_TS_REVE1); 973 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 974 MESON_SAR_ADC_DELTA_10_TS_REVE0); 975 } 976 977 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN, 978 priv->param->disable_ring_counter); 979 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, 980 MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN, 981 regval); 982 983 if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11) { 984 regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc); 985 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, 986 MESON_SAR_ADC_REG11_EOC, regval); 987 988 if (priv->param->has_vref_select) { 989 regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_SEL, 990 priv->param->vref_select); 991 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, 992 MESON_SAR_ADC_REG11_VREF_SEL, regval); 993 } 994 995 regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE, 996 priv->param->vref_voltage); 997 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, 998 MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval); 999 1000 regval = FIELD_PREP(MESON_SAR_ADC_REG11_CMV_SEL, 1001 priv->param->cmv_select); 1002 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, 1003 MESON_SAR_ADC_REG11_CMV_SEL, regval); 1004 1005 if (priv->param->enable_mpll_clock_workaround) { 1006 dev_warn(dev, 1007 "Enabling unknown bits to make the MPLL clocks work. This may change so always update dtbs and kernel together\n"); 1008 regmap_write(priv->regmap, MESON_SAR_ADC_REG12, 1009 MESON_SAR_ADC_REG12_MPLL0_UNKNOWN | 1010 MESON_SAR_ADC_REG12_MPLL1_UNKNOWN | 1011 MESON_SAR_ADC_REG12_MPLL2_UNKNOWN); 1012 } 1013 } 1014 1015 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); 1016 if (ret) 1017 return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n"); 1018 1019 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate); 1020 if (ret) 1021 return dev_err_probe(dev, ret, "failed to set adc clock rate\n"); 1022 1023 return 0; 1024 } 1025 1026 static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off) 1027 { 1028 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 1029 1030 if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11) 1031 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, 1032 MESON_SAR_ADC_REG11_BANDGAP_EN, 1033 on_off ? MESON_SAR_ADC_REG11_BANDGAP_EN : 0); 1034 else 1035 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, 1036 MESON_SAR_ADC_DELTA_10_TS_VBG_EN, 1037 on_off ? MESON_SAR_ADC_DELTA_10_TS_VBG_EN : 0); 1038 } 1039 1040 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) 1041 { 1042 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 1043 struct device *dev = indio_dev->dev.parent; 1044 int ret; 1045 u32 regval; 1046 1047 ret = meson_sar_adc_lock(indio_dev); 1048 if (ret) { 1049 dev_err(dev, "failed to lock adc\n"); 1050 goto err_lock; 1051 } 1052 1053 ret = regulator_enable(priv->vref); 1054 if (ret < 0) { 1055 dev_err(dev, "failed to enable vref regulator\n"); 1056 goto err_vref; 1057 } 1058 1059 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1); 1060 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, 1061 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval); 1062 1063 meson_sar_adc_set_bandgap(indio_dev, true); 1064 1065 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3, 1066 MESON_SAR_ADC_REG3_ADC_EN); 1067 1068 udelay(5); 1069 1070 ret = clk_prepare_enable(priv->adc_clk); 1071 if (ret) { 1072 dev_err(dev, "failed to enable adc clk\n"); 1073 goto err_adc_clk; 1074 } 1075 1076 meson_sar_adc_unlock(indio_dev); 1077 1078 return 0; 1079 1080 err_adc_clk: 1081 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3, 1082 MESON_SAR_ADC_REG3_ADC_EN); 1083 meson_sar_adc_set_bandgap(indio_dev, false); 1084 regulator_disable(priv->vref); 1085 err_vref: 1086 meson_sar_adc_unlock(indio_dev); 1087 err_lock: 1088 return ret; 1089 } 1090 1091 static void meson_sar_adc_hw_disable(struct iio_dev *indio_dev) 1092 { 1093 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 1094 int ret; 1095 1096 /* 1097 * If taking the lock fails we have to assume that BL30 is broken. The 1098 * best we can do then is to release the resources anyhow. 1099 */ 1100 ret = meson_sar_adc_lock(indio_dev); 1101 if (ret) 1102 dev_err(indio_dev->dev.parent, "Failed to lock ADC (%pE)\n", ERR_PTR(ret)); 1103 1104 clk_disable_unprepare(priv->adc_clk); 1105 1106 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3, 1107 MESON_SAR_ADC_REG3_ADC_EN); 1108 1109 meson_sar_adc_set_bandgap(indio_dev, false); 1110 1111 regulator_disable(priv->vref); 1112 1113 if (!ret) 1114 meson_sar_adc_unlock(indio_dev); 1115 } 1116 1117 static irqreturn_t meson_sar_adc_irq(int irq, void *data) 1118 { 1119 struct iio_dev *indio_dev = data; 1120 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 1121 unsigned int cnt, threshold; 1122 u32 regval; 1123 1124 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); 1125 cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); 1126 threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval); 1127 1128 if (cnt < threshold) 1129 return IRQ_NONE; 1130 1131 complete(&priv->done); 1132 1133 return IRQ_HANDLED; 1134 } 1135 1136 static int meson_sar_adc_calib(struct iio_dev *indio_dev) 1137 { 1138 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 1139 int ret, nominal0, nominal1, value0, value1; 1140 1141 /* use points 25% and 75% for calibration */ 1142 nominal0 = (1 << priv->param->resolution) / 4; 1143 nominal1 = (1 << priv->param->resolution) * 3 / 4; 1144 1145 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4); 1146 usleep_range(10, 20); 1147 ret = meson_sar_adc_get_sample(indio_dev, 1148 find_channel_by_num(indio_dev, 1149 NUM_MUX_1_VDD_DIV4), 1150 MEAN_AVERAGING, EIGHT_SAMPLES, &value0); 1151 if (ret < 0) 1152 goto out; 1153 1154 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4); 1155 usleep_range(10, 20); 1156 ret = meson_sar_adc_get_sample(indio_dev, 1157 find_channel_by_num(indio_dev, 1158 NUM_MUX_3_VDD_MUL3_DIV4), 1159 MEAN_AVERAGING, EIGHT_SAMPLES, &value1); 1160 if (ret < 0) 1161 goto out; 1162 1163 if (value1 <= value0) { 1164 ret = -EINVAL; 1165 goto out; 1166 } 1167 1168 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION, 1169 value1 - value0); 1170 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale, 1171 MILLION); 1172 ret = 0; 1173 out: 1174 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT); 1175 1176 return ret; 1177 } 1178 1179 static int read_label(struct iio_dev *indio_dev, 1180 struct iio_chan_spec const *chan, 1181 char *label) 1182 { 1183 if (chan->type == IIO_TEMP) 1184 return sprintf(label, "temp-sensor\n"); 1185 if (chan->type == IIO_VOLTAGE && chan->channel >= NUM_MUX_0_VSS) 1186 return sprintf(label, "%s\n", 1187 chan7_mux_names[chan->channel - NUM_MUX_0_VSS]); 1188 if (chan->type == IIO_VOLTAGE) 1189 return sprintf(label, "channel-%d\n", chan->channel); 1190 return 0; 1191 } 1192 1193 static const struct iio_info meson_sar_adc_iio_info = { 1194 .read_raw = meson_sar_adc_iio_info_read_raw, 1195 .read_label = read_label, 1196 }; 1197 1198 static const struct meson_sar_adc_param meson_sar_adc_meson8_param = { 1199 .has_bl30_integration = false, 1200 .clock_rate = 1150000, 1201 .regmap_config = &meson_sar_adc_regmap_config_meson8, 1202 .resolution = 10, 1203 .temperature_trimming_bits = 4, 1204 .temperature_multiplier = 18 * 10000, 1205 .temperature_divider = 1024 * 10 * 85, 1206 }; 1207 1208 static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = { 1209 .has_bl30_integration = false, 1210 .clock_rate = 1150000, 1211 .regmap_config = &meson_sar_adc_regmap_config_meson8, 1212 .resolution = 10, 1213 .temperature_trimming_bits = 5, 1214 .temperature_multiplier = 10, 1215 .temperature_divider = 32, 1216 }; 1217 1218 static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = { 1219 .has_bl30_integration = true, 1220 .clock_rate = 1200000, 1221 .regmap_config = &meson_sar_adc_regmap_config_gxbb, 1222 .resolution = 10, 1223 .vref_voltage = 1, 1224 .cmv_select = 1, 1225 }; 1226 1227 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = { 1228 .has_bl30_integration = true, 1229 .clock_rate = 1200000, 1230 .regmap_config = &meson_sar_adc_regmap_config_gxbb, 1231 .resolution = 12, 1232 .disable_ring_counter = 1, 1233 .vref_voltage = 1, 1234 .cmv_select = 1, 1235 }; 1236 1237 static const struct meson_sar_adc_param meson_sar_adc_gxlx_param = { 1238 .has_bl30_integration = true, 1239 .clock_rate = 1200000, 1240 .regmap_config = &meson_sar_adc_regmap_config_gxbb, 1241 .resolution = 12, 1242 .disable_ring_counter = 1, 1243 .vref_voltage = 1, 1244 .cmv_select = true, 1245 .enable_mpll_clock_workaround = true, 1246 }; 1247 1248 static const struct meson_sar_adc_param meson_sar_adc_axg_param = { 1249 .has_bl30_integration = true, 1250 .clock_rate = 1200000, 1251 .regmap_config = &meson_sar_adc_regmap_config_gxbb, 1252 .resolution = 12, 1253 .disable_ring_counter = 1, 1254 .vref_voltage = 1, 1255 .has_vref_select = true, 1256 .vref_select = VREF_VDDA, 1257 .cmv_select = 1, 1258 }; 1259 1260 static const struct meson_sar_adc_param meson_sar_adc_g12a_param = { 1261 .has_bl30_integration = false, 1262 .clock_rate = 1200000, 1263 .regmap_config = &meson_sar_adc_regmap_config_gxbb, 1264 .resolution = 12, 1265 .disable_ring_counter = 1, 1266 .adc_eoc = 1, 1267 .has_vref_select = true, 1268 .vref_select = VREF_VDDA, 1269 }; 1270 1271 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { 1272 .param = &meson_sar_adc_meson8_param, 1273 .name = "meson-meson8-saradc", 1274 }; 1275 1276 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = { 1277 .param = &meson_sar_adc_meson8b_param, 1278 .name = "meson-meson8b-saradc", 1279 }; 1280 1281 static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = { 1282 .param = &meson_sar_adc_meson8b_param, 1283 .name = "meson-meson8m2-saradc", 1284 }; 1285 1286 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = { 1287 .param = &meson_sar_adc_gxbb_param, 1288 .name = "meson-gxbb-saradc", 1289 }; 1290 1291 static const struct meson_sar_adc_data meson_sar_adc_gxl_data = { 1292 .param = &meson_sar_adc_gxl_param, 1293 .name = "meson-gxl-saradc", 1294 }; 1295 1296 static const struct meson_sar_adc_data meson_sar_adc_gxlx_data = { 1297 .param = &meson_sar_adc_gxlx_param, 1298 .name = "meson-gxlx-saradc", 1299 }; 1300 1301 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = { 1302 .param = &meson_sar_adc_gxl_param, 1303 .name = "meson-gxm-saradc", 1304 }; 1305 1306 static const struct meson_sar_adc_data meson_sar_adc_axg_data = { 1307 .param = &meson_sar_adc_axg_param, 1308 .name = "meson-axg-saradc", 1309 }; 1310 1311 static const struct meson_sar_adc_data meson_sar_adc_g12a_data = { 1312 .param = &meson_sar_adc_g12a_param, 1313 .name = "meson-g12a-saradc", 1314 }; 1315 1316 static const struct of_device_id meson_sar_adc_of_match[] = { 1317 { 1318 .compatible = "amlogic,meson8-saradc", 1319 .data = &meson_sar_adc_meson8_data, 1320 }, { 1321 .compatible = "amlogic,meson8b-saradc", 1322 .data = &meson_sar_adc_meson8b_data, 1323 }, { 1324 .compatible = "amlogic,meson8m2-saradc", 1325 .data = &meson_sar_adc_meson8m2_data, 1326 }, { 1327 .compatible = "amlogic,meson-gxbb-saradc", 1328 .data = &meson_sar_adc_gxbb_data, 1329 }, { 1330 .compatible = "amlogic,meson-gxl-saradc", 1331 .data = &meson_sar_adc_gxl_data, 1332 }, { 1333 .compatible = "amlogic,meson-gxlx-saradc", 1334 .data = &meson_sar_adc_gxlx_data, 1335 }, { 1336 .compatible = "amlogic,meson-gxm-saradc", 1337 .data = &meson_sar_adc_gxm_data, 1338 }, { 1339 .compatible = "amlogic,meson-axg-saradc", 1340 .data = &meson_sar_adc_axg_data, 1341 }, { 1342 .compatible = "amlogic,meson-g12a-saradc", 1343 .data = &meson_sar_adc_g12a_data, 1344 }, 1345 { } 1346 }; 1347 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match); 1348 1349 static int meson_sar_adc_probe(struct platform_device *pdev) 1350 { 1351 const struct meson_sar_adc_data *match_data; 1352 struct meson_sar_adc_priv *priv; 1353 struct device *dev = &pdev->dev; 1354 struct iio_dev *indio_dev; 1355 void __iomem *base; 1356 int irq, ret; 1357 1358 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv)); 1359 if (!indio_dev) 1360 return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n"); 1361 1362 priv = iio_priv(indio_dev); 1363 init_completion(&priv->done); 1364 1365 match_data = of_device_get_match_data(dev); 1366 if (!match_data) 1367 return dev_err_probe(dev, -ENODEV, "failed to get match data\n"); 1368 1369 priv->param = match_data->param; 1370 1371 indio_dev->name = match_data->name; 1372 indio_dev->modes = INDIO_DIRECT_MODE; 1373 indio_dev->info = &meson_sar_adc_iio_info; 1374 1375 base = devm_platform_ioremap_resource(pdev, 0); 1376 if (IS_ERR(base)) 1377 return PTR_ERR(base); 1378 1379 priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config); 1380 if (IS_ERR(priv->regmap)) 1381 return dev_err_probe(dev, PTR_ERR(priv->regmap), "failed to init regmap\n"); 1382 1383 irq = irq_of_parse_and_map(dev->of_node, 0); 1384 if (!irq) 1385 return dev_err_probe(dev, -EINVAL, "failed to get irq\n"); 1386 1387 ret = devm_request_irq(dev, irq, meson_sar_adc_irq, IRQF_SHARED, dev_name(dev), indio_dev); 1388 if (ret) 1389 return dev_err_probe(dev, ret, "failed to request irq\n"); 1390 1391 priv->clkin = devm_clk_get(dev, "clkin"); 1392 if (IS_ERR(priv->clkin)) 1393 return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n"); 1394 1395 priv->core_clk = devm_clk_get_enabled(dev, "core"); 1396 if (IS_ERR(priv->core_clk)) 1397 return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n"); 1398 1399 priv->adc_clk = devm_clk_get_optional(dev, "adc_clk"); 1400 if (IS_ERR(priv->adc_clk)) 1401 return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n"); 1402 1403 priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel"); 1404 if (IS_ERR(priv->adc_sel_clk)) 1405 return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n"); 1406 1407 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ 1408 if (!priv->adc_clk) { 1409 ret = meson_sar_adc_clk_init(indio_dev, base); 1410 if (ret) 1411 return dev_err_probe(dev, ret, "failed to init internal clk\n"); 1412 } 1413 1414 priv->vref = devm_regulator_get(dev, "vref"); 1415 if (IS_ERR(priv->vref)) 1416 return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n"); 1417 1418 priv->calibscale = MILLION; 1419 1420 if (priv->param->temperature_trimming_bits) { 1421 ret = meson_sar_adc_temp_sensor_init(indio_dev); 1422 if (ret) 1423 return ret; 1424 } 1425 1426 if (priv->temperature_sensor_calibrated) { 1427 indio_dev->channels = meson_sar_adc_and_temp_iio_channels; 1428 indio_dev->num_channels = 1429 ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels); 1430 } else { 1431 indio_dev->channels = meson_sar_adc_iio_channels; 1432 indio_dev->num_channels = 1433 ARRAY_SIZE(meson_sar_adc_iio_channels); 1434 } 1435 1436 ret = meson_sar_adc_init(indio_dev); 1437 if (ret) 1438 goto err; 1439 1440 mutex_init(&priv->lock); 1441 1442 ret = meson_sar_adc_hw_enable(indio_dev); 1443 if (ret) 1444 goto err; 1445 1446 ret = meson_sar_adc_calib(indio_dev); 1447 if (ret) 1448 dev_warn(dev, "calibration failed\n"); 1449 1450 platform_set_drvdata(pdev, indio_dev); 1451 1452 ret = iio_device_register(indio_dev); 1453 if (ret) { 1454 dev_err_probe(dev, ret, "failed to register iio device\n"); 1455 goto err_hw; 1456 } 1457 1458 return 0; 1459 1460 err_hw: 1461 meson_sar_adc_hw_disable(indio_dev); 1462 err: 1463 return ret; 1464 } 1465 1466 static void meson_sar_adc_remove(struct platform_device *pdev) 1467 { 1468 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1469 1470 iio_device_unregister(indio_dev); 1471 1472 meson_sar_adc_hw_disable(indio_dev); 1473 } 1474 1475 static int meson_sar_adc_suspend(struct device *dev) 1476 { 1477 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1478 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 1479 1480 meson_sar_adc_hw_disable(indio_dev); 1481 1482 clk_disable_unprepare(priv->core_clk); 1483 1484 return 0; 1485 } 1486 1487 static int meson_sar_adc_resume(struct device *dev) 1488 { 1489 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1490 struct meson_sar_adc_priv *priv = iio_priv(indio_dev); 1491 int ret; 1492 1493 ret = clk_prepare_enable(priv->core_clk); 1494 if (ret) { 1495 dev_err(dev, "failed to enable core clk\n"); 1496 return ret; 1497 } 1498 1499 return meson_sar_adc_hw_enable(indio_dev); 1500 } 1501 1502 static DEFINE_SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops, 1503 meson_sar_adc_suspend, meson_sar_adc_resume); 1504 1505 static struct platform_driver meson_sar_adc_driver = { 1506 .probe = meson_sar_adc_probe, 1507 .remove = meson_sar_adc_remove, 1508 .driver = { 1509 .name = "meson-saradc", 1510 .of_match_table = meson_sar_adc_of_match, 1511 .pm = pm_sleep_ptr(&meson_sar_adc_pm_ops), 1512 }, 1513 }; 1514 1515 module_platform_driver(meson_sar_adc_driver); 1516 1517 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 1518 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver"); 1519 MODULE_LICENSE("GPL v2"); 1520