1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Microchip MCP3911, Two-channel Analog Front End 4 * 5 * Copyright (C) 2018 Marcus Folkesson <marcus.folkesson@gmail.com> 6 * Copyright (C) 2018 Kent Gustavsson <kent@minoris.se> 7 */ 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dev_printk.h> 14 #include <linux/err.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/module.h> 17 #include <linux/property.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/spi/spi.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/triggered_buffer.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/trigger.h> 26 27 #include <linux/unaligned.h> 28 29 #define MCP3911_REG_CHANNEL0 0x00 30 #define MCP3911_REG_CHANNEL1 0x03 31 #define MCP3911_REG_MOD 0x06 32 #define MCP3911_REG_PHASE 0x07 33 #define MCP3911_REG_GAIN 0x09 34 #define MCP3911_GAIN_MASK(ch) (GENMASK(2, 0) << 3 * (ch)) 35 #define MCP3911_GAIN_VAL(ch, val) ((val << 3 * (ch)) & MCP3911_GAIN_MASK(ch)) 36 37 #define MCP3911_REG_STATUSCOM 0x0a 38 #define MCP3911_STATUSCOM_DRHIZ BIT(12) 39 #define MCP3911_STATUSCOM_READ GENMASK(7, 6) 40 #define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4) 41 #define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3) 42 #define MCP3911_STATUSCOM_EN_OFFCAL BIT(2) 43 #define MCP3911_STATUSCOM_EN_GAINCAL BIT(1) 44 45 #define MCP3911_REG_CONFIG 0x0c 46 #define MCP3911_CONFIG_CLKEXT BIT(1) 47 #define MCP3911_CONFIG_VREFEXT BIT(2) 48 #define MCP3911_CONFIG_OSR GENMASK(13, 11) 49 50 #define MCP3911_REG_OFFCAL_CH0 0x0e 51 #define MCP3911_REG_GAINCAL_CH0 0x11 52 #define MCP3911_REG_OFFCAL_CH1 0x14 53 #define MCP3911_REG_GAINCAL_CH1 0x17 54 #define MCP3911_REG_VREFCAL 0x1a 55 56 #define MCP3911_CHANNEL(ch) (MCP3911_REG_CHANNEL0 + (ch) * 3) 57 #define MCP3911_OFFCAL(ch) (MCP3911_REG_OFFCAL_CH0 + (ch) * 6) 58 59 /* Internal voltage reference in mV */ 60 #define MCP3911_INT_VREF_MV 1200 61 62 #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 6) | (1 << 0)) & 0xff) 63 #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff) 64 #define MCP3911_REG_MASK GENMASK(4, 1) 65 66 #define MCP3911_NUM_SCALES 6 67 68 /* Registers compatible with MCP3910 */ 69 #define MCP3910_REG_STATUSCOM 0x0c 70 #define MCP3910_STATUSCOM_READ GENMASK(23, 22) 71 #define MCP3910_STATUSCOM_DRHIZ BIT(20) 72 73 #define MCP3910_REG_GAIN 0x0b 74 75 #define MCP3910_REG_CONFIG0 0x0d 76 #define MCP3910_CONFIG0_EN_OFFCAL BIT(23) 77 #define MCP3910_CONFIG0_OSR GENMASK(15, 13) 78 79 #define MCP3910_REG_CONFIG1 0x0e 80 #define MCP3910_CONFIG1_CLKEXT BIT(6) 81 #define MCP3910_CONFIG1_VREFEXT BIT(7) 82 83 #define MCP3910_CHANNEL(ch) (MCP3911_REG_CHANNEL0 + (ch)) 84 85 #define MCP3910_REG_OFFCAL_CH0 0x0f 86 #define MCP3910_OFFCAL(ch) (MCP3910_REG_OFFCAL_CH0 + (ch) * 6) 87 88 /* Maximal number of channels used by the MCP39XX family */ 89 #define MCP39XX_MAX_NUM_CHANNELS 8 90 91 static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 }; 92 static u32 mcp3911_scale_table[MCP3911_NUM_SCALES][2]; 93 94 enum mcp3911_id { 95 MCP3910, 96 MCP3911, 97 MCP3912, 98 MCP3913, 99 MCP3914, 100 MCP3918, 101 MCP3919, 102 }; 103 104 struct mcp3911; 105 struct mcp3911_chip_info { 106 const struct iio_chan_spec *channels; 107 unsigned int num_channels; 108 109 int (*config)(struct mcp3911 *adc, bool external_vref); 110 int (*get_osr)(struct mcp3911 *adc, u32 *val); 111 int (*set_osr)(struct mcp3911 *adc, u32 val); 112 int (*enable_offset)(struct mcp3911 *adc, bool enable); 113 int (*get_offset)(struct mcp3911 *adc, int channel, int *val); 114 int (*set_offset)(struct mcp3911 *adc, int channel, int val); 115 int (*set_scale)(struct mcp3911 *adc, int channel, u32 val); 116 int (*get_raw)(struct mcp3911 *adc, int channel, int *val); 117 }; 118 119 struct mcp3911 { 120 struct spi_device *spi; 121 struct mutex lock; 122 struct clk *clki; 123 u32 dev_addr; 124 struct iio_trigger *trig; 125 u32 gain[MCP39XX_MAX_NUM_CHANNELS]; 126 const struct mcp3911_chip_info *chip; 127 struct { 128 u32 channels[MCP39XX_MAX_NUM_CHANNELS]; 129 aligned_s64 ts; 130 } scan; 131 132 u8 tx_buf __aligned(IIO_DMA_MINALIGN); 133 u8 rx_buf[MCP39XX_MAX_NUM_CHANNELS * 3]; 134 }; 135 136 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) 137 { 138 int ret; 139 140 reg = MCP3911_REG_READ(reg, adc->dev_addr); 141 ret = spi_write_then_read(adc->spi, ®, 1, val, len); 142 if (ret < 0) 143 return ret; 144 145 be32_to_cpus(val); 146 *val >>= ((4 - len) * 8); 147 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val, 148 FIELD_GET(MCP3911_REG_MASK, reg)); 149 return ret; 150 } 151 152 static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len) 153 { 154 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg); 155 156 val <<= (3 - len) * 8; 157 cpu_to_be32s(&val); 158 val |= MCP3911_REG_WRITE(reg, adc->dev_addr); 159 160 return spi_write(adc->spi, &val, len + 1); 161 } 162 163 static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, u32 val, u8 len) 164 { 165 u32 tmp; 166 int ret; 167 168 ret = mcp3911_read(adc, reg, &tmp, len); 169 if (ret) 170 return ret; 171 172 val &= mask; 173 val |= tmp & ~mask; 174 return mcp3911_write(adc, reg, val, len); 175 } 176 177 static int mcp3911_read_s24(struct mcp3911 *const adc, u8 const reg, s32 *const val) 178 { 179 u32 uval; 180 int const ret = mcp3911_read(adc, reg, &uval, 3); 181 182 if (ret) 183 return ret; 184 185 *val = sign_extend32(uval, 23); 186 return ret; 187 } 188 189 static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable) 190 { 191 unsigned int mask = MCP3910_CONFIG0_EN_OFFCAL; 192 unsigned int value = enable ? mask : 0; 193 194 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, value, 3); 195 } 196 197 static int mcp3910_get_offset(struct mcp3911 *adc, int channel, int *val) 198 { 199 return mcp3911_read(adc, MCP3910_OFFCAL(channel), val, 3); 200 } 201 202 static int mcp3910_set_offset(struct mcp3911 *adc, int channel, int val) 203 { 204 int ret; 205 206 ret = mcp3911_write(adc, MCP3910_OFFCAL(channel), val, 3); 207 if (ret) 208 return ret; 209 210 return adc->chip->enable_offset(adc, 1); 211 } 212 213 static int mcp3910_get_raw(struct mcp3911 *adc, int channel, s32 *val) 214 { 215 return mcp3911_read_s24(adc, MCP3910_CHANNEL(channel), val); 216 } 217 218 static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable) 219 { 220 unsigned int mask = MCP3911_STATUSCOM_EN_OFFCAL; 221 unsigned int value = enable ? mask : 0; 222 223 return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, value, 2); 224 } 225 226 static int mcp3911_get_offset(struct mcp3911 *adc, int channel, int *val) 227 { 228 return mcp3911_read(adc, MCP3911_OFFCAL(channel), val, 3); 229 } 230 231 static int mcp3911_set_offset(struct mcp3911 *adc, int channel, int val) 232 { 233 int ret; 234 235 ret = mcp3911_write(adc, MCP3911_OFFCAL(channel), val, 3); 236 if (ret) 237 return ret; 238 239 return adc->chip->enable_offset(adc, 1); 240 } 241 242 static int mcp3911_get_raw(struct mcp3911 *adc, int channel, s32 *val) 243 { 244 return mcp3911_read_s24(adc, MCP3911_CHANNEL(channel), val); 245 } 246 247 static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val) 248 { 249 int ret; 250 unsigned int osr; 251 252 ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, 3); 253 if (ret) 254 return ret; 255 256 osr = FIELD_GET(MCP3910_CONFIG0_OSR, *val); 257 *val = 32 << osr; 258 return 0; 259 } 260 261 static int mcp3910_set_osr(struct mcp3911 *adc, u32 val) 262 { 263 unsigned int osr = FIELD_PREP(MCP3910_CONFIG0_OSR, val); 264 unsigned int mask = MCP3910_CONFIG0_OSR; 265 266 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, osr, 3); 267 } 268 269 static int mcp3911_set_osr(struct mcp3911 *adc, u32 val) 270 { 271 unsigned int osr = FIELD_PREP(MCP3911_CONFIG_OSR, val); 272 unsigned int mask = MCP3911_CONFIG_OSR; 273 274 return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, osr, 2); 275 } 276 277 static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val) 278 { 279 int ret; 280 unsigned int osr; 281 282 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2); 283 if (ret) 284 return ret; 285 286 osr = FIELD_GET(MCP3911_CONFIG_OSR, *val); 287 *val = 32 << osr; 288 return ret; 289 } 290 291 static int mcp3910_set_scale(struct mcp3911 *adc, int channel, u32 val) 292 { 293 return mcp3911_update(adc, MCP3910_REG_GAIN, 294 MCP3911_GAIN_MASK(channel), 295 MCP3911_GAIN_VAL(channel, val), 3); 296 } 297 298 static int mcp3911_set_scale(struct mcp3911 *adc, int channel, u32 val) 299 { 300 return mcp3911_update(adc, MCP3911_REG_GAIN, 301 MCP3911_GAIN_MASK(channel), 302 MCP3911_GAIN_VAL(channel, val), 1); 303 } 304 305 static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev, 306 struct iio_chan_spec const *chan, 307 long mask) 308 { 309 switch (mask) { 310 case IIO_CHAN_INFO_SCALE: 311 return IIO_VAL_INT_PLUS_NANO; 312 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 313 return IIO_VAL_INT; 314 default: 315 return IIO_VAL_INT_PLUS_NANO; 316 } 317 } 318 319 static int mcp3911_read_avail(struct iio_dev *indio_dev, 320 struct iio_chan_spec const *chan, 321 const int **vals, int *type, int *length, 322 long info) 323 { 324 switch (info) { 325 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 326 *type = IIO_VAL_INT; 327 *vals = mcp3911_osr_table; 328 *length = ARRAY_SIZE(mcp3911_osr_table); 329 return IIO_AVAIL_LIST; 330 case IIO_CHAN_INFO_SCALE: 331 *type = IIO_VAL_INT_PLUS_NANO; 332 *vals = (int *)mcp3911_scale_table; 333 *length = ARRAY_SIZE(mcp3911_scale_table) * 2; 334 return IIO_AVAIL_LIST; 335 default: 336 return -EINVAL; 337 } 338 } 339 340 static int mcp3911_read_raw(struct iio_dev *indio_dev, 341 struct iio_chan_spec const *channel, int *val, 342 int *val2, long mask) 343 { 344 struct mcp3911 *adc = iio_priv(indio_dev); 345 int ret; 346 347 guard(mutex)(&adc->lock); 348 switch (mask) { 349 case IIO_CHAN_INFO_RAW: 350 ret = adc->chip->get_raw(adc, channel->channel, val); 351 if (ret) 352 return ret; 353 return IIO_VAL_INT; 354 case IIO_CHAN_INFO_OFFSET: 355 ret = adc->chip->get_offset(adc, channel->channel, val); 356 if (ret) 357 return ret; 358 359 return IIO_VAL_INT; 360 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 361 ret = adc->chip->get_osr(adc, val); 362 if (ret) 363 return ret; 364 365 return IIO_VAL_INT; 366 case IIO_CHAN_INFO_SCALE: 367 *val = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][0]; 368 *val2 = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][1]; 369 return IIO_VAL_INT_PLUS_NANO; 370 default: 371 return -EINVAL; 372 } 373 } 374 375 static int mcp3911_write_raw(struct iio_dev *indio_dev, 376 struct iio_chan_spec const *channel, int val, 377 int val2, long mask) 378 { 379 struct mcp3911 *adc = iio_priv(indio_dev); 380 381 guard(mutex)(&adc->lock); 382 switch (mask) { 383 case IIO_CHAN_INFO_SCALE: 384 for (int i = 0; i < MCP3911_NUM_SCALES; i++) { 385 if (val == mcp3911_scale_table[i][0] && 386 val2 == mcp3911_scale_table[i][1]) { 387 388 adc->gain[channel->channel] = BIT(i); 389 return adc->chip->set_scale(adc, channel->channel, i); 390 } 391 } 392 return -EINVAL; 393 case IIO_CHAN_INFO_OFFSET: 394 if (val2 != 0) 395 return -EINVAL; 396 397 return adc->chip->set_offset(adc, channel->channel, val); 398 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 399 for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) { 400 if (val == mcp3911_osr_table[i]) { 401 return adc->chip->set_osr(adc, i); 402 } 403 } 404 return -EINVAL; 405 default: 406 return -EINVAL; 407 } 408 } 409 410 static int mcp3911_calc_scale_table(u32 vref_mv) 411 { 412 u32 div; 413 u64 tmp; 414 415 /* 416 * For 24-bit Conversion 417 * Raw = ((Voltage)/(Vref) * 2^23 * Gain * 1.5 418 * Voltage = Raw * (Vref)/(2^23 * Gain * 1.5) 419 * 420 * ref = Reference voltage 421 * div = (2^23 * 1.5 * gain) = 12582912 * gain 422 */ 423 for (int i = 0; i < MCP3911_NUM_SCALES; i++) { 424 div = 12582912 * BIT(i); 425 tmp = div_s64((s64)vref_mv * 1000000000LL, div); 426 427 mcp3911_scale_table[i][0] = 0; 428 mcp3911_scale_table[i][1] = tmp; 429 } 430 431 return 0; 432 } 433 434 #define MCP3911_CHAN(idx) { \ 435 .type = IIO_VOLTAGE, \ 436 .indexed = 1, \ 437 .channel = idx, \ 438 .scan_index = idx, \ 439 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 440 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 441 BIT(IIO_CHAN_INFO_OFFSET) | \ 442 BIT(IIO_CHAN_INFO_SCALE), \ 443 .info_mask_shared_by_type_available = \ 444 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 445 .info_mask_separate_available = \ 446 BIT(IIO_CHAN_INFO_SCALE), \ 447 .scan_type = { \ 448 .sign = 's', \ 449 .realbits = 24, \ 450 .storagebits = 32, \ 451 .endianness = IIO_BE, \ 452 }, \ 453 } 454 455 static const struct iio_chan_spec mcp3910_channels[] = { 456 MCP3911_CHAN(0), 457 MCP3911_CHAN(1), 458 IIO_CHAN_SOFT_TIMESTAMP(2), 459 }; 460 461 static const struct iio_chan_spec mcp3911_channels[] = { 462 MCP3911_CHAN(0), 463 MCP3911_CHAN(1), 464 IIO_CHAN_SOFT_TIMESTAMP(2), 465 }; 466 467 static const struct iio_chan_spec mcp3912_channels[] = { 468 MCP3911_CHAN(0), 469 MCP3911_CHAN(1), 470 MCP3911_CHAN(2), 471 MCP3911_CHAN(3), 472 IIO_CHAN_SOFT_TIMESTAMP(4), 473 }; 474 475 static const struct iio_chan_spec mcp3913_channels[] = { 476 MCP3911_CHAN(0), 477 MCP3911_CHAN(1), 478 MCP3911_CHAN(2), 479 MCP3911_CHAN(3), 480 MCP3911_CHAN(4), 481 MCP3911_CHAN(5), 482 IIO_CHAN_SOFT_TIMESTAMP(6), 483 }; 484 485 static const struct iio_chan_spec mcp3914_channels[] = { 486 MCP3911_CHAN(0), 487 MCP3911_CHAN(1), 488 MCP3911_CHAN(2), 489 MCP3911_CHAN(3), 490 MCP3911_CHAN(4), 491 MCP3911_CHAN(5), 492 MCP3911_CHAN(6), 493 MCP3911_CHAN(7), 494 IIO_CHAN_SOFT_TIMESTAMP(8), 495 }; 496 497 static const struct iio_chan_spec mcp3918_channels[] = { 498 MCP3911_CHAN(0), 499 IIO_CHAN_SOFT_TIMESTAMP(1), 500 }; 501 502 static const struct iio_chan_spec mcp3919_channels[] = { 503 MCP3911_CHAN(0), 504 MCP3911_CHAN(1), 505 MCP3911_CHAN(2), 506 IIO_CHAN_SOFT_TIMESTAMP(3), 507 }; 508 509 static irqreturn_t mcp3911_trigger_handler(int irq, void *p) 510 { 511 struct iio_poll_func *pf = p; 512 struct iio_dev *indio_dev = pf->indio_dev; 513 struct mcp3911 *adc = iio_priv(indio_dev); 514 struct device *dev = &adc->spi->dev; 515 struct spi_transfer xfer[] = { 516 { 517 .tx_buf = &adc->tx_buf, 518 .len = 1, 519 }, { 520 .rx_buf = adc->rx_buf, 521 .len = (adc->chip->num_channels - 1) * 3, 522 }, 523 }; 524 int scan_index; 525 int i = 0; 526 int ret; 527 528 guard(mutex)(&adc->lock); 529 adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr); 530 ret = spi_sync_transfer(adc->spi, xfer, ARRAY_SIZE(xfer)); 531 if (ret < 0) { 532 dev_warn(dev, "failed to get conversion data\n"); 533 goto out; 534 } 535 536 iio_for_each_active_channel(indio_dev, scan_index) { 537 const struct iio_chan_spec *scan_chan = &indio_dev->channels[scan_index]; 538 539 adc->scan.channels[i] = get_unaligned_be24(&adc->rx_buf[scan_chan->channel * 3]); 540 i++; 541 } 542 iio_push_to_buffers_with_ts(indio_dev, &adc->scan, sizeof(adc->scan), 543 iio_get_time_ns(indio_dev)); 544 out: 545 iio_trigger_notify_done(indio_dev->trig); 546 547 return IRQ_HANDLED; 548 } 549 550 static const struct iio_info mcp3911_info = { 551 .read_raw = mcp3911_read_raw, 552 .write_raw = mcp3911_write_raw, 553 .read_avail = mcp3911_read_avail, 554 .write_raw_get_fmt = mcp3911_write_raw_get_fmt, 555 }; 556 557 static int mcp3911_config(struct mcp3911 *adc, bool external_vref) 558 { 559 struct device *dev = &adc->spi->dev; 560 u32 regval; 561 int ret; 562 563 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, ®val, 2); 564 if (ret) 565 return ret; 566 567 regval &= ~MCP3911_CONFIG_VREFEXT; 568 if (external_vref) { 569 dev_dbg(dev, "use external voltage reference\n"); 570 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1); 571 } else { 572 dev_dbg(dev, "use internal voltage reference (1.2V)\n"); 573 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0); 574 } 575 576 regval &= ~MCP3911_CONFIG_CLKEXT; 577 if (adc->clki) { 578 dev_dbg(dev, "use external clock as clocksource\n"); 579 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1); 580 } else { 581 dev_dbg(dev, "use crystal oscillator as clocksource\n"); 582 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0); 583 } 584 585 ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2); 586 if (ret) 587 return ret; 588 589 ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, ®val, 2); 590 if (ret) 591 return ret; 592 593 /* Address counter incremented, cycle through register types */ 594 regval &= ~MCP3911_STATUSCOM_READ; 595 regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02); 596 597 regval &= ~MCP3911_STATUSCOM_DRHIZ; 598 if (device_property_read_bool(dev, "microchip,data-ready-hiz")) 599 regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 0); 600 else 601 regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 1); 602 603 /* Disable offset to ignore any old values in offset register */ 604 regval &= ~MCP3911_STATUSCOM_EN_OFFCAL; 605 606 ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2); 607 if (ret) 608 return ret; 609 610 /* Set gain to 1 for all channels */ 611 ret = mcp3911_read(adc, MCP3911_REG_GAIN, ®val, 1); 612 if (ret) 613 return ret; 614 615 for (int i = 0; i < adc->chip->num_channels - 1; i++) { 616 adc->gain[i] = 1; 617 regval &= ~MCP3911_GAIN_MASK(i); 618 } 619 620 return mcp3911_write(adc, MCP3911_REG_GAIN, regval, 1); 621 } 622 623 static int mcp3910_config(struct mcp3911 *adc, bool external_vref) 624 { 625 struct device *dev = &adc->spi->dev; 626 u32 regval; 627 int ret; 628 629 ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, ®val, 3); 630 if (ret) 631 return ret; 632 633 regval &= ~MCP3910_CONFIG1_VREFEXT; 634 if (external_vref) { 635 dev_dbg(dev, "use external voltage reference\n"); 636 regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 1); 637 } else { 638 dev_dbg(dev, "use internal voltage reference (1.2V)\n"); 639 regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 0); 640 } 641 642 regval &= ~MCP3910_CONFIG1_CLKEXT; 643 if (adc->clki) { 644 dev_dbg(dev, "use external clock as clocksource\n"); 645 regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 1); 646 } else { 647 dev_dbg(dev, "use crystal oscillator as clocksource\n"); 648 regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 0); 649 } 650 651 ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, regval, 3); 652 if (ret) 653 return ret; 654 655 ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, ®val, 3); 656 if (ret) 657 return ret; 658 659 /* Address counter incremented, cycle through register types */ 660 regval &= ~MCP3910_STATUSCOM_READ; 661 regval |= FIELD_PREP(MCP3910_STATUSCOM_READ, 0x02); 662 663 regval &= ~MCP3910_STATUSCOM_DRHIZ; 664 if (device_property_read_bool(dev, "microchip,data-ready-hiz")) 665 regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 0); 666 else 667 regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 1); 668 669 ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, regval, 3); 670 if (ret) 671 return ret; 672 673 /* Set gain to 1 for all channels */ 674 ret = mcp3911_read(adc, MCP3910_REG_GAIN, ®val, 3); 675 if (ret) 676 return ret; 677 678 for (int i = 0; i < adc->chip->num_channels - 1; i++) { 679 adc->gain[i] = 1; 680 regval &= ~MCP3911_GAIN_MASK(i); 681 } 682 ret = mcp3911_write(adc, MCP3910_REG_GAIN, regval, 3); 683 if (ret) 684 return ret; 685 686 /* Disable offset to ignore any old values in offset register */ 687 return adc->chip->enable_offset(adc, 0); 688 } 689 690 static int mcp3911_set_trigger_state(struct iio_trigger *trig, bool enable) 691 { 692 struct mcp3911 *adc = iio_trigger_get_drvdata(trig); 693 694 if (enable) 695 enable_irq(adc->spi->irq); 696 else 697 disable_irq(adc->spi->irq); 698 699 return 0; 700 } 701 702 static const struct iio_trigger_ops mcp3911_trigger_ops = { 703 .validate_device = iio_trigger_validate_own_device, 704 .set_trigger_state = mcp3911_set_trigger_state, 705 }; 706 707 static int mcp3911_probe(struct spi_device *spi) 708 { 709 struct device *dev = &spi->dev; 710 struct gpio_desc *gpio_reset; 711 struct iio_dev *indio_dev; 712 struct mcp3911 *adc; 713 bool external_vref; 714 u32 vref_mv; 715 int ret; 716 717 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 718 if (!indio_dev) 719 return -ENOMEM; 720 721 adc = iio_priv(indio_dev); 722 adc->spi = spi; 723 adc->chip = spi_get_device_match_data(spi); 724 725 ret = devm_regulator_get_enable_read_voltage(dev, "vref"); 726 if (ret < 0 && ret != -ENODEV) 727 return dev_err_probe(dev, ret, "failed to get vref voltage\n"); 728 729 external_vref = ret != -ENODEV; 730 vref_mv = external_vref ? ret / 1000 : MCP3911_INT_VREF_MV; 731 732 adc->clki = devm_clk_get_enabled(dev, NULL); 733 if (IS_ERR(adc->clki)) { 734 if (PTR_ERR(adc->clki) == -ENOENT) { 735 adc->clki = NULL; 736 } else { 737 return dev_err_probe(dev, PTR_ERR(adc->clki), "failed to get adc clk\n"); 738 } 739 } 740 741 /* 742 * Fallback to "device-addr" due to historical mismatch between 743 * dt-bindings and implementation. 744 */ 745 ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr); 746 if (ret) 747 device_property_read_u32(dev, "device-addr", &adc->dev_addr); 748 if (adc->dev_addr > 3) { 749 return dev_err_probe(dev, -EINVAL, 750 "invalid device address (%i). Must be in range 0-3.\n", 751 adc->dev_addr); 752 } 753 dev_dbg(dev, "use device address %i\n", adc->dev_addr); 754 755 gpio_reset = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_HIGH); 756 if (IS_ERR(gpio_reset)) 757 return dev_err_probe(dev, PTR_ERR(gpio_reset), 758 "Cannot get reset GPIO\n"); 759 760 if (gpio_reset) { 761 gpiod_set_value_cansleep(gpio_reset, 0); 762 763 /* 764 * Settling time after Hard Reset Mode (determined experimentally): 765 * 330 micro-seconds are too few; 470 micro-seconds are sufficient. 766 * Just in case, we add some safety factor... 767 */ 768 fsleep(600); 769 } 770 771 ret = adc->chip->config(adc, external_vref); 772 if (ret) 773 return ret; 774 775 ret = mcp3911_calc_scale_table(vref_mv); 776 if (ret) 777 return ret; 778 779 /* Set gain to 1 for all channels */ 780 for (int i = 0; i < adc->chip->num_channels - 1; i++) { 781 adc->gain[i] = 1; 782 ret = mcp3911_update(adc, MCP3911_REG_GAIN, 783 MCP3911_GAIN_MASK(i), 784 MCP3911_GAIN_VAL(i, 0), 1); 785 if (ret) 786 return ret; 787 } 788 789 indio_dev->name = spi_get_device_id(spi)->name; 790 indio_dev->modes = INDIO_DIRECT_MODE; 791 indio_dev->info = &mcp3911_info; 792 spi_set_drvdata(spi, indio_dev); 793 794 indio_dev->channels = adc->chip->channels; 795 indio_dev->num_channels = adc->chip->num_channels; 796 797 mutex_init(&adc->lock); 798 799 if (spi->irq > 0) { 800 adc->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, 801 iio_device_id(indio_dev)); 802 if (!adc->trig) 803 return -ENOMEM; 804 805 adc->trig->ops = &mcp3911_trigger_ops; 806 iio_trigger_set_drvdata(adc->trig, adc); 807 ret = devm_iio_trigger_register(dev, adc->trig); 808 if (ret) 809 return ret; 810 811 /* 812 * The device generates interrupts as long as it is powered up. 813 * Some platforms might not allow the option to power it down so 814 * don't enable the interrupt to avoid extra load on the system. 815 */ 816 ret = devm_request_irq(dev, spi->irq, &iio_trigger_generic_data_rdy_poll, 817 IRQF_NO_AUTOEN | IRQF_NO_THREAD, 818 indio_dev->name, adc->trig); 819 if (ret) 820 return ret; 821 } 822 823 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 824 mcp3911_trigger_handler, NULL); 825 if (ret) 826 return ret; 827 828 return devm_iio_device_register(dev, indio_dev); 829 } 830 831 static const struct mcp3911_chip_info mcp3911_chip_info[] = { 832 [MCP3910] = { 833 .channels = mcp3910_channels, 834 .num_channels = ARRAY_SIZE(mcp3910_channels), 835 .config = mcp3910_config, 836 .get_osr = mcp3910_get_osr, 837 .set_osr = mcp3910_set_osr, 838 .enable_offset = mcp3910_enable_offset, 839 .get_offset = mcp3910_get_offset, 840 .set_offset = mcp3910_set_offset, 841 .set_scale = mcp3910_set_scale, 842 .get_raw = mcp3910_get_raw, 843 }, 844 [MCP3911] = { 845 .channels = mcp3911_channels, 846 .num_channels = ARRAY_SIZE(mcp3911_channels), 847 .config = mcp3911_config, 848 .get_osr = mcp3911_get_osr, 849 .set_osr = mcp3911_set_osr, 850 .enable_offset = mcp3911_enable_offset, 851 .get_offset = mcp3911_get_offset, 852 .set_offset = mcp3911_set_offset, 853 .set_scale = mcp3911_set_scale, 854 .get_raw = mcp3911_get_raw, 855 }, 856 [MCP3912] = { 857 .channels = mcp3912_channels, 858 .num_channels = ARRAY_SIZE(mcp3912_channels), 859 .config = mcp3910_config, 860 .get_osr = mcp3910_get_osr, 861 .set_osr = mcp3910_set_osr, 862 .enable_offset = mcp3910_enable_offset, 863 .get_offset = mcp3910_get_offset, 864 .set_offset = mcp3910_set_offset, 865 .set_scale = mcp3910_set_scale, 866 .get_raw = mcp3910_get_raw, 867 }, 868 [MCP3913] = { 869 .channels = mcp3913_channels, 870 .num_channels = ARRAY_SIZE(mcp3913_channels), 871 .config = mcp3910_config, 872 .get_osr = mcp3910_get_osr, 873 .set_osr = mcp3910_set_osr, 874 .enable_offset = mcp3910_enable_offset, 875 .get_offset = mcp3910_get_offset, 876 .set_offset = mcp3910_set_offset, 877 .set_scale = mcp3910_set_scale, 878 .get_raw = mcp3910_get_raw, 879 }, 880 [MCP3914] = { 881 .channels = mcp3914_channels, 882 .num_channels = ARRAY_SIZE(mcp3914_channels), 883 .config = mcp3910_config, 884 .get_osr = mcp3910_get_osr, 885 .set_osr = mcp3910_set_osr, 886 .enable_offset = mcp3910_enable_offset, 887 .get_offset = mcp3910_get_offset, 888 .set_offset = mcp3910_set_offset, 889 .set_scale = mcp3910_set_scale, 890 .get_raw = mcp3910_get_raw, 891 }, 892 [MCP3918] = { 893 .channels = mcp3918_channels, 894 .num_channels = ARRAY_SIZE(mcp3918_channels), 895 .config = mcp3910_config, 896 .get_osr = mcp3910_get_osr, 897 .set_osr = mcp3910_set_osr, 898 .enable_offset = mcp3910_enable_offset, 899 .get_offset = mcp3910_get_offset, 900 .set_offset = mcp3910_set_offset, 901 .set_scale = mcp3910_set_scale, 902 .get_raw = mcp3910_get_raw, 903 }, 904 [MCP3919] = { 905 .channels = mcp3919_channels, 906 .num_channels = ARRAY_SIZE(mcp3919_channels), 907 .config = mcp3910_config, 908 .get_osr = mcp3910_get_osr, 909 .set_osr = mcp3910_set_osr, 910 .enable_offset = mcp3910_enable_offset, 911 .get_offset = mcp3910_get_offset, 912 .set_offset = mcp3910_set_offset, 913 .set_scale = mcp3910_set_scale, 914 .get_raw = mcp3910_get_raw, 915 }, 916 }; 917 static const struct of_device_id mcp3911_dt_ids[] = { 918 { .compatible = "microchip,mcp3910", .data = &mcp3911_chip_info[MCP3910] }, 919 { .compatible = "microchip,mcp3911", .data = &mcp3911_chip_info[MCP3911] }, 920 { .compatible = "microchip,mcp3912", .data = &mcp3911_chip_info[MCP3912] }, 921 { .compatible = "microchip,mcp3913", .data = &mcp3911_chip_info[MCP3913] }, 922 { .compatible = "microchip,mcp3914", .data = &mcp3911_chip_info[MCP3914] }, 923 { .compatible = "microchip,mcp3918", .data = &mcp3911_chip_info[MCP3918] }, 924 { .compatible = "microchip,mcp3919", .data = &mcp3911_chip_info[MCP3919] }, 925 { } 926 }; 927 MODULE_DEVICE_TABLE(of, mcp3911_dt_ids); 928 929 static const struct spi_device_id mcp3911_id[] = { 930 { .name = "mcp3910", .driver_data = (kernel_ulong_t)&mcp3911_chip_info[MCP3910] }, 931 { .name = "mcp3911", .driver_data = (kernel_ulong_t)&mcp3911_chip_info[MCP3911] }, 932 { .name = "mcp3912", .driver_data = (kernel_ulong_t)&mcp3911_chip_info[MCP3912] }, 933 { .name = "mcp3913", .driver_data = (kernel_ulong_t)&mcp3911_chip_info[MCP3913] }, 934 { .name = "mcp3914", .driver_data = (kernel_ulong_t)&mcp3911_chip_info[MCP3914] }, 935 { .name = "mcp3918", .driver_data = (kernel_ulong_t)&mcp3911_chip_info[MCP3918] }, 936 { .name = "mcp3919", .driver_data = (kernel_ulong_t)&mcp3911_chip_info[MCP3919] }, 937 { } 938 }; 939 MODULE_DEVICE_TABLE(spi, mcp3911_id); 940 941 static struct spi_driver mcp3911_driver = { 942 .driver = { 943 .name = "mcp3911", 944 .of_match_table = mcp3911_dt_ids, 945 }, 946 .probe = mcp3911_probe, 947 .id_table = mcp3911_id, 948 }; 949 module_spi_driver(mcp3911_driver); 950 951 MODULE_AUTHOR("Marcus Folkesson <marcus.folkesson@gmail.com>"); 952 MODULE_AUTHOR("Kent Gustavsson <kent@minoris.se>"); 953 MODULE_DESCRIPTION("Microchip Technology MCP3911"); 954 MODULE_LICENSE("GPL v2"); 955