xref: /linux/drivers/iio/adc/mcp3422.c (revision c0c914eca7f251c70facc37dfebeaf176601918d)
1 /*
2  * mcp3422.c - driver for the Microchip mcp3422/3/4/6/7/8 chip family
3  *
4  * Copyright (C) 2013, Angelo Compagnucci
5  * Author: Angelo Compagnucci <angelo.compagnucci@gmail.com>
6  *
7  * Datasheet: http://ww1.microchip.com/downloads/en/devicedoc/22088b.pdf
8  *            http://ww1.microchip.com/downloads/en/DeviceDoc/22226a.pdf
9  *
10  * This driver exports the value of analog input voltage to sysfs, the
11  * voltage unit is nV.
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2 of the License, or
16  * (at your option) any later version.
17  */
18 
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/module.h>
22 #include <linux/delay.h>
23 #include <linux/sysfs.h>
24 #include <linux/of.h>
25 
26 #include <linux/iio/iio.h>
27 #include <linux/iio/sysfs.h>
28 
29 /* Masks */
30 #define MCP3422_CHANNEL_MASK	0x60
31 #define MCP3422_PGA_MASK	0x03
32 #define MCP3422_SRATE_MASK	0x0C
33 #define MCP3422_SRATE_240	0x0
34 #define MCP3422_SRATE_60	0x1
35 #define MCP3422_SRATE_15	0x2
36 #define MCP3422_SRATE_3	0x3
37 #define MCP3422_PGA_1	0
38 #define MCP3422_PGA_2	1
39 #define MCP3422_PGA_4	2
40 #define MCP3422_PGA_8	3
41 #define MCP3422_CONT_SAMPLING	0x10
42 
43 #define MCP3422_CHANNEL(config)	(((config) & MCP3422_CHANNEL_MASK) >> 5)
44 #define MCP3422_PGA(config)	((config) & MCP3422_PGA_MASK)
45 #define MCP3422_SAMPLE_RATE(config)	(((config) & MCP3422_SRATE_MASK) >> 2)
46 
47 #define MCP3422_CHANNEL_VALUE(value) (((value) << 5) & MCP3422_CHANNEL_MASK)
48 #define MCP3422_PGA_VALUE(value) ((value) & MCP3422_PGA_MASK)
49 #define MCP3422_SAMPLE_RATE_VALUE(value) ((value << 2) & MCP3422_SRATE_MASK)
50 
51 #define MCP3422_CHAN(_index) \
52 	{ \
53 		.type = IIO_VOLTAGE, \
54 		.indexed = 1, \
55 		.channel = _index, \
56 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
57 				| BIT(IIO_CHAN_INFO_SCALE), \
58 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
59 	}
60 
61 static const int mcp3422_scales[4][4] = {
62 	{ 1000000, 500000, 250000, 125000 },
63 	{ 250000 , 125000, 62500 , 31250  },
64 	{ 62500  , 31250 , 15625 , 7812   },
65 	{ 15625  , 7812  , 3906  , 1953   } };
66 
67 /* Constant msleep times for data acquisitions */
68 static const int mcp3422_read_times[4] = {
69 	[MCP3422_SRATE_240] = 1000 / 240,
70 	[MCP3422_SRATE_60] = 1000 / 60,
71 	[MCP3422_SRATE_15] = 1000 / 15,
72 	[MCP3422_SRATE_3] = 1000 / 3 };
73 
74 /* sample rates to integer conversion table */
75 static const int mcp3422_sample_rates[4] = {
76 	[MCP3422_SRATE_240] = 240,
77 	[MCP3422_SRATE_60] = 60,
78 	[MCP3422_SRATE_15] = 15,
79 	[MCP3422_SRATE_3] = 3 };
80 
81 /* sample rates to sign extension table */
82 static const int mcp3422_sign_extend[4] = {
83 	[MCP3422_SRATE_240] = 11,
84 	[MCP3422_SRATE_60] = 13,
85 	[MCP3422_SRATE_15] = 15,
86 	[MCP3422_SRATE_3] = 17 };
87 
88 /* Client data (each client gets its own) */
89 struct mcp3422 {
90 	struct i2c_client *i2c;
91 	u8 id;
92 	u8 config;
93 	u8 pga[4];
94 	struct mutex lock;
95 };
96 
97 static int mcp3422_update_config(struct mcp3422 *adc, u8 newconfig)
98 {
99 	int ret;
100 
101 	mutex_lock(&adc->lock);
102 
103 	ret = i2c_master_send(adc->i2c, &newconfig, 1);
104 	if (ret > 0) {
105 		adc->config = newconfig;
106 		ret = 0;
107 	}
108 
109 	mutex_unlock(&adc->lock);
110 
111 	return ret;
112 }
113 
114 static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config)
115 {
116 	int ret = 0;
117 	u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
118 	u8 buf[4] = {0, 0, 0, 0};
119 	u32 temp;
120 
121 	if (sample_rate == MCP3422_SRATE_3) {
122 		ret = i2c_master_recv(adc->i2c, buf, 4);
123 		temp = buf[0] << 16 | buf[1] << 8 | buf[2];
124 		*config = buf[3];
125 	} else {
126 		ret = i2c_master_recv(adc->i2c, buf, 3);
127 		temp = buf[0] << 8 | buf[1];
128 		*config = buf[2];
129 	}
130 
131 	*value = sign_extend32(temp, mcp3422_sign_extend[sample_rate]);
132 
133 	return ret;
134 }
135 
136 static int mcp3422_read_channel(struct mcp3422 *adc,
137 				struct iio_chan_spec const *channel, int *value)
138 {
139 	int ret;
140 	u8 config;
141 	u8 req_channel = channel->channel;
142 
143 	if (req_channel != MCP3422_CHANNEL(adc->config)) {
144 		config = adc->config;
145 		config &= ~MCP3422_CHANNEL_MASK;
146 		config |= MCP3422_CHANNEL_VALUE(req_channel);
147 		config &= ~MCP3422_PGA_MASK;
148 		config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
149 		ret = mcp3422_update_config(adc, config);
150 		if (ret < 0)
151 			return ret;
152 		msleep(mcp3422_read_times[MCP3422_SAMPLE_RATE(adc->config)]);
153 	}
154 
155 	return mcp3422_read(adc, value, &config);
156 }
157 
158 static int mcp3422_read_raw(struct iio_dev *iio,
159 			struct iio_chan_spec const *channel, int *val1,
160 			int *val2, long mask)
161 {
162 	struct mcp3422 *adc = iio_priv(iio);
163 	int err;
164 
165 	u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
166 	u8 pga		 = MCP3422_PGA(adc->config);
167 
168 	switch (mask) {
169 	case IIO_CHAN_INFO_RAW:
170 		err = mcp3422_read_channel(adc, channel, val1);
171 		if (err < 0)
172 			return -EINVAL;
173 		return IIO_VAL_INT;
174 
175 	case IIO_CHAN_INFO_SCALE:
176 
177 		*val1 = 0;
178 		*val2 = mcp3422_scales[sample_rate][pga];
179 		return IIO_VAL_INT_PLUS_NANO;
180 
181 	case IIO_CHAN_INFO_SAMP_FREQ:
182 		*val1 = mcp3422_sample_rates[MCP3422_SAMPLE_RATE(adc->config)];
183 		return IIO_VAL_INT;
184 
185 	default:
186 		break;
187 	}
188 
189 	return -EINVAL;
190 }
191 
192 static int mcp3422_write_raw(struct iio_dev *iio,
193 			struct iio_chan_spec const *channel, int val1,
194 			int val2, long mask)
195 {
196 	struct mcp3422 *adc = iio_priv(iio);
197 	u8 temp;
198 	u8 config = adc->config;
199 	u8 req_channel = channel->channel;
200 	u8 sample_rate = MCP3422_SAMPLE_RATE(config);
201 	u8 i;
202 
203 	switch (mask) {
204 	case IIO_CHAN_INFO_SCALE:
205 		if (val1 != 0)
206 			return -EINVAL;
207 
208 		for (i = 0; i < ARRAY_SIZE(mcp3422_scales[0]); i++) {
209 			if (val2 == mcp3422_scales[sample_rate][i]) {
210 				adc->pga[req_channel] = i;
211 
212 				config &= ~MCP3422_CHANNEL_MASK;
213 				config |= MCP3422_CHANNEL_VALUE(req_channel);
214 				config &= ~MCP3422_PGA_MASK;
215 				config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
216 
217 				return mcp3422_update_config(adc, config);
218 			}
219 		}
220 		return -EINVAL;
221 
222 	case IIO_CHAN_INFO_SAMP_FREQ:
223 		switch (val1) {
224 		case 240:
225 			temp = MCP3422_SRATE_240;
226 			break;
227 		case 60:
228 			temp = MCP3422_SRATE_60;
229 			break;
230 		case 15:
231 			temp = MCP3422_SRATE_15;
232 			break;
233 		case 3:
234 			if (adc->id > 4)
235 				return -EINVAL;
236 			temp = MCP3422_SRATE_3;
237 			break;
238 		default:
239 			return -EINVAL;
240 		}
241 
242 		config &= ~MCP3422_CHANNEL_MASK;
243 		config |= MCP3422_CHANNEL_VALUE(req_channel);
244 		config &= ~MCP3422_SRATE_MASK;
245 		config |= MCP3422_SAMPLE_RATE_VALUE(temp);
246 
247 		return mcp3422_update_config(adc, config);
248 
249 	default:
250 		break;
251 	}
252 
253 	return -EINVAL;
254 }
255 
256 static int mcp3422_write_raw_get_fmt(struct iio_dev *indio_dev,
257 		struct iio_chan_spec const *chan, long mask)
258 {
259 	switch (mask) {
260 	case IIO_CHAN_INFO_SCALE:
261 		return IIO_VAL_INT_PLUS_NANO;
262 	case IIO_CHAN_INFO_SAMP_FREQ:
263 		return IIO_VAL_INT_PLUS_MICRO;
264 	default:
265 		return -EINVAL;
266 	}
267 }
268 
269 static ssize_t mcp3422_show_samp_freqs(struct device *dev,
270 		struct device_attribute *attr, char *buf)
271 {
272 	struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
273 
274 	if (adc->id > 4)
275 		return sprintf(buf, "240 60 15\n");
276 
277 	return sprintf(buf, "240 60 15 3\n");
278 }
279 
280 static ssize_t mcp3422_show_scales(struct device *dev,
281 		struct device_attribute *attr, char *buf)
282 {
283 	struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
284 	u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
285 
286 	return sprintf(buf, "0.%09u 0.%09u 0.%09u 0.%09u\n",
287 		mcp3422_scales[sample_rate][0],
288 		mcp3422_scales[sample_rate][1],
289 		mcp3422_scales[sample_rate][2],
290 		mcp3422_scales[sample_rate][3]);
291 }
292 
293 static IIO_DEVICE_ATTR(sampling_frequency_available, S_IRUGO,
294 		mcp3422_show_samp_freqs, NULL, 0);
295 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
296 		mcp3422_show_scales, NULL, 0);
297 
298 static struct attribute *mcp3422_attributes[] = {
299 	&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
300 	&iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
301 	NULL,
302 };
303 
304 static const struct attribute_group mcp3422_attribute_group = {
305 	.attrs = mcp3422_attributes,
306 };
307 
308 static const struct iio_chan_spec mcp3421_channels[] = {
309 	MCP3422_CHAN(0),
310 };
311 
312 static const struct iio_chan_spec mcp3422_channels[] = {
313 	MCP3422_CHAN(0),
314 	MCP3422_CHAN(1),
315 };
316 
317 static const struct iio_chan_spec mcp3424_channels[] = {
318 	MCP3422_CHAN(0),
319 	MCP3422_CHAN(1),
320 	MCP3422_CHAN(2),
321 	MCP3422_CHAN(3),
322 };
323 
324 static const struct iio_info mcp3422_info = {
325 	.read_raw = mcp3422_read_raw,
326 	.write_raw = mcp3422_write_raw,
327 	.write_raw_get_fmt = mcp3422_write_raw_get_fmt,
328 	.attrs = &mcp3422_attribute_group,
329 	.driver_module = THIS_MODULE,
330 };
331 
332 static int mcp3422_probe(struct i2c_client *client,
333 			 const struct i2c_device_id *id)
334 {
335 	struct iio_dev *indio_dev;
336 	struct mcp3422 *adc;
337 	int err;
338 	u8 config;
339 
340 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
341 		return -ENODEV;
342 
343 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*adc));
344 	if (!indio_dev)
345 		return -ENOMEM;
346 
347 	adc = iio_priv(indio_dev);
348 	adc->i2c = client;
349 	adc->id = (u8)(id->driver_data);
350 
351 	mutex_init(&adc->lock);
352 
353 	indio_dev->dev.parent = &client->dev;
354 	indio_dev->name = dev_name(&client->dev);
355 	indio_dev->modes = INDIO_DIRECT_MODE;
356 	indio_dev->info = &mcp3422_info;
357 
358 	switch (adc->id) {
359 	case 1:
360 		indio_dev->channels = mcp3421_channels;
361 		indio_dev->num_channels = ARRAY_SIZE(mcp3421_channels);
362 		break;
363 	case 2:
364 	case 3:
365 	case 6:
366 	case 7:
367 		indio_dev->channels = mcp3422_channels;
368 		indio_dev->num_channels = ARRAY_SIZE(mcp3422_channels);
369 		break;
370 	case 4:
371 	case 8:
372 		indio_dev->channels = mcp3424_channels;
373 		indio_dev->num_channels = ARRAY_SIZE(mcp3424_channels);
374 		break;
375 	}
376 
377 	/* meaningful default configuration */
378 	config = (MCP3422_CONT_SAMPLING
379 		| MCP3422_CHANNEL_VALUE(1)
380 		| MCP3422_PGA_VALUE(MCP3422_PGA_1)
381 		| MCP3422_SAMPLE_RATE_VALUE(MCP3422_SRATE_240));
382 	mcp3422_update_config(adc, config);
383 
384 	err = devm_iio_device_register(&client->dev, indio_dev);
385 	if (err < 0)
386 		return err;
387 
388 	i2c_set_clientdata(client, indio_dev);
389 
390 	return 0;
391 }
392 
393 static const struct i2c_device_id mcp3422_id[] = {
394 	{ "mcp3421", 1 },
395 	{ "mcp3422", 2 },
396 	{ "mcp3423", 3 },
397 	{ "mcp3424", 4 },
398 	{ "mcp3426", 6 },
399 	{ "mcp3427", 7 },
400 	{ "mcp3428", 8 },
401 	{ }
402 };
403 MODULE_DEVICE_TABLE(i2c, mcp3422_id);
404 
405 #ifdef CONFIG_OF
406 static const struct of_device_id mcp3422_of_match[] = {
407 	{ .compatible = "mcp3422" },
408 	{ }
409 };
410 MODULE_DEVICE_TABLE(of, mcp3422_of_match);
411 #endif
412 
413 static struct i2c_driver mcp3422_driver = {
414 	.driver = {
415 		.name = "mcp3422",
416 		.of_match_table = of_match_ptr(mcp3422_of_match),
417 	},
418 	.probe = mcp3422_probe,
419 	.id_table = mcp3422_id,
420 };
421 module_i2c_driver(mcp3422_driver);
422 
423 MODULE_AUTHOR("Angelo Compagnucci <angelo.compagnucci@gmail.com>");
424 MODULE_DESCRIPTION("Microchip mcp3422/3/4/6/7/8 driver");
425 MODULE_LICENSE("GPL v2");
426