1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * mcp3422.c - driver for the Microchip mcp3421/2/3/4/5/6/7/8 chip family 4 * 5 * Copyright (C) 2013, Angelo Compagnucci 6 * Author: Angelo Compagnucci <angelo.compagnucci@gmail.com> 7 * 8 * Datasheet: http://ww1.microchip.com/downloads/en/devicedoc/22088b.pdf 9 * https://ww1.microchip.com/downloads/en/DeviceDoc/22226a.pdf 10 * https://ww1.microchip.com/downloads/en/DeviceDoc/22072b.pdf 11 * 12 * This driver exports the value of analog input voltage to sysfs, the 13 * voltage unit is nV. 14 */ 15 16 #include <linux/bitfield.h> 17 #include <linux/bits.h> 18 #include <linux/err.h> 19 #include <linux/i2c.h> 20 #include <linux/module.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/delay.h> 23 #include <linux/sysfs.h> 24 #include <linux/unaligned.h> 25 26 #include <linux/iio/iio.h> 27 #include <linux/iio/sysfs.h> 28 29 #define MCP3422_CHANNEL_MASK GENMASK(6, 5) 30 #define MCP3422_SRATE_MASK GENMASK(3, 2) 31 #define MCP3422_PGA_MASK GENMASK(1, 0) 32 33 #define MCP3422_SRATE_240 0x0 34 #define MCP3422_SRATE_60 0x1 35 #define MCP3422_SRATE_15 0x2 36 #define MCP3422_SRATE_3 0x3 37 #define MCP3422_PGA_1 0 38 #define MCP3422_PGA_2 1 39 #define MCP3422_PGA_4 2 40 #define MCP3422_PGA_8 3 41 #define MCP3422_CONT_SAMPLING BIT(4) 42 43 #define MCP3422_CHAN(_index) \ 44 { \ 45 .type = IIO_VOLTAGE, \ 46 .indexed = 1, \ 47 .channel = _index, \ 48 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 49 | BIT(IIO_CHAN_INFO_SCALE), \ 50 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 51 } 52 53 static const int mcp3422_scales[4][4] = { 54 { 1000000, 500000, 250000, 125000 }, 55 { 250000, 125000, 62500, 31250 }, 56 { 62500, 31250, 15625, 7812 }, 57 { 15625, 7812, 3906, 1953 } }; 58 59 /* Constant msleep times for data acquisitions */ 60 static const int mcp3422_read_times[4] = { 61 [MCP3422_SRATE_240] = 1000 / 240, 62 [MCP3422_SRATE_60] = 1000 / 60, 63 [MCP3422_SRATE_15] = 1000 / 15, 64 [MCP3422_SRATE_3] = 1000 / 3 }; 65 66 /* sample rates to integer conversion table */ 67 static const int mcp3422_sample_rates[4] = { 68 [MCP3422_SRATE_240] = 240, 69 [MCP3422_SRATE_60] = 60, 70 [MCP3422_SRATE_15] = 15, 71 [MCP3422_SRATE_3] = 3 }; 72 73 /* sample rates to sign extension table */ 74 static const int mcp3422_sign_extend[4] = { 75 [MCP3422_SRATE_240] = 11, 76 [MCP3422_SRATE_60] = 13, 77 [MCP3422_SRATE_15] = 15, 78 [MCP3422_SRATE_3] = 17 }; 79 80 /* Client data (each client gets its own) */ 81 struct mcp3422 { 82 struct i2c_client *i2c; 83 u8 id; 84 u8 config; 85 u8 pga[4]; 86 struct mutex lock; 87 }; 88 89 static int mcp3422_update_config(struct mcp3422 *adc, u8 newconfig) 90 { 91 int ret; 92 93 ret = i2c_master_send(adc->i2c, &newconfig, 1); 94 if (ret > 0) { 95 adc->config = newconfig; 96 ret = 0; 97 } 98 99 return ret; 100 } 101 102 static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config) 103 { 104 int ret = 0; 105 u8 sample_rate = FIELD_GET(MCP3422_SRATE_MASK, adc->config); 106 u8 buf[4] = {0, 0, 0, 0}; 107 u32 temp; 108 109 if (sample_rate == MCP3422_SRATE_3) { 110 ret = i2c_master_recv(adc->i2c, buf, 4); 111 temp = get_unaligned_be24(&buf[0]); 112 *config = buf[3]; 113 } else { 114 ret = i2c_master_recv(adc->i2c, buf, 3); 115 temp = get_unaligned_be16(&buf[0]); 116 *config = buf[2]; 117 } 118 119 *value = sign_extend32(temp, mcp3422_sign_extend[sample_rate]); 120 121 return ret; 122 } 123 124 static int mcp3422_read_channel(struct mcp3422 *adc, 125 struct iio_chan_spec const *channel, int *value) 126 { 127 int ret; 128 u8 config; 129 u8 req_channel = channel->channel; 130 131 mutex_lock(&adc->lock); 132 133 if (req_channel != FIELD_GET(MCP3422_CHANNEL_MASK, adc->config)) { 134 config = adc->config; 135 136 FIELD_MODIFY(MCP3422_CHANNEL_MASK, &config, req_channel); 137 FIELD_MODIFY(MCP3422_PGA_MASK, &config, adc->pga[req_channel]); 138 139 ret = mcp3422_update_config(adc, config); 140 if (ret < 0) { 141 mutex_unlock(&adc->lock); 142 return ret; 143 } 144 msleep(mcp3422_read_times[FIELD_GET(MCP3422_SRATE_MASK, adc->config)]); 145 } 146 147 ret = mcp3422_read(adc, value, &config); 148 149 mutex_unlock(&adc->lock); 150 151 return ret; 152 } 153 154 static int mcp3422_read_raw(struct iio_dev *iio, 155 struct iio_chan_spec const *channel, int *val1, 156 int *val2, long mask) 157 { 158 struct mcp3422 *adc = iio_priv(iio); 159 int err; 160 u8 sample_rate = FIELD_GET(MCP3422_SRATE_MASK, adc->config); 161 u8 pga = FIELD_GET(MCP3422_PGA_MASK, adc->config); 162 163 switch (mask) { 164 case IIO_CHAN_INFO_RAW: 165 err = mcp3422_read_channel(adc, channel, val1); 166 if (err < 0) 167 return -EINVAL; 168 return IIO_VAL_INT; 169 170 case IIO_CHAN_INFO_SCALE: 171 172 *val1 = 0; 173 *val2 = mcp3422_scales[sample_rate][pga]; 174 return IIO_VAL_INT_PLUS_NANO; 175 176 case IIO_CHAN_INFO_SAMP_FREQ: 177 *val1 = mcp3422_sample_rates[FIELD_GET(MCP3422_SRATE_MASK, adc->config)]; 178 return IIO_VAL_INT; 179 180 default: 181 break; 182 } 183 184 return -EINVAL; 185 } 186 187 static int mcp3422_write_raw(struct iio_dev *iio, 188 struct iio_chan_spec const *channel, int val1, 189 int val2, long mask) 190 { 191 struct mcp3422 *adc = iio_priv(iio); 192 u8 temp; 193 u8 config = adc->config; 194 u8 req_channel = channel->channel; 195 u8 sample_rate = FIELD_GET(MCP3422_SRATE_MASK, config); 196 u8 i; 197 198 switch (mask) { 199 case IIO_CHAN_INFO_SCALE: 200 if (val1 != 0) 201 return -EINVAL; 202 203 for (i = 0; i < ARRAY_SIZE(mcp3422_scales[0]); i++) { 204 if (val2 == mcp3422_scales[sample_rate][i]) { 205 adc->pga[req_channel] = i; 206 207 FIELD_MODIFY(MCP3422_CHANNEL_MASK, &config, req_channel); 208 FIELD_MODIFY(MCP3422_PGA_MASK, &config, adc->pga[req_channel]); 209 210 return mcp3422_update_config(adc, config); 211 } 212 } 213 return -EINVAL; 214 215 case IIO_CHAN_INFO_SAMP_FREQ: 216 switch (val1) { 217 case 240: 218 temp = MCP3422_SRATE_240; 219 break; 220 case 60: 221 temp = MCP3422_SRATE_60; 222 break; 223 case 15: 224 temp = MCP3422_SRATE_15; 225 break; 226 case 3: 227 if (adc->id > 4) 228 return -EINVAL; 229 temp = MCP3422_SRATE_3; 230 break; 231 default: 232 return -EINVAL; 233 } 234 235 FIELD_MODIFY(MCP3422_CHANNEL_MASK, &config, req_channel); 236 FIELD_MODIFY(MCP3422_SRATE_MASK, &config, temp); 237 238 return mcp3422_update_config(adc, config); 239 240 default: 241 break; 242 } 243 244 return -EINVAL; 245 } 246 247 static int mcp3422_write_raw_get_fmt(struct iio_dev *indio_dev, 248 struct iio_chan_spec const *chan, long mask) 249 { 250 switch (mask) { 251 case IIO_CHAN_INFO_SCALE: 252 return IIO_VAL_INT_PLUS_NANO; 253 case IIO_CHAN_INFO_SAMP_FREQ: 254 return IIO_VAL_INT_PLUS_MICRO; 255 default: 256 return -EINVAL; 257 } 258 } 259 260 static ssize_t mcp3422_show_samp_freqs(struct device *dev, 261 struct device_attribute *attr, char *buf) 262 { 263 struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev)); 264 265 if (adc->id > 4) 266 return sprintf(buf, "240 60 15\n"); 267 268 return sprintf(buf, "240 60 15 3\n"); 269 } 270 271 static ssize_t mcp3422_show_scales(struct device *dev, 272 struct device_attribute *attr, char *buf) 273 { 274 struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev)); 275 u8 sample_rate = FIELD_GET(MCP3422_SRATE_MASK, adc->config); 276 277 return sprintf(buf, "0.%09u 0.%09u 0.%09u 0.%09u\n", 278 mcp3422_scales[sample_rate][0], 279 mcp3422_scales[sample_rate][1], 280 mcp3422_scales[sample_rate][2], 281 mcp3422_scales[sample_rate][3]); 282 } 283 284 static IIO_DEVICE_ATTR(sampling_frequency_available, S_IRUGO, 285 mcp3422_show_samp_freqs, NULL, 0); 286 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, 287 mcp3422_show_scales, NULL, 0); 288 289 static struct attribute *mcp3422_attributes[] = { 290 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 291 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, 292 NULL, 293 }; 294 295 static const struct attribute_group mcp3422_attribute_group = { 296 .attrs = mcp3422_attributes, 297 }; 298 299 static const struct iio_chan_spec mcp3421_channels[] = { 300 MCP3422_CHAN(0), 301 }; 302 303 static const struct iio_chan_spec mcp3422_channels[] = { 304 MCP3422_CHAN(0), 305 MCP3422_CHAN(1), 306 }; 307 308 static const struct iio_chan_spec mcp3424_channels[] = { 309 MCP3422_CHAN(0), 310 MCP3422_CHAN(1), 311 MCP3422_CHAN(2), 312 MCP3422_CHAN(3), 313 }; 314 315 static const struct iio_info mcp3422_info = { 316 .read_raw = mcp3422_read_raw, 317 .write_raw = mcp3422_write_raw, 318 .write_raw_get_fmt = mcp3422_write_raw_get_fmt, 319 .attrs = &mcp3422_attribute_group, 320 }; 321 322 static int mcp3422_probe(struct i2c_client *client) 323 { 324 const struct i2c_device_id *id = i2c_client_get_device_id(client); 325 struct iio_dev *indio_dev; 326 struct mcp3422 *adc; 327 int err; 328 u8 config; 329 330 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 331 return -EOPNOTSUPP; 332 333 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*adc)); 334 if (!indio_dev) 335 return -ENOMEM; 336 337 adc = iio_priv(indio_dev); 338 adc->i2c = client; 339 adc->id = (u8)(id->driver_data); 340 341 mutex_init(&adc->lock); 342 343 indio_dev->name = dev_name(&client->dev); 344 indio_dev->modes = INDIO_DIRECT_MODE; 345 indio_dev->info = &mcp3422_info; 346 347 switch (adc->id) { 348 case 1: 349 case 5: 350 indio_dev->channels = mcp3421_channels; 351 indio_dev->num_channels = ARRAY_SIZE(mcp3421_channels); 352 break; 353 case 2: 354 case 3: 355 case 6: 356 case 7: 357 indio_dev->channels = mcp3422_channels; 358 indio_dev->num_channels = ARRAY_SIZE(mcp3422_channels); 359 break; 360 case 4: 361 case 8: 362 indio_dev->channels = mcp3424_channels; 363 indio_dev->num_channels = ARRAY_SIZE(mcp3424_channels); 364 break; 365 } 366 367 /* meaningful default configuration */ 368 config = MCP3422_CONT_SAMPLING | 369 FIELD_PREP(MCP3422_CHANNEL_MASK, 0) | 370 FIELD_PREP(MCP3422_PGA_MASK, MCP3422_PGA_1) | 371 FIELD_PREP(MCP3422_SRATE_MASK, MCP3422_SRATE_240); 372 err = mcp3422_update_config(adc, config); 373 if (err < 0) 374 return err; 375 376 err = devm_iio_device_register(&client->dev, indio_dev); 377 if (err < 0) 378 return err; 379 380 i2c_set_clientdata(client, indio_dev); 381 382 return 0; 383 } 384 385 static const struct i2c_device_id mcp3422_id[] = { 386 { .name = "mcp3421", .driver_data = 1 }, 387 { .name = "mcp3422", .driver_data = 2 }, 388 { .name = "mcp3423", .driver_data = 3 }, 389 { .name = "mcp3424", .driver_data = 4 }, 390 { .name = "mcp3425", .driver_data = 5 }, 391 { .name = "mcp3426", .driver_data = 6 }, 392 { .name = "mcp3427", .driver_data = 7 }, 393 { .name = "mcp3428", .driver_data = 8 }, 394 { } 395 }; 396 MODULE_DEVICE_TABLE(i2c, mcp3422_id); 397 398 static const struct of_device_id mcp3422_of_match[] = { 399 { .compatible = "mcp3422" }, 400 { } 401 }; 402 MODULE_DEVICE_TABLE(of, mcp3422_of_match); 403 404 static struct i2c_driver mcp3422_driver = { 405 .driver = { 406 .name = "mcp3422", 407 .of_match_table = mcp3422_of_match, 408 }, 409 .probe = mcp3422_probe, 410 .id_table = mcp3422_id, 411 }; 412 module_i2c_driver(mcp3422_driver); 413 414 MODULE_AUTHOR("Angelo Compagnucci <angelo.compagnucci@gmail.com>"); 415 MODULE_DESCRIPTION("Microchip mcp3421/2/3/4/5/6/7/8 driver"); 416 MODULE_LICENSE("GPL v2"); 417