1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 /* 3 * Analog Devices MAX14001/MAX14002 ADC driver 4 * 5 * Copyright (C) 2023-2025 Analog Devices Inc. 6 * Copyright (C) 2023 Kim Seer Paller <kimseer.paller@analog.com> 7 * Copyright (c) 2025 Marilene Andrade Garcia <marilene.agarcia@gmail.com> 8 * 9 * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/MAX14001-MAX14002.pdf 10 */ 11 12 #include <linux/array_size.h> 13 #include <linux/bitfield.h> 14 #include <linux/bitrev.h> 15 #include <linux/bits.h> 16 #include <linux/cleanup.h> 17 #include <linux/device.h> 18 #include <linux/module.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/spi/spi.h> 22 #include <linux/types.h> 23 #include <linux/units.h> 24 #include <asm/byteorder.h> 25 26 #include <linux/iio/iio.h> 27 #include <linux/iio/types.h> 28 29 /* MAX14001 Registers Address */ 30 #define MAX14001_REG_ADC 0x00 31 #define MAX14001_REG_FADC 0x01 32 #define MAX14001_REG_FLAGS 0x02 33 #define MAX14001_REG_FLTEN 0x03 34 #define MAX14001_REG_THL 0x04 35 #define MAX14001_REG_THU 0x05 36 #define MAX14001_REG_INRR 0x06 37 #define MAX14001_REG_INRT 0x07 38 #define MAX14001_REG_INRP 0x08 39 #define MAX14001_REG_CFG 0x09 40 #define MAX14001_REG_ENBL 0x0A 41 #define MAX14001_REG_ACT 0x0B 42 #define MAX14001_REG_WEN 0x0C 43 44 #define MAX14001_REG_VERIFICATION(x) ((x) + 0x10) 45 46 #define MAX14001_REG_CFG_BIT_EXRF BIT(5) 47 48 #define MAX14001_REG_WEN_VALUE_WRITE 0x294 49 50 #define MAX14001_MASK_ADDR GENMASK(15, 11) 51 #define MAX14001_MASK_WR BIT(10) 52 #define MAX14001_MASK_DATA GENMASK(9, 0) 53 54 struct max14001_state { 55 const struct max14001_chip_info *chip_info; 56 struct spi_device *spi; 57 struct regmap *regmap; 58 int vref_mV; 59 bool spi_hw_has_lsb_first; 60 61 /* 62 * The following buffers will be bit-reversed during device 63 * communication, because the device transmits and receives data 64 * LSB-first. 65 * DMA (thus cache coherency maintenance) requires the transfer 66 * buffers to live in their own cache lines. 67 */ 68 union { 69 __be16 be; 70 __le16 le; 71 } spi_tx_buffer __aligned(IIO_DMA_MINALIGN); 72 73 union { 74 __be16 be; 75 __le16 le; 76 } spi_rx_buffer; 77 }; 78 79 struct max14001_chip_info { 80 const char *name; 81 }; 82 83 static int max14001_read(void *context, unsigned int reg, unsigned int *val) 84 { 85 struct max14001_state *st = context; 86 struct spi_transfer xfers[] = { 87 { 88 .tx_buf = &st->spi_tx_buffer, 89 .len = sizeof(st->spi_tx_buffer), 90 .cs_change = 1, 91 }, { 92 .rx_buf = &st->spi_rx_buffer, 93 .len = sizeof(st->spi_rx_buffer), 94 }, 95 }; 96 int ret; 97 unsigned int addr, data; 98 99 /* 100 * Prepare SPI transmit buffer 16 bit-value and reverse bit order 101 * to align with the LSB-first input on SDI port in order to meet 102 * the device communication requirements. If the controller supports 103 * SPI_LSB_FIRST, this step will be handled by the SPI controller. 104 */ 105 addr = FIELD_PREP(MAX14001_MASK_ADDR, reg); 106 107 if (st->spi_hw_has_lsb_first) 108 st->spi_tx_buffer.le = cpu_to_le16(addr); 109 else 110 st->spi_tx_buffer.be = cpu_to_be16(bitrev16(addr)); 111 112 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); 113 if (ret) 114 return ret; 115 116 /* 117 * Convert received 16-bit value to cpu-endian format and reverse 118 * bit order. If the controller supports SPI_LSB_FIRST, this step 119 * will be handled by the SPI controller. 120 */ 121 if (st->spi_hw_has_lsb_first) 122 data = le16_to_cpu(st->spi_rx_buffer.le); 123 else 124 data = bitrev16(be16_to_cpu(st->spi_rx_buffer.be)); 125 126 *val = FIELD_GET(MAX14001_MASK_DATA, data); 127 128 return 0; 129 } 130 131 static int max14001_write(struct max14001_state *st, unsigned int reg, unsigned int val) 132 { 133 unsigned int addr; 134 135 /* 136 * Prepare SPI transmit buffer 16 bit-value and reverse bit order 137 * to align with the LSB-first input on SDI port in order to meet 138 * the device communication requirements. If the controller supports 139 * SPI_LSB_FIRST, this step will be handled by the SPI controller. 140 */ 141 addr = FIELD_PREP(MAX14001_MASK_ADDR, reg) | 142 FIELD_PREP(MAX14001_MASK_WR, 1) | 143 FIELD_PREP(MAX14001_MASK_DATA, val); 144 145 if (st->spi_hw_has_lsb_first) 146 st->spi_tx_buffer.le = cpu_to_le16(addr); 147 else 148 st->spi_tx_buffer.be = cpu_to_be16(bitrev16(addr)); 149 150 return spi_write(st->spi, &st->spi_tx_buffer, sizeof(st->spi_tx_buffer)); 151 } 152 153 static int max14001_write_single_reg(void *context, unsigned int reg, unsigned int val) 154 { 155 struct max14001_state *st = context; 156 int ret; 157 158 /* Enable writing to the SPI register. */ 159 ret = max14001_write(st, MAX14001_REG_WEN, MAX14001_REG_WEN_VALUE_WRITE); 160 if (ret) 161 return ret; 162 163 /* Writing data into SPI register. */ 164 ret = max14001_write(st, reg, val); 165 if (ret) 166 return ret; 167 168 /* Disable writing to the SPI register. */ 169 return max14001_write(st, MAX14001_REG_WEN, 0); 170 } 171 172 static int max14001_write_verification_reg(struct max14001_state *st, unsigned int reg) 173 { 174 unsigned int val; 175 int ret; 176 177 ret = regmap_read(st->regmap, reg, &val); 178 if (ret) 179 return ret; 180 181 return max14001_write(st, MAX14001_REG_VERIFICATION(reg), val); 182 } 183 184 static int max14001_disable_mv_fault(struct max14001_state *st) 185 { 186 unsigned int reg; 187 int ret; 188 189 /* Enable writing to the SPI registers. */ 190 ret = max14001_write(st, MAX14001_REG_WEN, MAX14001_REG_WEN_VALUE_WRITE); 191 if (ret) 192 return ret; 193 194 /* 195 * Reads all registers and writes the values to their appropriate 196 * verification registers to clear the Memory Validation fault. 197 */ 198 for (reg = MAX14001_REG_FLTEN; reg <= MAX14001_REG_ENBL; reg++) { 199 ret = max14001_write_verification_reg(st, reg); 200 if (ret) 201 return ret; 202 } 203 204 /* Disable writing to the SPI registers. */ 205 return max14001_write(st, MAX14001_REG_WEN, 0); 206 } 207 208 static int max14001_debugfs_reg_access(struct iio_dev *indio_dev, 209 unsigned int reg, unsigned int writeval, 210 unsigned int *readval) 211 { 212 struct max14001_state *st = iio_priv(indio_dev); 213 214 if (readval) 215 return regmap_read(st->regmap, reg, readval); 216 217 return regmap_write(st->regmap, reg, writeval); 218 } 219 220 static int max14001_read_raw(struct iio_dev *indio_dev, 221 struct iio_chan_spec const *chan, 222 int *val, int *val2, long mask) 223 { 224 struct max14001_state *st = iio_priv(indio_dev); 225 int ret; 226 227 switch (mask) { 228 case IIO_CHAN_INFO_RAW: 229 ret = regmap_read(st->regmap, MAX14001_REG_ADC, val); 230 if (ret) 231 return ret; 232 233 return IIO_VAL_INT; 234 case IIO_CHAN_INFO_SCALE: 235 *val = st->vref_mV; 236 *val2 = 10; 237 238 return IIO_VAL_FRACTIONAL_LOG2; 239 default: 240 return -EINVAL; 241 } 242 } 243 244 static const struct regmap_range max14001_regmap_rd_range[] = { 245 regmap_reg_range(MAX14001_REG_ADC, MAX14001_REG_ENBL), 246 regmap_reg_range(MAX14001_REG_WEN, MAX14001_REG_WEN), 247 regmap_reg_range(MAX14001_REG_VERIFICATION(MAX14001_REG_FLTEN), 248 MAX14001_REG_VERIFICATION(MAX14001_REG_ENBL)), 249 }; 250 251 static const struct regmap_access_table max14001_regmap_rd_table = { 252 .yes_ranges = max14001_regmap_rd_range, 253 .n_yes_ranges = ARRAY_SIZE(max14001_regmap_rd_range), 254 }; 255 256 static const struct regmap_range max14001_regmap_wr_range[] = { 257 regmap_reg_range(MAX14001_REG_FLTEN, MAX14001_REG_WEN), 258 regmap_reg_range(MAX14001_REG_VERIFICATION(MAX14001_REG_FLTEN), 259 MAX14001_REG_VERIFICATION(MAX14001_REG_ENBL)), 260 }; 261 262 static const struct regmap_access_table max14001_regmap_wr_table = { 263 .yes_ranges = max14001_regmap_wr_range, 264 .n_yes_ranges = ARRAY_SIZE(max14001_regmap_wr_range), 265 }; 266 267 static const struct regmap_config max14001_regmap_config = { 268 .reg_read = max14001_read, 269 .reg_write = max14001_write_single_reg, 270 .max_register = MAX14001_REG_VERIFICATION(MAX14001_REG_ENBL), 271 .rd_table = &max14001_regmap_rd_table, 272 .wr_table = &max14001_regmap_wr_table, 273 }; 274 275 static const struct iio_info max14001_info = { 276 .read_raw = max14001_read_raw, 277 .debugfs_reg_access = max14001_debugfs_reg_access, 278 }; 279 280 static const struct iio_chan_spec max14001_channel[] = { 281 { 282 .type = IIO_VOLTAGE, 283 .indexed = 1, 284 .channel = 0, 285 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 286 BIT(IIO_CHAN_INFO_SCALE), 287 }, 288 }; 289 290 static int max14001_probe(struct spi_device *spi) 291 { 292 struct device *dev = &spi->dev; 293 struct iio_dev *indio_dev; 294 struct max14001_state *st; 295 int ret; 296 bool use_ext_vrefin = false; 297 298 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 299 if (!indio_dev) 300 return -ENOMEM; 301 302 st = iio_priv(indio_dev); 303 st->spi = spi; 304 st->spi_hw_has_lsb_first = spi->mode & SPI_LSB_FIRST; 305 st->chip_info = spi_get_device_match_data(spi); 306 if (!st->chip_info) 307 return -EINVAL; 308 309 indio_dev->name = st->chip_info->name; 310 indio_dev->info = &max14001_info; 311 indio_dev->channels = max14001_channel; 312 indio_dev->num_channels = ARRAY_SIZE(max14001_channel); 313 indio_dev->modes = INDIO_DIRECT_MODE; 314 315 st->regmap = devm_regmap_init(dev, NULL, st, &max14001_regmap_config); 316 if (IS_ERR(st->regmap)) 317 return dev_err_probe(dev, PTR_ERR(st->regmap), "Failed to initialize regmap\n"); 318 319 ret = devm_regulator_get_enable(dev, "vdd"); 320 if (ret) 321 return dev_err_probe(dev, ret, "Failed to enable Vdd supply\n"); 322 323 ret = devm_regulator_get_enable(dev, "vddl"); 324 if (ret) 325 return dev_err_probe(dev, ret, "Failed to enable Vddl supply\n"); 326 327 ret = devm_regulator_get_enable_read_voltage(dev, "refin"); 328 if (ret < 0 && ret != -ENODEV) 329 return dev_err_probe(dev, ret, "Failed to get REFIN voltage\n"); 330 331 if (ret == -ENODEV) 332 ret = 1250000; 333 else 334 use_ext_vrefin = true; 335 st->vref_mV = ret / (MICRO / MILLI); 336 337 if (use_ext_vrefin) { 338 /* 339 * Configure the MAX14001/MAX14002 to use an external voltage 340 * reference source by setting the bit 5 of the configuration register. 341 */ 342 ret = regmap_set_bits(st->regmap, MAX14001_REG_CFG, 343 MAX14001_REG_CFG_BIT_EXRF); 344 if (ret) 345 return dev_err_probe(dev, ret, 346 "Failed to set External REFIN in Configuration Register\n"); 347 } 348 349 ret = max14001_disable_mv_fault(st); 350 if (ret) 351 return dev_err_probe(dev, ret, "Failed to disable MV Fault\n"); 352 353 return devm_iio_device_register(dev, indio_dev); 354 } 355 356 static struct max14001_chip_info max14001_chip_info = { 357 .name = "max14001", 358 }; 359 360 static struct max14001_chip_info max14002_chip_info = { 361 .name = "max14002", 362 }; 363 364 static const struct spi_device_id max14001_id_table[] = { 365 { .name = "max14001", .driver_data = (kernel_ulong_t)&max14001_chip_info }, 366 { .name = "max14002", .driver_data = (kernel_ulong_t)&max14002_chip_info }, 367 { } 368 }; 369 370 static const struct of_device_id max14001_of_match[] = { 371 { .compatible = "adi,max14001", .data = &max14001_chip_info }, 372 { .compatible = "adi,max14002", .data = &max14002_chip_info }, 373 { } 374 }; 375 MODULE_DEVICE_TABLE(of, max14001_of_match); 376 377 static struct spi_driver max14001_driver = { 378 .driver = { 379 .name = "max14001", 380 .of_match_table = max14001_of_match, 381 }, 382 .probe = max14001_probe, 383 .id_table = max14001_id_table, 384 }; 385 module_spi_driver(max14001_driver); 386 387 MODULE_AUTHOR("Kim Seer Paller <kimseer.paller@analog.com>"); 388 MODULE_AUTHOR("Marilene Andrade Garcia <marilene.agarcia@gmail.com>"); 389 MODULE_DESCRIPTION("Analog Devices MAX14001/MAX14002 ADCs driver"); 390 MODULE_LICENSE("GPL"); 391