1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MAX11410 SPI ADC driver 4 * 5 * Copyright 2022 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/err.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/regmap.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/spi/spi.h> 17 18 #include <asm/unaligned.h> 19 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/sysfs.h> 22 #include <linux/iio/trigger.h> 23 #include <linux/iio/trigger_consumer.h> 24 #include <linux/iio/triggered_buffer.h> 25 26 #define MAX11410_REG_CONV_START 0x01 27 #define MAX11410_CONV_TYPE_SINGLE 0x00 28 #define MAX11410_CONV_TYPE_CONTINUOUS 0x01 29 #define MAX11410_REG_CAL_START 0x03 30 #define MAX11410_CAL_START_SELF 0x00 31 #define MAX11410_CAL_START_PGA 0x01 32 #define MAX11410_REG_GPIO_CTRL(ch) ((ch) ? 0x05 : 0x04) 33 #define MAX11410_GPIO_INTRB 0xC1 34 #define MAX11410_REG_FILTER 0x08 35 #define MAX11410_FILTER_RATE_MASK GENMASK(3, 0) 36 #define MAX11410_FILTER_RATE_MAX 0x0F 37 #define MAX11410_FILTER_LINEF_MASK GENMASK(5, 4) 38 #define MAX11410_FILTER_50HZ BIT(5) 39 #define MAX11410_FILTER_60HZ BIT(4) 40 #define MAX11410_REG_CTRL 0x09 41 #define MAX11410_CTRL_REFSEL_MASK GENMASK(2, 0) 42 #define MAX11410_CTRL_VREFN_BUF_BIT BIT(3) 43 #define MAX11410_CTRL_VREFP_BUF_BIT BIT(4) 44 #define MAX11410_CTRL_FORMAT_BIT BIT(5) 45 #define MAX11410_CTRL_UNIPOLAR_BIT BIT(6) 46 #define MAX11410_REG_MUX_CTRL0 0x0B 47 #define MAX11410_REG_PGA 0x0E 48 #define MAX11410_PGA_GAIN_MASK GENMASK(2, 0) 49 #define MAX11410_PGA_SIG_PATH_MASK GENMASK(5, 4) 50 #define MAX11410_PGA_SIG_PATH_BUFFERED 0x00 51 #define MAX11410_PGA_SIG_PATH_BYPASS 0x01 52 #define MAX11410_PGA_SIG_PATH_PGA 0x02 53 #define MAX11410_REG_DATA0 0x30 54 #define MAX11410_REG_STATUS 0x38 55 #define MAX11410_STATUS_CONV_READY_BIT BIT(0) 56 #define MAX11410_STATUS_CAL_READY_BIT BIT(2) 57 58 #define MAX11410_REFSEL_AVDD_AGND 0x03 59 #define MAX11410_REFSEL_MAX 0x06 60 #define MAX11410_SIG_PATH_MAX 0x02 61 #define MAX11410_CHANNEL_INDEX_MAX 0x0A 62 #define MAX11410_AINP_AVDD 0x0A 63 #define MAX11410_AINN_GND 0x0A 64 65 #define MAX11410_CONVERSION_TIMEOUT_MS 2000 66 #define MAX11410_CALIB_TIMEOUT_MS 2000 67 68 #define MAX11410_SCALE_AVAIL_SIZE 8 69 70 enum max11410_filter { 71 MAX11410_FILTER_FIR5060, 72 MAX11410_FILTER_FIR50, 73 MAX11410_FILTER_FIR60, 74 MAX11410_FILTER_SINC4, 75 }; 76 77 static const u8 max11410_sampling_len[] = { 78 [MAX11410_FILTER_FIR5060] = 5, 79 [MAX11410_FILTER_FIR50] = 6, 80 [MAX11410_FILTER_FIR60] = 6, 81 [MAX11410_FILTER_SINC4] = 10, 82 }; 83 84 static const int max11410_sampling_rates[4][10][2] = { 85 [MAX11410_FILTER_FIR5060] = { 86 { 1, 100000 }, 87 { 2, 100000 }, 88 { 4, 200000 }, 89 { 8, 400000 }, 90 { 16, 800000 } 91 }, 92 [MAX11410_FILTER_FIR50] = { 93 { 1, 300000 }, 94 { 2, 700000 }, 95 { 5, 300000 }, 96 { 10, 700000 }, 97 { 21, 300000 }, 98 { 40 } 99 }, 100 [MAX11410_FILTER_FIR60] = { 101 { 1, 300000 }, 102 { 2, 700000 }, 103 { 5, 300000 }, 104 { 10, 700000 }, 105 { 21, 300000 }, 106 { 40 } 107 }, 108 [MAX11410_FILTER_SINC4] = { 109 { 4 }, 110 { 10 }, 111 { 20 }, 112 { 40 }, 113 { 60 }, 114 { 120 }, 115 { 240 }, 116 { 480 }, 117 { 960 }, 118 { 1920 } 119 } 120 }; 121 122 struct max11410_channel_config { 123 u32 settling_time_us; 124 u32 *scale_avail; 125 u8 refsel; 126 u8 sig_path; 127 u8 gain; 128 bool bipolar; 129 bool buffered_vrefp; 130 bool buffered_vrefn; 131 }; 132 133 struct max11410_state { 134 struct spi_device *spi_dev; 135 struct iio_trigger *trig; 136 struct completion completion; 137 struct mutex lock; /* Prevent changing channel config during sampling */ 138 struct regmap *regmap; 139 struct regulator *avdd; 140 struct regulator *vrefp[3]; 141 struct regulator *vrefn[3]; 142 struct max11410_channel_config *channels; 143 int irq; 144 struct { 145 u32 data __aligned(IIO_DMA_MINALIGN); 146 s64 ts __aligned(8); 147 } scan; 148 }; 149 150 static const struct iio_chan_spec chanspec_template = { 151 .type = IIO_VOLTAGE, 152 .indexed = 1, 153 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 154 BIT(IIO_CHAN_INFO_SCALE) | 155 BIT(IIO_CHAN_INFO_OFFSET), 156 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), 157 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), 158 .scan_type = { 159 .sign = 's', 160 .realbits = 24, 161 .storagebits = 32, 162 .endianness = IIO_LE, 163 }, 164 }; 165 166 static unsigned int max11410_reg_size(unsigned int reg) 167 { 168 /* Registers from 0x00 to 0x10 are 1 byte, the rest are 3 bytes long. */ 169 return reg <= 0x10 ? 1 : 3; 170 } 171 172 static int max11410_write_reg(struct max11410_state *st, unsigned int reg, 173 unsigned int val) 174 { 175 /* This driver only needs to write 8-bit registers */ 176 if (max11410_reg_size(reg) != 1) 177 return -EINVAL; 178 179 return regmap_write(st->regmap, reg, val); 180 } 181 182 static int max11410_read_reg(struct max11410_state *st, unsigned int reg, 183 int *val) 184 { 185 int ret; 186 187 if (max11410_reg_size(reg) == 3) { 188 ret = regmap_bulk_read(st->regmap, reg, &st->scan.data, 3); 189 if (ret) 190 return ret; 191 192 *val = get_unaligned_be24(&st->scan.data); 193 return 0; 194 } 195 196 return regmap_read(st->regmap, reg, val); 197 } 198 199 static struct regulator *max11410_get_vrefp(struct max11410_state *st, 200 u8 refsel) 201 { 202 refsel = refsel % 4; 203 if (refsel == 3) 204 return st->avdd; 205 206 return st->vrefp[refsel]; 207 } 208 209 static struct regulator *max11410_get_vrefn(struct max11410_state *st, 210 u8 refsel) 211 { 212 if (refsel > 2) 213 return NULL; 214 215 return st->vrefn[refsel]; 216 } 217 218 static const struct regmap_config regmap_config = { 219 .reg_bits = 8, 220 .val_bits = 8, 221 .max_register = 0x39, 222 }; 223 224 static ssize_t max11410_notch_en_show(struct device *dev, 225 struct device_attribute *devattr, 226 char *buf) 227 { 228 struct iio_dev *indio_dev = dev_get_drvdata(dev); 229 struct max11410_state *state = iio_priv(indio_dev); 230 struct iio_dev_attr *iio_attr = to_iio_dev_attr(devattr); 231 unsigned int val; 232 int ret; 233 234 ret = max11410_read_reg(state, MAX11410_REG_FILTER, &val); 235 if (ret) 236 return ret; 237 238 switch (iio_attr->address) { 239 case 0: 240 val = !FIELD_GET(MAX11410_FILTER_50HZ, val); 241 break; 242 case 1: 243 val = !FIELD_GET(MAX11410_FILTER_60HZ, val); 244 break; 245 case 2: 246 val = FIELD_GET(MAX11410_FILTER_LINEF_MASK, val) == 3; 247 break; 248 default: 249 return -EINVAL; 250 } 251 252 return sysfs_emit(buf, "%d\n", val); 253 } 254 255 static ssize_t max11410_notch_en_store(struct device *dev, 256 struct device_attribute *devattr, 257 const char *buf, size_t count) 258 { 259 struct iio_dev_attr *iio_attr = to_iio_dev_attr(devattr); 260 struct iio_dev *indio_dev = dev_get_drvdata(dev); 261 struct max11410_state *state = iio_priv(indio_dev); 262 unsigned int filter_bits; 263 bool enable; 264 int ret; 265 266 ret = kstrtobool(buf, &enable); 267 if (ret) 268 return ret; 269 270 switch (iio_attr->address) { 271 case 0: 272 filter_bits = MAX11410_FILTER_50HZ; 273 break; 274 case 1: 275 filter_bits = MAX11410_FILTER_60HZ; 276 break; 277 case 2: 278 default: 279 filter_bits = MAX11410_FILTER_50HZ | MAX11410_FILTER_60HZ; 280 enable = !enable; 281 break; 282 } 283 284 if (enable) 285 ret = regmap_clear_bits(state->regmap, MAX11410_REG_FILTER, 286 filter_bits); 287 else 288 ret = regmap_set_bits(state->regmap, MAX11410_REG_FILTER, 289 filter_bits); 290 291 if (ret) 292 return ret; 293 294 return count; 295 } 296 297 static ssize_t in_voltage_filter2_notch_center_show(struct device *dev, 298 struct device_attribute *devattr, 299 char *buf) 300 { 301 struct iio_dev *indio_dev = dev_get_drvdata(dev); 302 struct max11410_state *state = iio_priv(indio_dev); 303 int ret, reg, rate, filter; 304 305 ret = regmap_read(state->regmap, MAX11410_REG_FILTER, ®); 306 if (ret) 307 return ret; 308 309 rate = FIELD_GET(MAX11410_FILTER_RATE_MASK, reg); 310 rate = clamp_val(rate, 0, 311 max11410_sampling_len[MAX11410_FILTER_SINC4] - 1); 312 filter = max11410_sampling_rates[MAX11410_FILTER_SINC4][rate][0]; 313 314 return sysfs_emit(buf, "%d\n", filter); 315 } 316 317 static IIO_CONST_ATTR(in_voltage_filter0_notch_center, "50"); 318 static IIO_CONST_ATTR(in_voltage_filter1_notch_center, "60"); 319 static IIO_DEVICE_ATTR_RO(in_voltage_filter2_notch_center, 2); 320 321 static IIO_DEVICE_ATTR(in_voltage_filter0_notch_en, 0644, 322 max11410_notch_en_show, max11410_notch_en_store, 0); 323 static IIO_DEVICE_ATTR(in_voltage_filter1_notch_en, 0644, 324 max11410_notch_en_show, max11410_notch_en_store, 1); 325 static IIO_DEVICE_ATTR(in_voltage_filter2_notch_en, 0644, 326 max11410_notch_en_show, max11410_notch_en_store, 2); 327 328 static struct attribute *max11410_attributes[] = { 329 &iio_const_attr_in_voltage_filter0_notch_center.dev_attr.attr, 330 &iio_const_attr_in_voltage_filter1_notch_center.dev_attr.attr, 331 &iio_dev_attr_in_voltage_filter2_notch_center.dev_attr.attr, 332 &iio_dev_attr_in_voltage_filter0_notch_en.dev_attr.attr, 333 &iio_dev_attr_in_voltage_filter1_notch_en.dev_attr.attr, 334 &iio_dev_attr_in_voltage_filter2_notch_en.dev_attr.attr, 335 NULL 336 }; 337 338 static const struct attribute_group max11410_attribute_group = { 339 .attrs = max11410_attributes, 340 }; 341 342 static int max11410_set_input_mux(struct max11410_state *st, u8 ainp, u8 ainn) 343 { 344 if (ainp > MAX11410_CHANNEL_INDEX_MAX || 345 ainn > MAX11410_CHANNEL_INDEX_MAX) 346 return -EINVAL; 347 348 return max11410_write_reg(st, MAX11410_REG_MUX_CTRL0, 349 (ainp << 4) | ainn); 350 } 351 352 static int max11410_configure_channel(struct max11410_state *st, 353 struct iio_chan_spec const *chan) 354 { 355 struct max11410_channel_config cfg = st->channels[chan->address]; 356 unsigned int regval; 357 int ret; 358 359 if (chan->differential) 360 ret = max11410_set_input_mux(st, chan->channel, chan->channel2); 361 else 362 ret = max11410_set_input_mux(st, chan->channel, 363 MAX11410_AINN_GND); 364 365 if (ret) 366 return ret; 367 368 regval = FIELD_PREP(MAX11410_CTRL_VREFP_BUF_BIT, cfg.buffered_vrefp) | 369 FIELD_PREP(MAX11410_CTRL_VREFN_BUF_BIT, cfg.buffered_vrefn) | 370 FIELD_PREP(MAX11410_CTRL_REFSEL_MASK, cfg.refsel) | 371 FIELD_PREP(MAX11410_CTRL_UNIPOLAR_BIT, cfg.bipolar ? 0 : 1); 372 ret = regmap_update_bits(st->regmap, MAX11410_REG_CTRL, 373 MAX11410_CTRL_REFSEL_MASK | 374 MAX11410_CTRL_VREFP_BUF_BIT | 375 MAX11410_CTRL_VREFN_BUF_BIT | 376 MAX11410_CTRL_UNIPOLAR_BIT, regval); 377 if (ret) 378 return ret; 379 380 regval = FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK, cfg.sig_path) | 381 FIELD_PREP(MAX11410_PGA_GAIN_MASK, cfg.gain); 382 ret = regmap_write(st->regmap, MAX11410_REG_PGA, regval); 383 if (ret) 384 return ret; 385 386 if (cfg.settling_time_us) 387 fsleep(cfg.settling_time_us); 388 389 return 0; 390 } 391 392 static int max11410_sample(struct max11410_state *st, int *sample_raw, 393 struct iio_chan_spec const *chan) 394 { 395 int val, ret; 396 397 ret = max11410_configure_channel(st, chan); 398 if (ret) 399 return ret; 400 401 if (st->irq > 0) 402 reinit_completion(&st->completion); 403 404 /* Start Conversion */ 405 ret = max11410_write_reg(st, MAX11410_REG_CONV_START, 406 MAX11410_CONV_TYPE_SINGLE); 407 if (ret) 408 return ret; 409 410 if (st->irq > 0) { 411 /* Wait for an interrupt. */ 412 ret = wait_for_completion_timeout(&st->completion, 413 msecs_to_jiffies(MAX11410_CONVERSION_TIMEOUT_MS)); 414 if (!ret) 415 return -ETIMEDOUT; 416 } else { 417 /* Wait for status register Conversion Ready flag */ 418 ret = read_poll_timeout(max11410_read_reg, ret, 419 ret || (val & MAX11410_STATUS_CONV_READY_BIT), 420 5000, MAX11410_CONVERSION_TIMEOUT_MS * 1000, 421 true, st, MAX11410_REG_STATUS, &val); 422 if (ret) 423 return ret; 424 } 425 426 /* Read ADC Data */ 427 return max11410_read_reg(st, MAX11410_REG_DATA0, sample_raw); 428 } 429 430 static int max11410_get_scale(struct max11410_state *state, 431 struct max11410_channel_config cfg) 432 { 433 struct regulator *vrefp, *vrefn; 434 int scale; 435 436 vrefp = max11410_get_vrefp(state, cfg.refsel); 437 438 scale = regulator_get_voltage(vrefp) / 1000; 439 vrefn = max11410_get_vrefn(state, cfg.refsel); 440 if (vrefn) 441 scale -= regulator_get_voltage(vrefn) / 1000; 442 443 if (cfg.bipolar) 444 scale *= 2; 445 446 return scale >> cfg.gain; 447 } 448 449 static int max11410_read_raw(struct iio_dev *indio_dev, 450 struct iio_chan_spec const *chan, 451 int *val, int *val2, long info) 452 { 453 struct max11410_state *state = iio_priv(indio_dev); 454 struct max11410_channel_config cfg = state->channels[chan->address]; 455 int ret, reg_val, filter, rate; 456 457 switch (info) { 458 case IIO_CHAN_INFO_SCALE: 459 *val = max11410_get_scale(state, cfg); 460 *val2 = chan->scan_type.realbits; 461 return IIO_VAL_FRACTIONAL_LOG2; 462 case IIO_CHAN_INFO_OFFSET: 463 if (cfg.bipolar) 464 *val = -BIT(chan->scan_type.realbits - 1); 465 else 466 *val = 0; 467 468 return IIO_VAL_INT; 469 case IIO_CHAN_INFO_RAW: 470 ret = iio_device_claim_direct_mode(indio_dev); 471 if (ret) 472 return ret; 473 474 mutex_lock(&state->lock); 475 476 ret = max11410_sample(state, ®_val, chan); 477 478 mutex_unlock(&state->lock); 479 480 iio_device_release_direct_mode(indio_dev); 481 482 if (ret) 483 return ret; 484 485 *val = reg_val; 486 487 return IIO_VAL_INT; 488 case IIO_CHAN_INFO_SAMP_FREQ: 489 ret = regmap_read(state->regmap, MAX11410_REG_FILTER, ®_val); 490 if (ret) 491 return ret; 492 493 filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val); 494 rate = reg_val & MAX11410_FILTER_RATE_MASK; 495 if (rate >= max11410_sampling_len[filter]) 496 rate = max11410_sampling_len[filter] - 1; 497 498 *val = max11410_sampling_rates[filter][rate][0]; 499 *val2 = max11410_sampling_rates[filter][rate][1]; 500 501 return IIO_VAL_INT_PLUS_MICRO; 502 } 503 return -EINVAL; 504 } 505 506 static int max11410_write_raw(struct iio_dev *indio_dev, 507 struct iio_chan_spec const *chan, 508 int val, int val2, long mask) 509 { 510 struct max11410_state *st = iio_priv(indio_dev); 511 int i, ret, reg_val, filter, gain; 512 u32 *scale_avail; 513 514 switch (mask) { 515 case IIO_CHAN_INFO_SCALE: 516 scale_avail = st->channels[chan->address].scale_avail; 517 if (!scale_avail) 518 return -EOPNOTSUPP; 519 520 /* Accept values in range 0.000001 <= scale < 1.000000 */ 521 if (val != 0 || val2 == 0) 522 return -EINVAL; 523 524 ret = iio_device_claim_direct_mode(indio_dev); 525 if (ret) 526 return ret; 527 528 /* Convert from INT_PLUS_MICRO to FRACTIONAL_LOG2 */ 529 val2 = val2 * DIV_ROUND_CLOSEST(BIT(24), 1000000); 530 val2 = DIV_ROUND_CLOSEST(scale_avail[0], val2); 531 gain = order_base_2(val2); 532 533 st->channels[chan->address].gain = clamp_val(gain, 0, 7); 534 535 iio_device_release_direct_mode(indio_dev); 536 537 return 0; 538 case IIO_CHAN_INFO_SAMP_FREQ: 539 ret = iio_device_claim_direct_mode(indio_dev); 540 if (ret) 541 return ret; 542 543 mutex_lock(&st->lock); 544 545 ret = regmap_read(st->regmap, MAX11410_REG_FILTER, ®_val); 546 if (ret) 547 goto out; 548 549 filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val); 550 551 for (i = 0; i < max11410_sampling_len[filter]; ++i) { 552 if (val == max11410_sampling_rates[filter][i][0] && 553 val2 == max11410_sampling_rates[filter][i][1]) 554 break; 555 } 556 if (i == max11410_sampling_len[filter]) { 557 ret = -EINVAL; 558 goto out; 559 } 560 561 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER, 562 MAX11410_FILTER_RATE_MASK, i); 563 564 out: 565 mutex_unlock(&st->lock); 566 iio_device_release_direct_mode(indio_dev); 567 568 return ret; 569 default: 570 return -EINVAL; 571 } 572 } 573 574 static int max11410_read_avail(struct iio_dev *indio_dev, 575 struct iio_chan_spec const *chan, 576 const int **vals, int *type, int *length, 577 long info) 578 { 579 struct max11410_state *st = iio_priv(indio_dev); 580 struct max11410_channel_config cfg; 581 int ret, reg_val, filter; 582 583 switch (info) { 584 case IIO_CHAN_INFO_SAMP_FREQ: 585 ret = regmap_read(st->regmap, MAX11410_REG_FILTER, ®_val); 586 if (ret) 587 return ret; 588 589 filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val); 590 591 *vals = (const int *)max11410_sampling_rates[filter]; 592 *length = max11410_sampling_len[filter] * 2; 593 *type = IIO_VAL_INT_PLUS_MICRO; 594 595 return IIO_AVAIL_LIST; 596 case IIO_CHAN_INFO_SCALE: 597 cfg = st->channels[chan->address]; 598 599 if (!cfg.scale_avail) 600 return -EINVAL; 601 602 *vals = cfg.scale_avail; 603 *length = MAX11410_SCALE_AVAIL_SIZE * 2; 604 *type = IIO_VAL_FRACTIONAL_LOG2; 605 606 return IIO_AVAIL_LIST; 607 } 608 return -EINVAL; 609 } 610 611 static const struct iio_info max11410_info = { 612 .read_raw = max11410_read_raw, 613 .write_raw = max11410_write_raw, 614 .read_avail = max11410_read_avail, 615 .attrs = &max11410_attribute_group, 616 }; 617 618 static irqreturn_t max11410_trigger_handler(int irq, void *p) 619 { 620 struct iio_poll_func *pf = p; 621 struct iio_dev *indio_dev = pf->indio_dev; 622 struct max11410_state *st = iio_priv(indio_dev); 623 int ret; 624 625 ret = max11410_read_reg(st, MAX11410_REG_DATA0, &st->scan.data); 626 if (ret) { 627 dev_err(&indio_dev->dev, "cannot read data\n"); 628 goto out; 629 } 630 631 iio_push_to_buffers_with_timestamp(indio_dev, &st->scan, 632 iio_get_time_ns(indio_dev)); 633 634 out: 635 iio_trigger_notify_done(indio_dev->trig); 636 637 return IRQ_HANDLED; 638 } 639 640 static int max11410_buffer_postenable(struct iio_dev *indio_dev) 641 { 642 struct max11410_state *st = iio_priv(indio_dev); 643 int scan_ch, ret; 644 645 scan_ch = ffs(*indio_dev->active_scan_mask) - 1; 646 647 ret = max11410_configure_channel(st, &indio_dev->channels[scan_ch]); 648 if (ret) 649 return ret; 650 651 /* Start continuous conversion. */ 652 return max11410_write_reg(st, MAX11410_REG_CONV_START, 653 MAX11410_CONV_TYPE_CONTINUOUS); 654 } 655 656 static int max11410_buffer_predisable(struct iio_dev *indio_dev) 657 { 658 struct max11410_state *st = iio_priv(indio_dev); 659 660 /* Stop continuous conversion. */ 661 return max11410_write_reg(st, MAX11410_REG_CONV_START, 662 MAX11410_CONV_TYPE_SINGLE); 663 } 664 665 static const struct iio_buffer_setup_ops max11410_buffer_ops = { 666 .postenable = &max11410_buffer_postenable, 667 .predisable = &max11410_buffer_predisable, 668 .validate_scan_mask = &iio_validate_scan_mask_onehot, 669 }; 670 671 static const struct iio_trigger_ops max11410_trigger_ops = { 672 .validate_device = iio_trigger_validate_own_device, 673 }; 674 675 static irqreturn_t max11410_interrupt(int irq, void *dev_id) 676 { 677 struct iio_dev *indio_dev = dev_id; 678 struct max11410_state *st = iio_priv(indio_dev); 679 680 if (iio_buffer_enabled(indio_dev)) 681 iio_trigger_poll_chained(st->trig); 682 else 683 complete(&st->completion); 684 685 return IRQ_HANDLED; 686 }; 687 688 static int max11410_parse_channels(struct max11410_state *st, 689 struct iio_dev *indio_dev) 690 { 691 struct iio_chan_spec chanspec = chanspec_template; 692 struct device *dev = &st->spi_dev->dev; 693 struct max11410_channel_config *cfg; 694 struct iio_chan_spec *channels; 695 struct fwnode_handle *child; 696 u32 reference, sig_path; 697 const char *node_name; 698 u32 inputs[2], scale; 699 unsigned int num_ch; 700 int chan_idx = 0; 701 int ret, i; 702 703 num_ch = device_get_child_node_count(dev); 704 if (num_ch == 0) 705 return dev_err_probe(&indio_dev->dev, -ENODEV, 706 "FW has no channels defined\n"); 707 708 /* Reserve space for soft timestamp channel */ 709 num_ch++; 710 channels = devm_kcalloc(dev, num_ch, sizeof(*channels), GFP_KERNEL); 711 if (!channels) 712 return -ENOMEM; 713 714 st->channels = devm_kcalloc(dev, num_ch, sizeof(*st->channels), 715 GFP_KERNEL); 716 if (!st->channels) 717 return -ENOMEM; 718 719 device_for_each_child_node(dev, child) { 720 node_name = fwnode_get_name(child); 721 if (fwnode_property_present(child, "diff-channels")) { 722 ret = fwnode_property_read_u32_array(child, 723 "diff-channels", 724 inputs, 725 ARRAY_SIZE(inputs)); 726 727 chanspec.differential = 1; 728 } else { 729 ret = fwnode_property_read_u32(child, "reg", &inputs[0]); 730 731 inputs[1] = 0; 732 chanspec.differential = 0; 733 } 734 if (ret) { 735 fwnode_handle_put(child); 736 return ret; 737 } 738 739 if (inputs[0] > MAX11410_CHANNEL_INDEX_MAX || 740 inputs[1] > MAX11410_CHANNEL_INDEX_MAX) { 741 fwnode_handle_put(child); 742 return dev_err_probe(&indio_dev->dev, -EINVAL, 743 "Invalid channel index for %s, should be less than %d\n", 744 node_name, 745 MAX11410_CHANNEL_INDEX_MAX + 1); 746 } 747 748 cfg = &st->channels[chan_idx]; 749 750 reference = MAX11410_REFSEL_AVDD_AGND; 751 fwnode_property_read_u32(child, "adi,reference", &reference); 752 if (reference > MAX11410_REFSEL_MAX) { 753 fwnode_handle_put(child); 754 return dev_err_probe(&indio_dev->dev, -EINVAL, 755 "Invalid adi,reference value for %s, should be less than %d.\n", 756 node_name, MAX11410_REFSEL_MAX + 1); 757 } 758 759 if (!max11410_get_vrefp(st, reference) || 760 (!max11410_get_vrefn(st, reference) && reference <= 2)) { 761 fwnode_handle_put(child); 762 return dev_err_probe(&indio_dev->dev, -EINVAL, 763 "Invalid VREF configuration for %s, either specify corresponding VREF regulators or change adi,reference property.\n", 764 node_name); 765 } 766 767 sig_path = MAX11410_PGA_SIG_PATH_BUFFERED; 768 fwnode_property_read_u32(child, "adi,input-mode", &sig_path); 769 if (sig_path > MAX11410_SIG_PATH_MAX) { 770 fwnode_handle_put(child); 771 return dev_err_probe(&indio_dev->dev, -EINVAL, 772 "Invalid adi,input-mode value for %s, should be less than %d.\n", 773 node_name, MAX11410_SIG_PATH_MAX + 1); 774 } 775 776 fwnode_property_read_u32(child, "settling-time-us", 777 &cfg->settling_time_us); 778 cfg->bipolar = fwnode_property_read_bool(child, "bipolar"); 779 cfg->buffered_vrefp = fwnode_property_read_bool(child, "adi,buffered-vrefp"); 780 cfg->buffered_vrefn = fwnode_property_read_bool(child, "adi,buffered-vrefn"); 781 cfg->refsel = reference; 782 cfg->sig_path = sig_path; 783 cfg->gain = 0; 784 785 /* Enable scale_available property if input mode is PGA */ 786 if (sig_path == MAX11410_PGA_SIG_PATH_PGA) { 787 __set_bit(IIO_CHAN_INFO_SCALE, 788 &chanspec.info_mask_separate_available); 789 cfg->scale_avail = devm_kcalloc(dev, MAX11410_SCALE_AVAIL_SIZE * 2, 790 sizeof(*cfg->scale_avail), 791 GFP_KERNEL); 792 if (!cfg->scale_avail) { 793 fwnode_handle_put(child); 794 return -ENOMEM; 795 } 796 797 scale = max11410_get_scale(st, *cfg); 798 for (i = 0; i < MAX11410_SCALE_AVAIL_SIZE; i++) { 799 cfg->scale_avail[2 * i] = scale >> i; 800 cfg->scale_avail[2 * i + 1] = chanspec.scan_type.realbits; 801 } 802 } else { 803 __clear_bit(IIO_CHAN_INFO_SCALE, 804 &chanspec.info_mask_separate_available); 805 } 806 807 chanspec.address = chan_idx; 808 chanspec.scan_index = chan_idx; 809 chanspec.channel = inputs[0]; 810 chanspec.channel2 = inputs[1]; 811 812 channels[chan_idx] = chanspec; 813 chan_idx++; 814 } 815 816 channels[chan_idx] = (struct iio_chan_spec)IIO_CHAN_SOFT_TIMESTAMP(chan_idx); 817 818 indio_dev->num_channels = chan_idx + 1; 819 indio_dev->channels = channels; 820 821 return 0; 822 } 823 824 static void max11410_disable_reg(void *reg) 825 { 826 regulator_disable(reg); 827 } 828 829 static int max11410_init_vref(struct device *dev, 830 struct regulator **vref, 831 const char *id) 832 { 833 struct regulator *reg; 834 int ret; 835 836 reg = devm_regulator_get_optional(dev, id); 837 if (PTR_ERR(reg) == -ENODEV) { 838 *vref = NULL; 839 return 0; 840 } else if (IS_ERR(reg)) { 841 return PTR_ERR(reg); 842 } 843 ret = regulator_enable(reg); 844 if (ret) 845 return dev_err_probe(dev, ret, 846 "Failed to enable regulator %s\n", id); 847 848 *vref = reg; 849 return devm_add_action_or_reset(dev, max11410_disable_reg, reg); 850 } 851 852 static int max11410_calibrate(struct max11410_state *st, u32 cal_type) 853 { 854 int ret, val; 855 856 ret = max11410_write_reg(st, MAX11410_REG_CAL_START, cal_type); 857 if (ret) 858 return ret; 859 860 /* Wait for status register Calibration Ready flag */ 861 return read_poll_timeout(max11410_read_reg, ret, 862 ret || (val & MAX11410_STATUS_CAL_READY_BIT), 863 50000, MAX11410_CALIB_TIMEOUT_MS * 1000, true, 864 st, MAX11410_REG_STATUS, &val); 865 } 866 867 static int max11410_self_calibrate(struct max11410_state *st) 868 { 869 int ret, i; 870 871 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER, 872 MAX11410_FILTER_RATE_MASK, 873 FIELD_PREP(MAX11410_FILTER_RATE_MASK, 874 MAX11410_FILTER_RATE_MAX)); 875 if (ret) 876 return ret; 877 878 ret = max11410_calibrate(st, MAX11410_CAL_START_SELF); 879 if (ret) 880 return ret; 881 882 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA, 883 MAX11410_PGA_SIG_PATH_MASK, 884 FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK, 885 MAX11410_PGA_SIG_PATH_PGA)); 886 if (ret) 887 return ret; 888 889 /* PGA calibrations */ 890 for (i = 1; i < 8; ++i) { 891 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA, 892 MAX11410_PGA_GAIN_MASK, i); 893 if (ret) 894 return ret; 895 896 ret = max11410_calibrate(st, MAX11410_CAL_START_PGA); 897 if (ret) 898 return ret; 899 } 900 901 /* Cleanup */ 902 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA, 903 MAX11410_PGA_GAIN_MASK, 0); 904 if (ret) 905 return ret; 906 907 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER, 908 MAX11410_FILTER_RATE_MASK, 0); 909 if (ret) 910 return ret; 911 912 return regmap_write_bits(st->regmap, MAX11410_REG_PGA, 913 MAX11410_PGA_SIG_PATH_MASK, 914 FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK, 915 MAX11410_PGA_SIG_PATH_BUFFERED)); 916 } 917 918 static int max11410_probe(struct spi_device *spi) 919 { 920 const char *vrefp_regs[] = { "vref0p", "vref1p", "vref2p" }; 921 const char *vrefn_regs[] = { "vref0n", "vref1n", "vref2n" }; 922 struct device *dev = &spi->dev; 923 struct max11410_state *st; 924 struct iio_dev *indio_dev; 925 int ret, irqs[2]; 926 int i; 927 928 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 929 if (!indio_dev) 930 return -ENOMEM; 931 932 st = iio_priv(indio_dev); 933 st->spi_dev = spi; 934 init_completion(&st->completion); 935 mutex_init(&st->lock); 936 937 indio_dev->name = "max11410"; 938 indio_dev->modes = INDIO_DIRECT_MODE; 939 indio_dev->info = &max11410_info; 940 941 st->regmap = devm_regmap_init_spi(spi, ®map_config); 942 if (IS_ERR(st->regmap)) 943 return dev_err_probe(dev, PTR_ERR(st->regmap), 944 "regmap initialization failed\n"); 945 946 ret = max11410_init_vref(dev, &st->avdd, "avdd"); 947 if (ret) 948 return ret; 949 950 for (i = 0; i < ARRAY_SIZE(vrefp_regs); i++) { 951 ret = max11410_init_vref(dev, &st->vrefp[i], vrefp_regs[i]); 952 if (ret) 953 return ret; 954 955 ret = max11410_init_vref(dev, &st->vrefn[i], vrefn_regs[i]); 956 if (ret) 957 return ret; 958 } 959 960 /* 961 * Regulators must be configured before parsing channels for 962 * validating "adi,reference" property of each channel. 963 */ 964 ret = max11410_parse_channels(st, indio_dev); 965 if (ret) 966 return ret; 967 968 irqs[0] = fwnode_irq_get_byname(dev_fwnode(dev), "gpio0"); 969 irqs[1] = fwnode_irq_get_byname(dev_fwnode(dev), "gpio1"); 970 971 if (irqs[0] > 0) { 972 st->irq = irqs[0]; 973 ret = regmap_write(st->regmap, MAX11410_REG_GPIO_CTRL(0), 974 MAX11410_GPIO_INTRB); 975 } else if (irqs[1] > 0) { 976 st->irq = irqs[1]; 977 ret = regmap_write(st->regmap, MAX11410_REG_GPIO_CTRL(1), 978 MAX11410_GPIO_INTRB); 979 } else if (spi->irq > 0) { 980 return dev_err_probe(dev, -ENODEV, 981 "no interrupt name specified"); 982 } 983 984 if (ret) 985 return ret; 986 987 ret = regmap_set_bits(st->regmap, MAX11410_REG_CTRL, 988 MAX11410_CTRL_FORMAT_BIT); 989 if (ret) 990 return ret; 991 992 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 993 &max11410_trigger_handler, 994 &max11410_buffer_ops); 995 if (ret) 996 return ret; 997 998 if (st->irq > 0) { 999 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 1000 indio_dev->name, 1001 iio_device_id(indio_dev)); 1002 if (!st->trig) 1003 return -ENOMEM; 1004 1005 st->trig->ops = &max11410_trigger_ops; 1006 ret = devm_iio_trigger_register(dev, st->trig); 1007 if (ret) 1008 return ret; 1009 1010 ret = devm_request_threaded_irq(dev, st->irq, NULL, 1011 &max11410_interrupt, 1012 IRQF_ONESHOT, "max11410", 1013 indio_dev); 1014 if (ret) 1015 return ret; 1016 } 1017 1018 ret = max11410_self_calibrate(st); 1019 if (ret) 1020 return dev_err_probe(dev, ret, 1021 "cannot perform device self calibration\n"); 1022 1023 return devm_iio_device_register(dev, indio_dev); 1024 } 1025 1026 static const struct of_device_id max11410_spi_of_id[] = { 1027 { .compatible = "adi,max11410" }, 1028 { } 1029 }; 1030 MODULE_DEVICE_TABLE(of, max11410_spi_of_id); 1031 1032 static const struct spi_device_id max11410_id[] = { 1033 { "max11410" }, 1034 { } 1035 }; 1036 MODULE_DEVICE_TABLE(spi, max11410_id); 1037 1038 static struct spi_driver max11410_driver = { 1039 .driver = { 1040 .name = "max11410", 1041 .of_match_table = max11410_spi_of_id, 1042 }, 1043 .probe = max11410_probe, 1044 .id_table = max11410_id, 1045 }; 1046 module_spi_driver(max11410_driver); 1047 1048 MODULE_AUTHOR("David Jung <David.Jung@analog.com>"); 1049 MODULE_AUTHOR("Ibrahim Tilki <Ibrahim.Tilki@analog.com>"); 1050 MODULE_DESCRIPTION("Analog Devices MAX11410 ADC"); 1051 MODULE_LICENSE("GPL"); 1052