1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * iio/adc/max1027.c 4 * Copyright (C) 2014 Philippe Reynes 5 * 6 * based on linux/drivers/iio/ad7923.c 7 * Copyright 2011 Analog Devices Inc (from AD7923 Driver) 8 * Copyright 2012 CS Systemes d'Information 9 * 10 * max1027.c 11 * 12 * Partial support for max1027 and similar chips. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/spi/spi.h> 18 #include <linux/delay.h> 19 20 #include <linux/iio/iio.h> 21 #include <linux/iio/buffer.h> 22 #include <linux/iio/trigger.h> 23 #include <linux/iio/trigger_consumer.h> 24 #include <linux/iio/triggered_buffer.h> 25 26 #define MAX1027_CONV_REG BIT(7) 27 #define MAX1027_SETUP_REG BIT(6) 28 #define MAX1027_AVG_REG BIT(5) 29 #define MAX1027_RST_REG BIT(4) 30 31 /* conversion register */ 32 #define MAX1027_TEMP BIT(0) 33 #define MAX1027_SCAN_0_N (0x00 << 1) 34 #define MAX1027_SCAN_N_M (0x01 << 1) 35 #define MAX1027_SCAN_N (0x02 << 1) 36 #define MAX1027_NOSCAN (0x03 << 1) 37 #define MAX1027_CHAN(n) ((n) << 3) 38 39 /* setup register */ 40 #define MAX1027_UNIPOLAR 0x02 41 #define MAX1027_BIPOLAR 0x03 42 #define MAX1027_REF_MODE0 (0x00 << 2) 43 #define MAX1027_REF_MODE1 (0x01 << 2) 44 #define MAX1027_REF_MODE2 (0x02 << 2) 45 #define MAX1027_REF_MODE3 (0x03 << 2) 46 #define MAX1027_CKS_MODE0 (0x00 << 4) 47 #define MAX1027_CKS_MODE1 (0x01 << 4) 48 #define MAX1027_CKS_MODE2 (0x02 << 4) 49 #define MAX1027_CKS_MODE3 (0x03 << 4) 50 51 /* averaging register */ 52 #define MAX1027_NSCAN_4 0x00 53 #define MAX1027_NSCAN_8 0x01 54 #define MAX1027_NSCAN_12 0x02 55 #define MAX1027_NSCAN_16 0x03 56 #define MAX1027_NAVG_4 (0x00 << 2) 57 #define MAX1027_NAVG_8 (0x01 << 2) 58 #define MAX1027_NAVG_16 (0x02 << 2) 59 #define MAX1027_NAVG_32 (0x03 << 2) 60 #define MAX1027_AVG_EN BIT(4) 61 62 /* Device can achieve 300ksps so we assume a 3.33us conversion delay */ 63 #define MAX1027_CONVERSION_UDELAY 4 64 65 enum max1027_id { 66 max1027, 67 max1029, 68 max1031, 69 max1227, 70 max1229, 71 max1231, 72 }; 73 74 static const struct spi_device_id max1027_id[] = { 75 { .name = "max1027", .driver_data = max1027 }, 76 { .name = "max1029", .driver_data = max1029 }, 77 { .name = "max1031", .driver_data = max1031 }, 78 { .name = "max1227", .driver_data = max1227 }, 79 { .name = "max1229", .driver_data = max1229 }, 80 { .name = "max1231", .driver_data = max1231 }, 81 { } 82 }; 83 MODULE_DEVICE_TABLE(spi, max1027_id); 84 85 static const struct of_device_id max1027_adc_dt_ids[] = { 86 { .compatible = "maxim,max1027" }, 87 { .compatible = "maxim,max1029" }, 88 { .compatible = "maxim,max1031" }, 89 { .compatible = "maxim,max1227" }, 90 { .compatible = "maxim,max1229" }, 91 { .compatible = "maxim,max1231" }, 92 { } 93 }; 94 MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids); 95 96 #define MAX1027_V_CHAN(index, depth) \ 97 { \ 98 .type = IIO_VOLTAGE, \ 99 .indexed = 1, \ 100 .channel = index, \ 101 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 102 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 103 .scan_index = index + 1, \ 104 .scan_type = { \ 105 .sign = 'u', \ 106 .realbits = depth, \ 107 .storagebits = 16, \ 108 .shift = (depth == 10) ? 2 : 0, \ 109 .endianness = IIO_BE, \ 110 }, \ 111 } 112 113 #define MAX1027_T_CHAN \ 114 { \ 115 .type = IIO_TEMP, \ 116 .channel = 0, \ 117 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 118 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 119 .scan_index = 0, \ 120 .scan_type = { \ 121 .sign = 'u', \ 122 .realbits = 12, \ 123 .storagebits = 16, \ 124 .endianness = IIO_BE, \ 125 }, \ 126 } 127 128 #define MAX1X27_CHANNELS(depth) \ 129 MAX1027_T_CHAN, \ 130 MAX1027_V_CHAN(0, depth), \ 131 MAX1027_V_CHAN(1, depth), \ 132 MAX1027_V_CHAN(2, depth), \ 133 MAX1027_V_CHAN(3, depth), \ 134 MAX1027_V_CHAN(4, depth), \ 135 MAX1027_V_CHAN(5, depth), \ 136 MAX1027_V_CHAN(6, depth), \ 137 MAX1027_V_CHAN(7, depth) 138 139 #define MAX1X29_CHANNELS(depth) \ 140 MAX1X27_CHANNELS(depth), \ 141 MAX1027_V_CHAN(8, depth), \ 142 MAX1027_V_CHAN(9, depth), \ 143 MAX1027_V_CHAN(10, depth), \ 144 MAX1027_V_CHAN(11, depth) 145 146 #define MAX1X31_CHANNELS(depth) \ 147 MAX1X29_CHANNELS(depth), \ 148 MAX1027_V_CHAN(12, depth), \ 149 MAX1027_V_CHAN(13, depth), \ 150 MAX1027_V_CHAN(14, depth), \ 151 MAX1027_V_CHAN(15, depth) 152 153 static const struct iio_chan_spec max1027_channels[] = { 154 MAX1X27_CHANNELS(10), 155 }; 156 157 static const struct iio_chan_spec max1029_channels[] = { 158 MAX1X29_CHANNELS(10), 159 }; 160 161 static const struct iio_chan_spec max1031_channels[] = { 162 MAX1X31_CHANNELS(10), 163 }; 164 165 static const struct iio_chan_spec max1227_channels[] = { 166 MAX1X27_CHANNELS(12), 167 }; 168 169 static const struct iio_chan_spec max1229_channels[] = { 170 MAX1X29_CHANNELS(12), 171 }; 172 173 static const struct iio_chan_spec max1231_channels[] = { 174 MAX1X31_CHANNELS(12), 175 }; 176 177 /* 178 * These devices are able to scan from 0 to N, N being the highest voltage 179 * channel requested by the user. The temperature can be included or not, 180 * but cannot be retrieved alone. Based on the below 181 * ->available_scan_masks, the core will select the most appropriate 182 * ->active_scan_mask and the "minimum" number of channels will be 183 * scanned and pushed to the buffers. 184 * 185 * For example, if the user wants channels 1, 4 and 5, all channels from 186 * 0 to 5 will be scanned and pushed to the IIO buffers. The core will then 187 * filter out the unneeded samples based on the ->active_scan_mask that has 188 * been selected and only channels 1, 4 and 5 will be available to the user 189 * in the shared buffer. 190 */ 191 #define MAX1X27_SCAN_MASK_TEMP BIT(0) 192 193 #define MAX1X27_SCAN_MASKS(temp) \ 194 GENMASK(1, 1 - (temp)), GENMASK(2, 1 - (temp)), \ 195 GENMASK(3, 1 - (temp)), GENMASK(4, 1 - (temp)), \ 196 GENMASK(5, 1 - (temp)), GENMASK(6, 1 - (temp)), \ 197 GENMASK(7, 1 - (temp)), GENMASK(8, 1 - (temp)) 198 199 #define MAX1X29_SCAN_MASKS(temp) \ 200 MAX1X27_SCAN_MASKS(temp), \ 201 GENMASK(9, 1 - (temp)), GENMASK(10, 1 - (temp)), \ 202 GENMASK(11, 1 - (temp)), GENMASK(12, 1 - (temp)) 203 204 #define MAX1X31_SCAN_MASKS(temp) \ 205 MAX1X29_SCAN_MASKS(temp), \ 206 GENMASK(13, 1 - (temp)), GENMASK(14, 1 - (temp)), \ 207 GENMASK(15, 1 - (temp)), GENMASK(16, 1 - (temp)) 208 209 static const unsigned long max1027_available_scan_masks[] = { 210 MAX1X27_SCAN_MASKS(0), 211 MAX1X27_SCAN_MASKS(1), 212 0x00000000, 213 }; 214 215 static const unsigned long max1029_available_scan_masks[] = { 216 MAX1X29_SCAN_MASKS(0), 217 MAX1X29_SCAN_MASKS(1), 218 0x00000000, 219 }; 220 221 static const unsigned long max1031_available_scan_masks[] = { 222 MAX1X31_SCAN_MASKS(0), 223 MAX1X31_SCAN_MASKS(1), 224 0x00000000, 225 }; 226 227 struct max1027_chip_info { 228 const struct iio_chan_spec *channels; 229 unsigned int num_channels; 230 const unsigned long *available_scan_masks; 231 }; 232 233 static const struct max1027_chip_info max1027_chip_info_tbl[] = { 234 [max1027] = { 235 .channels = max1027_channels, 236 .num_channels = ARRAY_SIZE(max1027_channels), 237 .available_scan_masks = max1027_available_scan_masks, 238 }, 239 [max1029] = { 240 .channels = max1029_channels, 241 .num_channels = ARRAY_SIZE(max1029_channels), 242 .available_scan_masks = max1029_available_scan_masks, 243 }, 244 [max1031] = { 245 .channels = max1031_channels, 246 .num_channels = ARRAY_SIZE(max1031_channels), 247 .available_scan_masks = max1031_available_scan_masks, 248 }, 249 [max1227] = { 250 .channels = max1227_channels, 251 .num_channels = ARRAY_SIZE(max1227_channels), 252 .available_scan_masks = max1027_available_scan_masks, 253 }, 254 [max1229] = { 255 .channels = max1229_channels, 256 .num_channels = ARRAY_SIZE(max1229_channels), 257 .available_scan_masks = max1029_available_scan_masks, 258 }, 259 [max1231] = { 260 .channels = max1231_channels, 261 .num_channels = ARRAY_SIZE(max1231_channels), 262 .available_scan_masks = max1031_available_scan_masks, 263 }, 264 }; 265 266 struct max1027_state { 267 const struct max1027_chip_info *info; 268 struct spi_device *spi; 269 struct iio_trigger *trig; 270 __be16 *buffer; 271 struct mutex lock; 272 struct completion complete; 273 274 u8 reg __aligned(IIO_DMA_MINALIGN); 275 }; 276 277 static int max1027_wait_eoc(struct iio_dev *indio_dev) 278 { 279 struct max1027_state *st = iio_priv(indio_dev); 280 unsigned int conversion_time = MAX1027_CONVERSION_UDELAY; 281 int ret; 282 283 if (st->spi->irq) { 284 ret = wait_for_completion_timeout(&st->complete, 285 msecs_to_jiffies(1000)); 286 reinit_completion(&st->complete); 287 if (!ret) 288 return -ETIMEDOUT; 289 } else { 290 if (indio_dev->active_scan_mask) 291 conversion_time *= hweight32(*indio_dev->active_scan_mask); 292 293 usleep_range(conversion_time, conversion_time * 2); 294 } 295 296 return 0; 297 } 298 299 /* Scan from chan 0 to the highest requested channel. Include temperature on demand. */ 300 static int max1027_configure_chans_and_start(struct iio_dev *indio_dev) 301 { 302 struct max1027_state *st = iio_priv(indio_dev); 303 304 st->reg = MAX1027_CONV_REG | MAX1027_SCAN_0_N; 305 st->reg |= MAX1027_CHAN(fls(*indio_dev->active_scan_mask) - 2); 306 if (*indio_dev->active_scan_mask & MAX1X27_SCAN_MASK_TEMP) 307 st->reg |= MAX1027_TEMP; 308 309 return spi_write(st->spi, &st->reg, 1); 310 } 311 312 static int max1027_enable_trigger(struct iio_dev *indio_dev, bool enable) 313 { 314 struct max1027_state *st = iio_priv(indio_dev); 315 316 st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2; 317 318 /* 319 * Start acquisition on: 320 * MODE0: external hardware trigger wired to the cnvst input pin 321 * MODE2: conversion register write 322 */ 323 if (enable) 324 st->reg |= MAX1027_CKS_MODE0; 325 else 326 st->reg |= MAX1027_CKS_MODE2; 327 328 return spi_write(st->spi, &st->reg, 1); 329 } 330 331 static int max1027_read_single_value(struct iio_dev *indio_dev, 332 struct iio_chan_spec const *chan, 333 int *val) 334 { 335 int ret; 336 struct max1027_state *st = iio_priv(indio_dev); 337 338 /* Configure conversion register with the requested chan */ 339 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) | 340 MAX1027_NOSCAN; 341 if (chan->type == IIO_TEMP) 342 st->reg |= MAX1027_TEMP; 343 ret = spi_write(st->spi, &st->reg, 1); 344 if (ret < 0) { 345 dev_err(&indio_dev->dev, 346 "Failed to configure conversion register\n"); 347 return ret; 348 } 349 350 /* 351 * For an unknown reason, when we use the mode "10" (write 352 * conversion register), the interrupt doesn't occur every time. 353 * So we just wait the maximum conversion time and deliver the value. 354 */ 355 ret = max1027_wait_eoc(indio_dev); 356 if (ret) 357 return ret; 358 359 /* Read result */ 360 ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2); 361 if (ret < 0) 362 return ret; 363 364 *val = be16_to_cpu(st->buffer[0]); 365 366 return IIO_VAL_INT; 367 } 368 369 static int max1027_read_raw(struct iio_dev *indio_dev, 370 struct iio_chan_spec const *chan, 371 int *val, int *val2, long mask) 372 { 373 int ret = 0; 374 struct max1027_state *st = iio_priv(indio_dev); 375 376 guard(mutex)(&st->lock); 377 378 switch (mask) { 379 case IIO_CHAN_INFO_RAW: 380 if (!iio_device_claim_direct(indio_dev)) 381 return -EBUSY; 382 383 ret = max1027_read_single_value(indio_dev, chan, val); 384 iio_device_release_direct(indio_dev); 385 return ret; 386 case IIO_CHAN_INFO_SCALE: 387 switch (chan->type) { 388 case IIO_TEMP: 389 *val = 1; 390 *val2 = 8; 391 return IIO_VAL_FRACTIONAL; 392 case IIO_VOLTAGE: 393 *val = 2500; 394 *val2 = chan->scan_type.realbits; 395 return IIO_VAL_FRACTIONAL_LOG2; 396 default: 397 return -EINVAL; 398 } 399 default: 400 return -EINVAL; 401 } 402 } 403 404 static int max1027_debugfs_reg_access(struct iio_dev *indio_dev, 405 unsigned int reg, unsigned int writeval, 406 unsigned int *readval) 407 { 408 struct max1027_state *st = iio_priv(indio_dev); 409 u8 *val = (u8 *)st->buffer; 410 411 if (readval) { 412 int ret = spi_read(st->spi, val, 2); 413 *readval = be16_to_cpu(st->buffer[0]); 414 return ret; 415 } 416 417 *val = (u8)writeval; 418 return spi_write(st->spi, val, 1); 419 } 420 421 static int max1027_set_cnvst_trigger_state(struct iio_trigger *trig, bool state) 422 { 423 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 424 int ret; 425 426 /* 427 * In order to disable the convst trigger, start acquisition on 428 * conversion register write, which basically disables triggering 429 * conversions upon cnvst changes and thus has the effect of disabling 430 * the external hardware trigger. 431 */ 432 ret = max1027_enable_trigger(indio_dev, state); 433 if (ret) 434 return ret; 435 436 if (state) { 437 ret = max1027_configure_chans_and_start(indio_dev); 438 if (ret) 439 return ret; 440 } 441 442 return 0; 443 } 444 445 static int max1027_read_scan(struct iio_dev *indio_dev) 446 { 447 struct max1027_state *st = iio_priv(indio_dev); 448 unsigned int scanned_chans; 449 int ret; 450 451 scanned_chans = fls(*indio_dev->active_scan_mask) - 1; 452 if (*indio_dev->active_scan_mask & MAX1X27_SCAN_MASK_TEMP) 453 scanned_chans++; 454 455 /* fill buffer with all channel */ 456 ret = spi_read(st->spi, st->buffer, scanned_chans * 2); 457 if (ret < 0) 458 return ret; 459 460 iio_push_to_buffers(indio_dev, st->buffer); 461 462 return 0; 463 } 464 465 static irqreturn_t max1027_handler(int irq, void *private) 466 { 467 struct iio_dev *indio_dev = private; 468 struct max1027_state *st = iio_priv(indio_dev); 469 470 /* 471 * If buffers are disabled (raw read) or when using external triggers, 472 * we just need to unlock the waiters which will then handle the data. 473 * 474 * When using the internal trigger, we must hand-off the choice of the 475 * handler to the core which will then lookup through the interrupt tree 476 * for the right handler registered with iio_triggered_buffer_setup() 477 * to execute, as this trigger might very well be used in conjunction 478 * with another device. The core will then call the relevant handler to 479 * perform the data processing step. 480 */ 481 if (!iio_buffer_enabled(indio_dev)) 482 complete(&st->complete); 483 else 484 iio_trigger_poll(indio_dev->trig); 485 486 return IRQ_HANDLED; 487 } 488 489 static irqreturn_t max1027_trigger_handler(int irq, void *private) 490 { 491 struct iio_poll_func *pf = private; 492 struct iio_dev *indio_dev = pf->indio_dev; 493 int ret; 494 495 if (!iio_trigger_using_own(indio_dev)) { 496 ret = max1027_configure_chans_and_start(indio_dev); 497 if (ret) 498 goto out; 499 500 /* This is a threaded handler, it is fine to wait for an IRQ */ 501 ret = max1027_wait_eoc(indio_dev); 502 if (ret) 503 goto out; 504 } 505 506 ret = max1027_read_scan(indio_dev); 507 out: 508 if (ret) 509 dev_err(&indio_dev->dev, 510 "Cannot read scanned values (%d)\n", ret); 511 512 iio_trigger_notify_done(indio_dev->trig); 513 514 return IRQ_HANDLED; 515 } 516 517 static const struct iio_trigger_ops max1027_trigger_ops = { 518 .validate_device = &iio_trigger_validate_own_device, 519 .set_trigger_state = &max1027_set_cnvst_trigger_state, 520 }; 521 522 static const struct iio_info max1027_info = { 523 .read_raw = &max1027_read_raw, 524 .debugfs_reg_access = &max1027_debugfs_reg_access, 525 }; 526 527 static int max1027_probe(struct spi_device *spi) 528 { 529 int ret; 530 struct iio_dev *indio_dev; 531 struct max1027_state *st; 532 533 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 534 if (!indio_dev) { 535 pr_err("Can't allocate iio device\n"); 536 return -ENOMEM; 537 } 538 539 st = iio_priv(indio_dev); 540 st->spi = spi; 541 st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data]; 542 543 mutex_init(&st->lock); 544 init_completion(&st->complete); 545 546 indio_dev->name = spi_get_device_id(spi)->name; 547 indio_dev->info = &max1027_info; 548 indio_dev->modes = INDIO_DIRECT_MODE; 549 indio_dev->channels = st->info->channels; 550 indio_dev->num_channels = st->info->num_channels; 551 indio_dev->available_scan_masks = st->info->available_scan_masks; 552 553 st->buffer = devm_kmalloc_array(&indio_dev->dev, 554 indio_dev->num_channels, 2, 555 GFP_KERNEL); 556 if (!st->buffer) 557 return -ENOMEM; 558 559 /* Enable triggered buffers */ 560 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 561 &iio_pollfunc_store_time, 562 &max1027_trigger_handler, 563 NULL); 564 if (ret < 0) { 565 dev_err(&indio_dev->dev, "Failed to setup buffer\n"); 566 return ret; 567 } 568 569 /* If there is an EOC interrupt, register the cnvst hardware trigger */ 570 if (spi->irq) { 571 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger", 572 indio_dev->name); 573 if (!st->trig) { 574 ret = -ENOMEM; 575 dev_err(&indio_dev->dev, 576 "Failed to allocate iio trigger\n"); 577 return ret; 578 } 579 580 st->trig->ops = &max1027_trigger_ops; 581 iio_trigger_set_drvdata(st->trig, indio_dev); 582 ret = devm_iio_trigger_register(&indio_dev->dev, 583 st->trig); 584 if (ret < 0) { 585 dev_err(&indio_dev->dev, 586 "Failed to register iio trigger\n"); 587 return ret; 588 } 589 590 ret = devm_request_irq(&spi->dev, spi->irq, max1027_handler, 591 IRQF_TRIGGER_FALLING, 592 spi->dev.driver->name, indio_dev); 593 if (ret < 0) { 594 dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n"); 595 return ret; 596 } 597 } 598 599 /* Internal reset */ 600 st->reg = MAX1027_RST_REG; 601 ret = spi_write(st->spi, &st->reg, 1); 602 if (ret < 0) { 603 dev_err(&indio_dev->dev, "Failed to reset the ADC\n"); 604 return ret; 605 } 606 607 /* Disable averaging */ 608 st->reg = MAX1027_AVG_REG; 609 ret = spi_write(st->spi, &st->reg, 1); 610 if (ret < 0) { 611 dev_err(&indio_dev->dev, "Failed to configure averaging register\n"); 612 return ret; 613 } 614 615 /* Assume conversion on register write for now */ 616 ret = max1027_enable_trigger(indio_dev, false); 617 if (ret) 618 return ret; 619 620 return devm_iio_device_register(&spi->dev, indio_dev); 621 } 622 623 static struct spi_driver max1027_driver = { 624 .driver = { 625 .name = "max1027", 626 .of_match_table = max1027_adc_dt_ids, 627 }, 628 .probe = max1027_probe, 629 .id_table = max1027_id, 630 }; 631 module_spi_driver(max1027_driver); 632 633 MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>"); 634 MODULE_DESCRIPTION("MAX1X27/MAX1X29/MAX1X31 ADC"); 635 MODULE_LICENSE("GPL v2"); 636