xref: /linux/drivers/iio/adc/max1027.c (revision fc167f62483325aea9137e70e6773fe7ad1ca2ac)
1*fc167f62SPhilippe Reynes  /*
2*fc167f62SPhilippe Reynes   * iio/adc/max1027.c
3*fc167f62SPhilippe Reynes   * Copyright (C) 2014 Philippe Reynes
4*fc167f62SPhilippe Reynes   *
5*fc167f62SPhilippe Reynes   * based on linux/drivers/iio/ad7923.c
6*fc167f62SPhilippe Reynes   * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
7*fc167f62SPhilippe Reynes   * Copyright 2012 CS Systemes d'Information
8*fc167f62SPhilippe Reynes   *
9*fc167f62SPhilippe Reynes   * This program is free software; you can redistribute it and/or modify
10*fc167f62SPhilippe Reynes   * it under the terms of the GNU General Public License version 2 as
11*fc167f62SPhilippe Reynes   * published by the Free Software Foundation.
12*fc167f62SPhilippe Reynes   *
13*fc167f62SPhilippe Reynes   * max1027.c
14*fc167f62SPhilippe Reynes   *
15*fc167f62SPhilippe Reynes   * Partial support for max1027 and similar chips.
16*fc167f62SPhilippe Reynes   */
17*fc167f62SPhilippe Reynes 
18*fc167f62SPhilippe Reynes #include <linux/kernel.h>
19*fc167f62SPhilippe Reynes #include <linux/module.h>
20*fc167f62SPhilippe Reynes #include <linux/spi/spi.h>
21*fc167f62SPhilippe Reynes #include <linux/delay.h>
22*fc167f62SPhilippe Reynes 
23*fc167f62SPhilippe Reynes #include <linux/iio/iio.h>
24*fc167f62SPhilippe Reynes #include <linux/iio/buffer.h>
25*fc167f62SPhilippe Reynes #include <linux/iio/trigger.h>
26*fc167f62SPhilippe Reynes #include <linux/iio/trigger_consumer.h>
27*fc167f62SPhilippe Reynes #include <linux/iio/triggered_buffer.h>
28*fc167f62SPhilippe Reynes 
29*fc167f62SPhilippe Reynes #define MAX1027_CONV_REG  BIT(7)
30*fc167f62SPhilippe Reynes #define MAX1027_SETUP_REG BIT(6)
31*fc167f62SPhilippe Reynes #define MAX1027_AVG_REG   BIT(5)
32*fc167f62SPhilippe Reynes #define MAX1027_RST_REG   BIT(4)
33*fc167f62SPhilippe Reynes 
34*fc167f62SPhilippe Reynes /* conversion register */
35*fc167f62SPhilippe Reynes #define MAX1027_TEMP      BIT(0)
36*fc167f62SPhilippe Reynes #define MAX1027_SCAN_0_N  (0x00 << 1)
37*fc167f62SPhilippe Reynes #define MAX1027_SCAN_N_M  (0x01 << 1)
38*fc167f62SPhilippe Reynes #define MAX1027_SCAN_N    (0x02 << 1)
39*fc167f62SPhilippe Reynes #define MAX1027_NOSCAN    (0x03 << 1)
40*fc167f62SPhilippe Reynes #define MAX1027_CHAN(n)   ((n) << 3)
41*fc167f62SPhilippe Reynes 
42*fc167f62SPhilippe Reynes /* setup register */
43*fc167f62SPhilippe Reynes #define MAX1027_UNIPOLAR  0x02
44*fc167f62SPhilippe Reynes #define MAX1027_BIPOLAR   0x03
45*fc167f62SPhilippe Reynes #define MAX1027_REF_MODE0 (0x00 << 2)
46*fc167f62SPhilippe Reynes #define MAX1027_REF_MODE1 (0x01 << 2)
47*fc167f62SPhilippe Reynes #define MAX1027_REF_MODE2 (0x02 << 2)
48*fc167f62SPhilippe Reynes #define MAX1027_REF_MODE3 (0x03 << 2)
49*fc167f62SPhilippe Reynes #define MAX1027_CKS_MODE0 (0x00 << 4)
50*fc167f62SPhilippe Reynes #define MAX1027_CKS_MODE1 (0x01 << 4)
51*fc167f62SPhilippe Reynes #define MAX1027_CKS_MODE2 (0x02 << 4)
52*fc167f62SPhilippe Reynes #define MAX1027_CKS_MODE3 (0x03 << 4)
53*fc167f62SPhilippe Reynes 
54*fc167f62SPhilippe Reynes /* averaging register */
55*fc167f62SPhilippe Reynes #define MAX1027_NSCAN_4   0x00
56*fc167f62SPhilippe Reynes #define MAX1027_NSCAN_8   0x01
57*fc167f62SPhilippe Reynes #define MAX1027_NSCAN_12  0x02
58*fc167f62SPhilippe Reynes #define MAX1027_NSCAN_16  0x03
59*fc167f62SPhilippe Reynes #define MAX1027_NAVG_4    (0x00 << 2)
60*fc167f62SPhilippe Reynes #define MAX1027_NAVG_8    (0x01 << 2)
61*fc167f62SPhilippe Reynes #define MAX1027_NAVG_16   (0x02 << 2)
62*fc167f62SPhilippe Reynes #define MAX1027_NAVG_32   (0x03 << 2)
63*fc167f62SPhilippe Reynes #define MAX1027_AVG_EN    BIT(4)
64*fc167f62SPhilippe Reynes 
65*fc167f62SPhilippe Reynes enum max1027_id {
66*fc167f62SPhilippe Reynes 	max1027,
67*fc167f62SPhilippe Reynes 	max1029,
68*fc167f62SPhilippe Reynes 	max1031,
69*fc167f62SPhilippe Reynes };
70*fc167f62SPhilippe Reynes 
71*fc167f62SPhilippe Reynes static const struct spi_device_id max1027_id[] = {
72*fc167f62SPhilippe Reynes 	{"max1027", max1027},
73*fc167f62SPhilippe Reynes 	{"max1029", max1029},
74*fc167f62SPhilippe Reynes 	{"max1031", max1031},
75*fc167f62SPhilippe Reynes 	{}
76*fc167f62SPhilippe Reynes };
77*fc167f62SPhilippe Reynes MODULE_DEVICE_TABLE(spi, max1027_id);
78*fc167f62SPhilippe Reynes 
79*fc167f62SPhilippe Reynes #ifdef CONFIG_OF
80*fc167f62SPhilippe Reynes static const struct of_device_id max1027_adc_dt_ids[] = {
81*fc167f62SPhilippe Reynes 	{ .compatible = "maxim,max1027" },
82*fc167f62SPhilippe Reynes 	{ .compatible = "maxim,max1029" },
83*fc167f62SPhilippe Reynes 	{ .compatible = "maxim,max1031" },
84*fc167f62SPhilippe Reynes 	{},
85*fc167f62SPhilippe Reynes };
86*fc167f62SPhilippe Reynes MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
87*fc167f62SPhilippe Reynes #endif
88*fc167f62SPhilippe Reynes 
89*fc167f62SPhilippe Reynes #define MAX1027_V_CHAN(index)						\
90*fc167f62SPhilippe Reynes 	{								\
91*fc167f62SPhilippe Reynes 		.type = IIO_VOLTAGE,					\
92*fc167f62SPhilippe Reynes 		.indexed = 1,						\
93*fc167f62SPhilippe Reynes 		.channel = index,					\
94*fc167f62SPhilippe Reynes 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
95*fc167f62SPhilippe Reynes 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
96*fc167f62SPhilippe Reynes 		.scan_index = index + 1,				\
97*fc167f62SPhilippe Reynes 		.scan_type = {						\
98*fc167f62SPhilippe Reynes 			.sign = 'u',					\
99*fc167f62SPhilippe Reynes 			.realbits = 10,					\
100*fc167f62SPhilippe Reynes 			.storagebits = 16,				\
101*fc167f62SPhilippe Reynes 			.shift = 2,					\
102*fc167f62SPhilippe Reynes 			.endianness = IIO_BE,				\
103*fc167f62SPhilippe Reynes 		},							\
104*fc167f62SPhilippe Reynes 	}
105*fc167f62SPhilippe Reynes 
106*fc167f62SPhilippe Reynes #define MAX1027_T_CHAN							\
107*fc167f62SPhilippe Reynes 	{								\
108*fc167f62SPhilippe Reynes 		.type = IIO_TEMP,					\
109*fc167f62SPhilippe Reynes 		.channel = 0,						\
110*fc167f62SPhilippe Reynes 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
111*fc167f62SPhilippe Reynes 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
112*fc167f62SPhilippe Reynes 		.scan_index = 0,					\
113*fc167f62SPhilippe Reynes 		.scan_type = {						\
114*fc167f62SPhilippe Reynes 			.sign = 'u',					\
115*fc167f62SPhilippe Reynes 			.realbits = 12,					\
116*fc167f62SPhilippe Reynes 			.storagebits = 16,				\
117*fc167f62SPhilippe Reynes 			.endianness = IIO_BE,				\
118*fc167f62SPhilippe Reynes 		},							\
119*fc167f62SPhilippe Reynes 	}
120*fc167f62SPhilippe Reynes 
121*fc167f62SPhilippe Reynes static const struct iio_chan_spec max1027_channels[] = {
122*fc167f62SPhilippe Reynes 	MAX1027_T_CHAN,
123*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(0),
124*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(1),
125*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(2),
126*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(3),
127*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(4),
128*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(5),
129*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(6),
130*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(7)
131*fc167f62SPhilippe Reynes };
132*fc167f62SPhilippe Reynes 
133*fc167f62SPhilippe Reynes static const struct iio_chan_spec max1029_channels[] = {
134*fc167f62SPhilippe Reynes 	MAX1027_T_CHAN,
135*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(0),
136*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(1),
137*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(2),
138*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(3),
139*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(4),
140*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(5),
141*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(6),
142*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(7),
143*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(8),
144*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(9),
145*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(10),
146*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(11)
147*fc167f62SPhilippe Reynes };
148*fc167f62SPhilippe Reynes 
149*fc167f62SPhilippe Reynes static const struct iio_chan_spec max1031_channels[] = {
150*fc167f62SPhilippe Reynes 	MAX1027_T_CHAN,
151*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(0),
152*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(1),
153*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(2),
154*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(3),
155*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(4),
156*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(5),
157*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(6),
158*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(7),
159*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(8),
160*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(9),
161*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(10),
162*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(11),
163*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(12),
164*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(13),
165*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(14),
166*fc167f62SPhilippe Reynes 	MAX1027_V_CHAN(15)
167*fc167f62SPhilippe Reynes };
168*fc167f62SPhilippe Reynes 
169*fc167f62SPhilippe Reynes static const unsigned long max1027_available_scan_masks[] = {
170*fc167f62SPhilippe Reynes 	0x000001ff,
171*fc167f62SPhilippe Reynes 	0x00000000,
172*fc167f62SPhilippe Reynes };
173*fc167f62SPhilippe Reynes 
174*fc167f62SPhilippe Reynes static const unsigned long max1029_available_scan_masks[] = {
175*fc167f62SPhilippe Reynes 	0x00001fff,
176*fc167f62SPhilippe Reynes 	0x00000000,
177*fc167f62SPhilippe Reynes };
178*fc167f62SPhilippe Reynes 
179*fc167f62SPhilippe Reynes static const unsigned long max1031_available_scan_masks[] = {
180*fc167f62SPhilippe Reynes 	0x0001ffff,
181*fc167f62SPhilippe Reynes 	0x00000000,
182*fc167f62SPhilippe Reynes };
183*fc167f62SPhilippe Reynes 
184*fc167f62SPhilippe Reynes struct max1027_chip_info {
185*fc167f62SPhilippe Reynes 	const struct iio_chan_spec *channels;
186*fc167f62SPhilippe Reynes 	unsigned int num_channels;
187*fc167f62SPhilippe Reynes 	const unsigned long *available_scan_masks;
188*fc167f62SPhilippe Reynes };
189*fc167f62SPhilippe Reynes 
190*fc167f62SPhilippe Reynes static const struct max1027_chip_info max1027_chip_info_tbl[] = {
191*fc167f62SPhilippe Reynes 	[max1027] = {
192*fc167f62SPhilippe Reynes 		.channels = max1027_channels,
193*fc167f62SPhilippe Reynes 		.num_channels = ARRAY_SIZE(max1027_channels),
194*fc167f62SPhilippe Reynes 		.available_scan_masks = max1027_available_scan_masks,
195*fc167f62SPhilippe Reynes 	},
196*fc167f62SPhilippe Reynes 	[max1029] = {
197*fc167f62SPhilippe Reynes 		.channels = max1029_channels,
198*fc167f62SPhilippe Reynes 		.num_channels = ARRAY_SIZE(max1029_channels),
199*fc167f62SPhilippe Reynes 		.available_scan_masks = max1029_available_scan_masks,
200*fc167f62SPhilippe Reynes 	},
201*fc167f62SPhilippe Reynes 	[max1031] = {
202*fc167f62SPhilippe Reynes 		.channels = max1031_channels,
203*fc167f62SPhilippe Reynes 		.num_channels = ARRAY_SIZE(max1031_channels),
204*fc167f62SPhilippe Reynes 		.available_scan_masks = max1031_available_scan_masks,
205*fc167f62SPhilippe Reynes 	},
206*fc167f62SPhilippe Reynes };
207*fc167f62SPhilippe Reynes 
208*fc167f62SPhilippe Reynes struct max1027_state {
209*fc167f62SPhilippe Reynes 	const struct max1027_chip_info	*info;
210*fc167f62SPhilippe Reynes 	struct spi_device		*spi;
211*fc167f62SPhilippe Reynes 	struct iio_trigger		*trig;
212*fc167f62SPhilippe Reynes 	__be16				*buffer;
213*fc167f62SPhilippe Reynes 	struct mutex			lock;
214*fc167f62SPhilippe Reynes 
215*fc167f62SPhilippe Reynes 	u8				reg ____cacheline_aligned;
216*fc167f62SPhilippe Reynes };
217*fc167f62SPhilippe Reynes 
218*fc167f62SPhilippe Reynes static int max1027_read_single_value(struct iio_dev *indio_dev,
219*fc167f62SPhilippe Reynes 				     struct iio_chan_spec const *chan,
220*fc167f62SPhilippe Reynes 				     int *val)
221*fc167f62SPhilippe Reynes {
222*fc167f62SPhilippe Reynes 	int ret;
223*fc167f62SPhilippe Reynes 	struct max1027_state *st = iio_priv(indio_dev);
224*fc167f62SPhilippe Reynes 
225*fc167f62SPhilippe Reynes 	if (iio_buffer_enabled(indio_dev)) {
226*fc167f62SPhilippe Reynes 		dev_warn(&indio_dev->dev, "trigger mode already enabled");
227*fc167f62SPhilippe Reynes 		return -EBUSY;
228*fc167f62SPhilippe Reynes 	}
229*fc167f62SPhilippe Reynes 
230*fc167f62SPhilippe Reynes 	/* Start acquisition on conversion register write */
231*fc167f62SPhilippe Reynes 	st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
232*fc167f62SPhilippe Reynes 	ret = spi_write(st->spi, &st->reg, 1);
233*fc167f62SPhilippe Reynes 	if (ret < 0) {
234*fc167f62SPhilippe Reynes 		dev_err(&indio_dev->dev,
235*fc167f62SPhilippe Reynes 			"Failed to configure setup register\n");
236*fc167f62SPhilippe Reynes 		return ret;
237*fc167f62SPhilippe Reynes 	}
238*fc167f62SPhilippe Reynes 
239*fc167f62SPhilippe Reynes 	/* Configure conversion register with the requested chan */
240*fc167f62SPhilippe Reynes 	st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
241*fc167f62SPhilippe Reynes 		  MAX1027_NOSCAN | !!(chan->type == IIO_TEMP);
242*fc167f62SPhilippe Reynes 	ret = spi_write(st->spi, &st->reg, 1);
243*fc167f62SPhilippe Reynes 	if (ret < 0) {
244*fc167f62SPhilippe Reynes 		dev_err(&indio_dev->dev,
245*fc167f62SPhilippe Reynes 			"Failed to configure conversion register\n");
246*fc167f62SPhilippe Reynes 		return ret;
247*fc167f62SPhilippe Reynes 	}
248*fc167f62SPhilippe Reynes 
249*fc167f62SPhilippe Reynes 	/*
250*fc167f62SPhilippe Reynes 	 * For an unknown reason, when we use the mode "10" (write
251*fc167f62SPhilippe Reynes 	 * conversion register), the interrupt doesn't occur every time.
252*fc167f62SPhilippe Reynes 	 * So we just wait 1 ms.
253*fc167f62SPhilippe Reynes 	 */
254*fc167f62SPhilippe Reynes 	mdelay(1);
255*fc167f62SPhilippe Reynes 
256*fc167f62SPhilippe Reynes 	/* Read result */
257*fc167f62SPhilippe Reynes 	ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
258*fc167f62SPhilippe Reynes 	if (ret < 0)
259*fc167f62SPhilippe Reynes 		return ret;
260*fc167f62SPhilippe Reynes 
261*fc167f62SPhilippe Reynes 	*val = be16_to_cpu(st->buffer[0]);
262*fc167f62SPhilippe Reynes 
263*fc167f62SPhilippe Reynes 	return IIO_VAL_INT;
264*fc167f62SPhilippe Reynes }
265*fc167f62SPhilippe Reynes 
266*fc167f62SPhilippe Reynes static int max1027_read_raw(struct iio_dev *indio_dev,
267*fc167f62SPhilippe Reynes 			    struct iio_chan_spec const *chan,
268*fc167f62SPhilippe Reynes 			    int *val, int *val2, long mask)
269*fc167f62SPhilippe Reynes {
270*fc167f62SPhilippe Reynes 	int ret = 0;
271*fc167f62SPhilippe Reynes 	struct max1027_state *st = iio_priv(indio_dev);
272*fc167f62SPhilippe Reynes 
273*fc167f62SPhilippe Reynes 	mutex_lock(&st->lock);
274*fc167f62SPhilippe Reynes 
275*fc167f62SPhilippe Reynes 	switch (mask) {
276*fc167f62SPhilippe Reynes 	case IIO_CHAN_INFO_RAW:
277*fc167f62SPhilippe Reynes 		ret = max1027_read_single_value(indio_dev, chan, val);
278*fc167f62SPhilippe Reynes 		break;
279*fc167f62SPhilippe Reynes 	case IIO_CHAN_INFO_SCALE:
280*fc167f62SPhilippe Reynes 		switch (chan->type) {
281*fc167f62SPhilippe Reynes 		case IIO_TEMP:
282*fc167f62SPhilippe Reynes 			*val = 1;
283*fc167f62SPhilippe Reynes 			*val2 = 8;
284*fc167f62SPhilippe Reynes 			ret = IIO_VAL_FRACTIONAL;
285*fc167f62SPhilippe Reynes 			break;
286*fc167f62SPhilippe Reynes 		case IIO_VOLTAGE:
287*fc167f62SPhilippe Reynes 			*val = 2500;
288*fc167f62SPhilippe Reynes 			*val2 = 10;
289*fc167f62SPhilippe Reynes 			ret = IIO_VAL_FRACTIONAL_LOG2;
290*fc167f62SPhilippe Reynes 			break;
291*fc167f62SPhilippe Reynes 		default:
292*fc167f62SPhilippe Reynes 			ret = -EINVAL;
293*fc167f62SPhilippe Reynes 			break;
294*fc167f62SPhilippe Reynes 		}
295*fc167f62SPhilippe Reynes 		break;
296*fc167f62SPhilippe Reynes 	default:
297*fc167f62SPhilippe Reynes 		ret = -EINVAL;
298*fc167f62SPhilippe Reynes 		break;
299*fc167f62SPhilippe Reynes 	}
300*fc167f62SPhilippe Reynes 
301*fc167f62SPhilippe Reynes 	mutex_unlock(&st->lock);
302*fc167f62SPhilippe Reynes 
303*fc167f62SPhilippe Reynes 	return ret;
304*fc167f62SPhilippe Reynes }
305*fc167f62SPhilippe Reynes 
306*fc167f62SPhilippe Reynes static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
307*fc167f62SPhilippe Reynes 				      unsigned reg, unsigned writeval,
308*fc167f62SPhilippe Reynes 				      unsigned *readval)
309*fc167f62SPhilippe Reynes {
310*fc167f62SPhilippe Reynes 	struct max1027_state *st = iio_priv(indio_dev);
311*fc167f62SPhilippe Reynes 	u8 *val = (u8 *)st->buffer;
312*fc167f62SPhilippe Reynes 
313*fc167f62SPhilippe Reynes 	if (readval != NULL)
314*fc167f62SPhilippe Reynes 		return -EINVAL;
315*fc167f62SPhilippe Reynes 
316*fc167f62SPhilippe Reynes 	*val = (u8)writeval;
317*fc167f62SPhilippe Reynes 	return spi_write(st->spi, val, 1);
318*fc167f62SPhilippe Reynes }
319*fc167f62SPhilippe Reynes 
320*fc167f62SPhilippe Reynes static int max1027_validate_trigger(struct iio_dev *indio_dev,
321*fc167f62SPhilippe Reynes 				    struct iio_trigger *trig)
322*fc167f62SPhilippe Reynes {
323*fc167f62SPhilippe Reynes 	struct max1027_state *st = iio_priv(indio_dev);
324*fc167f62SPhilippe Reynes 
325*fc167f62SPhilippe Reynes 	if (st->trig != trig)
326*fc167f62SPhilippe Reynes 		return -EINVAL;
327*fc167f62SPhilippe Reynes 
328*fc167f62SPhilippe Reynes 	return 0;
329*fc167f62SPhilippe Reynes }
330*fc167f62SPhilippe Reynes 
331*fc167f62SPhilippe Reynes static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
332*fc167f62SPhilippe Reynes {
333*fc167f62SPhilippe Reynes 	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
334*fc167f62SPhilippe Reynes 	struct max1027_state *st = iio_priv(indio_dev);
335*fc167f62SPhilippe Reynes 	int ret;
336*fc167f62SPhilippe Reynes 
337*fc167f62SPhilippe Reynes 	if (state) {
338*fc167f62SPhilippe Reynes 		/* Start acquisition on cnvst */
339*fc167f62SPhilippe Reynes 		st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
340*fc167f62SPhilippe Reynes 			  MAX1027_REF_MODE2;
341*fc167f62SPhilippe Reynes 		ret = spi_write(st->spi, &st->reg, 1);
342*fc167f62SPhilippe Reynes 		if (ret < 0)
343*fc167f62SPhilippe Reynes 			return ret;
344*fc167f62SPhilippe Reynes 
345*fc167f62SPhilippe Reynes 		/* Scan from 0 to max */
346*fc167f62SPhilippe Reynes 		st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
347*fc167f62SPhilippe Reynes 			  MAX1027_SCAN_N_M | MAX1027_TEMP;
348*fc167f62SPhilippe Reynes 		ret = spi_write(st->spi, &st->reg, 1);
349*fc167f62SPhilippe Reynes 		if (ret < 0)
350*fc167f62SPhilippe Reynes 			return ret;
351*fc167f62SPhilippe Reynes 	} else {
352*fc167f62SPhilippe Reynes 		/* Start acquisition on conversion register write */
353*fc167f62SPhilippe Reynes 		st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2	|
354*fc167f62SPhilippe Reynes 			  MAX1027_REF_MODE2;
355*fc167f62SPhilippe Reynes 		ret = spi_write(st->spi, &st->reg, 1);
356*fc167f62SPhilippe Reynes 		if (ret < 0)
357*fc167f62SPhilippe Reynes 			return ret;
358*fc167f62SPhilippe Reynes 	}
359*fc167f62SPhilippe Reynes 
360*fc167f62SPhilippe Reynes 	return 0;
361*fc167f62SPhilippe Reynes }
362*fc167f62SPhilippe Reynes 
363*fc167f62SPhilippe Reynes static int max1027_validate_device(struct iio_trigger *trig,
364*fc167f62SPhilippe Reynes 				   struct iio_dev *indio_dev)
365*fc167f62SPhilippe Reynes {
366*fc167f62SPhilippe Reynes 	struct iio_dev *indio = iio_trigger_get_drvdata(trig);
367*fc167f62SPhilippe Reynes 
368*fc167f62SPhilippe Reynes 	if (indio != indio_dev)
369*fc167f62SPhilippe Reynes 		return -EINVAL;
370*fc167f62SPhilippe Reynes 
371*fc167f62SPhilippe Reynes 	return 0;
372*fc167f62SPhilippe Reynes }
373*fc167f62SPhilippe Reynes 
374*fc167f62SPhilippe Reynes static irqreturn_t max1027_trigger_handler(int irq, void *private)
375*fc167f62SPhilippe Reynes {
376*fc167f62SPhilippe Reynes 	struct iio_poll_func *pf = (struct iio_poll_func *)private;
377*fc167f62SPhilippe Reynes 	struct iio_dev *indio_dev = pf->indio_dev;
378*fc167f62SPhilippe Reynes 	struct max1027_state *st = iio_priv(indio_dev);
379*fc167f62SPhilippe Reynes 
380*fc167f62SPhilippe Reynes 	pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
381*fc167f62SPhilippe Reynes 
382*fc167f62SPhilippe Reynes 	/* fill buffer with all channel */
383*fc167f62SPhilippe Reynes 	spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
384*fc167f62SPhilippe Reynes 
385*fc167f62SPhilippe Reynes 	iio_push_to_buffers(indio_dev, st->buffer);
386*fc167f62SPhilippe Reynes 
387*fc167f62SPhilippe Reynes 	iio_trigger_notify_done(indio_dev->trig);
388*fc167f62SPhilippe Reynes 
389*fc167f62SPhilippe Reynes 	return IRQ_HANDLED;
390*fc167f62SPhilippe Reynes }
391*fc167f62SPhilippe Reynes 
392*fc167f62SPhilippe Reynes static const struct iio_trigger_ops max1027_trigger_ops = {
393*fc167f62SPhilippe Reynes 	.owner = THIS_MODULE,
394*fc167f62SPhilippe Reynes 	.validate_device = &max1027_validate_device,
395*fc167f62SPhilippe Reynes 	.set_trigger_state = &max1027_set_trigger_state,
396*fc167f62SPhilippe Reynes };
397*fc167f62SPhilippe Reynes 
398*fc167f62SPhilippe Reynes static const struct iio_info max1027_info = {
399*fc167f62SPhilippe Reynes 	.driver_module = THIS_MODULE,
400*fc167f62SPhilippe Reynes 	.read_raw = &max1027_read_raw,
401*fc167f62SPhilippe Reynes 	.validate_trigger = &max1027_validate_trigger,
402*fc167f62SPhilippe Reynes 	.debugfs_reg_access = &max1027_debugfs_reg_access,
403*fc167f62SPhilippe Reynes };
404*fc167f62SPhilippe Reynes 
405*fc167f62SPhilippe Reynes static int max1027_probe(struct spi_device *spi)
406*fc167f62SPhilippe Reynes {
407*fc167f62SPhilippe Reynes 	int ret;
408*fc167f62SPhilippe Reynes 	struct iio_dev *indio_dev;
409*fc167f62SPhilippe Reynes 	struct max1027_state *st;
410*fc167f62SPhilippe Reynes 
411*fc167f62SPhilippe Reynes 	pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
412*fc167f62SPhilippe Reynes 
413*fc167f62SPhilippe Reynes 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
414*fc167f62SPhilippe Reynes 	if (indio_dev == NULL) {
415*fc167f62SPhilippe Reynes 		pr_err("Can't allocate iio device\n");
416*fc167f62SPhilippe Reynes 		return -ENOMEM;
417*fc167f62SPhilippe Reynes 	}
418*fc167f62SPhilippe Reynes 
419*fc167f62SPhilippe Reynes 	spi_set_drvdata(spi, indio_dev);
420*fc167f62SPhilippe Reynes 
421*fc167f62SPhilippe Reynes 	st = iio_priv(indio_dev);
422*fc167f62SPhilippe Reynes 	st->spi = spi;
423*fc167f62SPhilippe Reynes 	st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
424*fc167f62SPhilippe Reynes 
425*fc167f62SPhilippe Reynes 	mutex_init(&st->lock);
426*fc167f62SPhilippe Reynes 
427*fc167f62SPhilippe Reynes 	indio_dev->name = spi_get_device_id(spi)->name;
428*fc167f62SPhilippe Reynes 	indio_dev->dev.parent = &spi->dev;
429*fc167f62SPhilippe Reynes 	indio_dev->info = &max1027_info;
430*fc167f62SPhilippe Reynes 	indio_dev->modes = INDIO_DIRECT_MODE;
431*fc167f62SPhilippe Reynes 	indio_dev->channels = st->info->channels;
432*fc167f62SPhilippe Reynes 	indio_dev->num_channels = st->info->num_channels;
433*fc167f62SPhilippe Reynes 	indio_dev->available_scan_masks = st->info->available_scan_masks;
434*fc167f62SPhilippe Reynes 
435*fc167f62SPhilippe Reynes 	st->buffer = devm_kmalloc(&indio_dev->dev,
436*fc167f62SPhilippe Reynes 				  indio_dev->num_channels * 2,
437*fc167f62SPhilippe Reynes 				  GFP_KERNEL);
438*fc167f62SPhilippe Reynes 	if (st->buffer == NULL) {
439*fc167f62SPhilippe Reynes 		dev_err(&indio_dev->dev, "Can't allocate bufffer\n");
440*fc167f62SPhilippe Reynes 		return -ENOMEM;
441*fc167f62SPhilippe Reynes 	}
442*fc167f62SPhilippe Reynes 
443*fc167f62SPhilippe Reynes 	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
444*fc167f62SPhilippe Reynes 					 &max1027_trigger_handler, NULL);
445*fc167f62SPhilippe Reynes 	if (ret < 0) {
446*fc167f62SPhilippe Reynes 		dev_err(&indio_dev->dev, "Failed to setup buffer\n");
447*fc167f62SPhilippe Reynes 		return ret;
448*fc167f62SPhilippe Reynes 	}
449*fc167f62SPhilippe Reynes 
450*fc167f62SPhilippe Reynes 	st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
451*fc167f62SPhilippe Reynes 							indio_dev->name);
452*fc167f62SPhilippe Reynes 	if (st->trig == NULL) {
453*fc167f62SPhilippe Reynes 		ret = -ENOMEM;
454*fc167f62SPhilippe Reynes 		dev_err(&indio_dev->dev, "Failed to allocate iio trigger\n");
455*fc167f62SPhilippe Reynes 		goto fail_trigger_alloc;
456*fc167f62SPhilippe Reynes 	}
457*fc167f62SPhilippe Reynes 
458*fc167f62SPhilippe Reynes 	st->trig->ops = &max1027_trigger_ops;
459*fc167f62SPhilippe Reynes 	st->trig->dev.parent = &spi->dev;
460*fc167f62SPhilippe Reynes 	iio_trigger_set_drvdata(st->trig, indio_dev);
461*fc167f62SPhilippe Reynes 	iio_trigger_register(st->trig);
462*fc167f62SPhilippe Reynes 
463*fc167f62SPhilippe Reynes 	ret = devm_request_threaded_irq(&spi->dev, spi->irq,
464*fc167f62SPhilippe Reynes 					iio_trigger_generic_data_rdy_poll,
465*fc167f62SPhilippe Reynes 					NULL,
466*fc167f62SPhilippe Reynes 					IRQF_TRIGGER_FALLING,
467*fc167f62SPhilippe Reynes 					spi->dev.driver->name, st->trig);
468*fc167f62SPhilippe Reynes 	if (ret < 0) {
469*fc167f62SPhilippe Reynes 		dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
470*fc167f62SPhilippe Reynes 		goto fail_dev_register;
471*fc167f62SPhilippe Reynes 	}
472*fc167f62SPhilippe Reynes 
473*fc167f62SPhilippe Reynes 	/* Disable averaging */
474*fc167f62SPhilippe Reynes 	st->reg = MAX1027_AVG_REG;
475*fc167f62SPhilippe Reynes 	ret = spi_write(st->spi, &st->reg, 1);
476*fc167f62SPhilippe Reynes 	if (ret < 0) {
477*fc167f62SPhilippe Reynes 		dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
478*fc167f62SPhilippe Reynes 		goto fail_dev_register;
479*fc167f62SPhilippe Reynes 	}
480*fc167f62SPhilippe Reynes 
481*fc167f62SPhilippe Reynes 	ret = iio_device_register(indio_dev);
482*fc167f62SPhilippe Reynes 	if (ret < 0) {
483*fc167f62SPhilippe Reynes 		dev_err(&indio_dev->dev, "Failed to register iio device\n");
484*fc167f62SPhilippe Reynes 		goto fail_dev_register;
485*fc167f62SPhilippe Reynes 	}
486*fc167f62SPhilippe Reynes 
487*fc167f62SPhilippe Reynes 	return 0;
488*fc167f62SPhilippe Reynes 
489*fc167f62SPhilippe Reynes fail_dev_register:
490*fc167f62SPhilippe Reynes fail_trigger_alloc:
491*fc167f62SPhilippe Reynes 	iio_triggered_buffer_cleanup(indio_dev);
492*fc167f62SPhilippe Reynes 
493*fc167f62SPhilippe Reynes 	return ret;
494*fc167f62SPhilippe Reynes }
495*fc167f62SPhilippe Reynes 
496*fc167f62SPhilippe Reynes static int max1027_remove(struct spi_device *spi)
497*fc167f62SPhilippe Reynes {
498*fc167f62SPhilippe Reynes 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
499*fc167f62SPhilippe Reynes 
500*fc167f62SPhilippe Reynes 	pr_debug("%s: remove(spi = 0x%p)\n", __func__, spi);
501*fc167f62SPhilippe Reynes 
502*fc167f62SPhilippe Reynes 	iio_device_unregister(indio_dev);
503*fc167f62SPhilippe Reynes 	iio_triggered_buffer_cleanup(indio_dev);
504*fc167f62SPhilippe Reynes 
505*fc167f62SPhilippe Reynes 	return 0;
506*fc167f62SPhilippe Reynes }
507*fc167f62SPhilippe Reynes 
508*fc167f62SPhilippe Reynes static struct spi_driver max1027_driver = {
509*fc167f62SPhilippe Reynes 	.driver = {
510*fc167f62SPhilippe Reynes 		.name	= "max1027",
511*fc167f62SPhilippe Reynes 		.owner	= THIS_MODULE,
512*fc167f62SPhilippe Reynes 	},
513*fc167f62SPhilippe Reynes 	.probe		= max1027_probe,
514*fc167f62SPhilippe Reynes 	.remove		= max1027_remove,
515*fc167f62SPhilippe Reynes 	.id_table	= max1027_id,
516*fc167f62SPhilippe Reynes };
517*fc167f62SPhilippe Reynes module_spi_driver(max1027_driver);
518*fc167f62SPhilippe Reynes 
519*fc167f62SPhilippe Reynes MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
520*fc167f62SPhilippe Reynes MODULE_DESCRIPTION("MAX1027/MAX1029/MAX1031 ADC");
521*fc167f62SPhilippe Reynes MODULE_LICENSE("GPL v2");
522