1fc167f62SPhilippe Reynes /* 2fc167f62SPhilippe Reynes * iio/adc/max1027.c 3fc167f62SPhilippe Reynes * Copyright (C) 2014 Philippe Reynes 4fc167f62SPhilippe Reynes * 5fc167f62SPhilippe Reynes * based on linux/drivers/iio/ad7923.c 6fc167f62SPhilippe Reynes * Copyright 2011 Analog Devices Inc (from AD7923 Driver) 7fc167f62SPhilippe Reynes * Copyright 2012 CS Systemes d'Information 8fc167f62SPhilippe Reynes * 9fc167f62SPhilippe Reynes * This program is free software; you can redistribute it and/or modify 10fc167f62SPhilippe Reynes * it under the terms of the GNU General Public License version 2 as 11fc167f62SPhilippe Reynes * published by the Free Software Foundation. 12fc167f62SPhilippe Reynes * 13fc167f62SPhilippe Reynes * max1027.c 14fc167f62SPhilippe Reynes * 15fc167f62SPhilippe Reynes * Partial support for max1027 and similar chips. 16fc167f62SPhilippe Reynes */ 17fc167f62SPhilippe Reynes 18fc167f62SPhilippe Reynes #include <linux/kernel.h> 19fc167f62SPhilippe Reynes #include <linux/module.h> 20fc167f62SPhilippe Reynes #include <linux/spi/spi.h> 21fc167f62SPhilippe Reynes #include <linux/delay.h> 22fc167f62SPhilippe Reynes 23fc167f62SPhilippe Reynes #include <linux/iio/iio.h> 24fc167f62SPhilippe Reynes #include <linux/iio/buffer.h> 25fc167f62SPhilippe Reynes #include <linux/iio/trigger.h> 26fc167f62SPhilippe Reynes #include <linux/iio/trigger_consumer.h> 27fc167f62SPhilippe Reynes #include <linux/iio/triggered_buffer.h> 28fc167f62SPhilippe Reynes 29fc167f62SPhilippe Reynes #define MAX1027_CONV_REG BIT(7) 30fc167f62SPhilippe Reynes #define MAX1027_SETUP_REG BIT(6) 31fc167f62SPhilippe Reynes #define MAX1027_AVG_REG BIT(5) 32fc167f62SPhilippe Reynes #define MAX1027_RST_REG BIT(4) 33fc167f62SPhilippe Reynes 34fc167f62SPhilippe Reynes /* conversion register */ 35fc167f62SPhilippe Reynes #define MAX1027_TEMP BIT(0) 36fc167f62SPhilippe Reynes #define MAX1027_SCAN_0_N (0x00 << 1) 37fc167f62SPhilippe Reynes #define MAX1027_SCAN_N_M (0x01 << 1) 38fc167f62SPhilippe Reynes #define MAX1027_SCAN_N (0x02 << 1) 39fc167f62SPhilippe Reynes #define MAX1027_NOSCAN (0x03 << 1) 40fc167f62SPhilippe Reynes #define MAX1027_CHAN(n) ((n) << 3) 41fc167f62SPhilippe Reynes 42fc167f62SPhilippe Reynes /* setup register */ 43fc167f62SPhilippe Reynes #define MAX1027_UNIPOLAR 0x02 44fc167f62SPhilippe Reynes #define MAX1027_BIPOLAR 0x03 45fc167f62SPhilippe Reynes #define MAX1027_REF_MODE0 (0x00 << 2) 46fc167f62SPhilippe Reynes #define MAX1027_REF_MODE1 (0x01 << 2) 47fc167f62SPhilippe Reynes #define MAX1027_REF_MODE2 (0x02 << 2) 48fc167f62SPhilippe Reynes #define MAX1027_REF_MODE3 (0x03 << 2) 49fc167f62SPhilippe Reynes #define MAX1027_CKS_MODE0 (0x00 << 4) 50fc167f62SPhilippe Reynes #define MAX1027_CKS_MODE1 (0x01 << 4) 51fc167f62SPhilippe Reynes #define MAX1027_CKS_MODE2 (0x02 << 4) 52fc167f62SPhilippe Reynes #define MAX1027_CKS_MODE3 (0x03 << 4) 53fc167f62SPhilippe Reynes 54fc167f62SPhilippe Reynes /* averaging register */ 55fc167f62SPhilippe Reynes #define MAX1027_NSCAN_4 0x00 56fc167f62SPhilippe Reynes #define MAX1027_NSCAN_8 0x01 57fc167f62SPhilippe Reynes #define MAX1027_NSCAN_12 0x02 58fc167f62SPhilippe Reynes #define MAX1027_NSCAN_16 0x03 59fc167f62SPhilippe Reynes #define MAX1027_NAVG_4 (0x00 << 2) 60fc167f62SPhilippe Reynes #define MAX1027_NAVG_8 (0x01 << 2) 61fc167f62SPhilippe Reynes #define MAX1027_NAVG_16 (0x02 << 2) 62fc167f62SPhilippe Reynes #define MAX1027_NAVG_32 (0x03 << 2) 63fc167f62SPhilippe Reynes #define MAX1027_AVG_EN BIT(4) 64fc167f62SPhilippe Reynes 65fc167f62SPhilippe Reynes enum max1027_id { 66fc167f62SPhilippe Reynes max1027, 67fc167f62SPhilippe Reynes max1029, 68fc167f62SPhilippe Reynes max1031, 69fc167f62SPhilippe Reynes }; 70fc167f62SPhilippe Reynes 71fc167f62SPhilippe Reynes static const struct spi_device_id max1027_id[] = { 72fc167f62SPhilippe Reynes {"max1027", max1027}, 73fc167f62SPhilippe Reynes {"max1029", max1029}, 74fc167f62SPhilippe Reynes {"max1031", max1031}, 75fc167f62SPhilippe Reynes {} 76fc167f62SPhilippe Reynes }; 77fc167f62SPhilippe Reynes MODULE_DEVICE_TABLE(spi, max1027_id); 78fc167f62SPhilippe Reynes 79fc167f62SPhilippe Reynes #ifdef CONFIG_OF 80fc167f62SPhilippe Reynes static const struct of_device_id max1027_adc_dt_ids[] = { 81fc167f62SPhilippe Reynes { .compatible = "maxim,max1027" }, 82fc167f62SPhilippe Reynes { .compatible = "maxim,max1029" }, 83fc167f62SPhilippe Reynes { .compatible = "maxim,max1031" }, 84fc167f62SPhilippe Reynes {}, 85fc167f62SPhilippe Reynes }; 86fc167f62SPhilippe Reynes MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids); 87fc167f62SPhilippe Reynes #endif 88fc167f62SPhilippe Reynes 89fc167f62SPhilippe Reynes #define MAX1027_V_CHAN(index) \ 90fc167f62SPhilippe Reynes { \ 91fc167f62SPhilippe Reynes .type = IIO_VOLTAGE, \ 92fc167f62SPhilippe Reynes .indexed = 1, \ 93fc167f62SPhilippe Reynes .channel = index, \ 94fc167f62SPhilippe Reynes .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 95fc167f62SPhilippe Reynes .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 96fc167f62SPhilippe Reynes .scan_index = index + 1, \ 97fc167f62SPhilippe Reynes .scan_type = { \ 98fc167f62SPhilippe Reynes .sign = 'u', \ 99fc167f62SPhilippe Reynes .realbits = 10, \ 100fc167f62SPhilippe Reynes .storagebits = 16, \ 101fc167f62SPhilippe Reynes .shift = 2, \ 102fc167f62SPhilippe Reynes .endianness = IIO_BE, \ 103fc167f62SPhilippe Reynes }, \ 104fc167f62SPhilippe Reynes } 105fc167f62SPhilippe Reynes 106fc167f62SPhilippe Reynes #define MAX1027_T_CHAN \ 107fc167f62SPhilippe Reynes { \ 108fc167f62SPhilippe Reynes .type = IIO_TEMP, \ 109fc167f62SPhilippe Reynes .channel = 0, \ 110fc167f62SPhilippe Reynes .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 111fc167f62SPhilippe Reynes .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 112fc167f62SPhilippe Reynes .scan_index = 0, \ 113fc167f62SPhilippe Reynes .scan_type = { \ 114fc167f62SPhilippe Reynes .sign = 'u', \ 115fc167f62SPhilippe Reynes .realbits = 12, \ 116fc167f62SPhilippe Reynes .storagebits = 16, \ 117fc167f62SPhilippe Reynes .endianness = IIO_BE, \ 118fc167f62SPhilippe Reynes }, \ 119fc167f62SPhilippe Reynes } 120fc167f62SPhilippe Reynes 121fc167f62SPhilippe Reynes static const struct iio_chan_spec max1027_channels[] = { 122fc167f62SPhilippe Reynes MAX1027_T_CHAN, 123fc167f62SPhilippe Reynes MAX1027_V_CHAN(0), 124fc167f62SPhilippe Reynes MAX1027_V_CHAN(1), 125fc167f62SPhilippe Reynes MAX1027_V_CHAN(2), 126fc167f62SPhilippe Reynes MAX1027_V_CHAN(3), 127fc167f62SPhilippe Reynes MAX1027_V_CHAN(4), 128fc167f62SPhilippe Reynes MAX1027_V_CHAN(5), 129fc167f62SPhilippe Reynes MAX1027_V_CHAN(6), 130fc167f62SPhilippe Reynes MAX1027_V_CHAN(7) 131fc167f62SPhilippe Reynes }; 132fc167f62SPhilippe Reynes 133fc167f62SPhilippe Reynes static const struct iio_chan_spec max1029_channels[] = { 134fc167f62SPhilippe Reynes MAX1027_T_CHAN, 135fc167f62SPhilippe Reynes MAX1027_V_CHAN(0), 136fc167f62SPhilippe Reynes MAX1027_V_CHAN(1), 137fc167f62SPhilippe Reynes MAX1027_V_CHAN(2), 138fc167f62SPhilippe Reynes MAX1027_V_CHAN(3), 139fc167f62SPhilippe Reynes MAX1027_V_CHAN(4), 140fc167f62SPhilippe Reynes MAX1027_V_CHAN(5), 141fc167f62SPhilippe Reynes MAX1027_V_CHAN(6), 142fc167f62SPhilippe Reynes MAX1027_V_CHAN(7), 143fc167f62SPhilippe Reynes MAX1027_V_CHAN(8), 144fc167f62SPhilippe Reynes MAX1027_V_CHAN(9), 145fc167f62SPhilippe Reynes MAX1027_V_CHAN(10), 146fc167f62SPhilippe Reynes MAX1027_V_CHAN(11) 147fc167f62SPhilippe Reynes }; 148fc167f62SPhilippe Reynes 149fc167f62SPhilippe Reynes static const struct iio_chan_spec max1031_channels[] = { 150fc167f62SPhilippe Reynes MAX1027_T_CHAN, 151fc167f62SPhilippe Reynes MAX1027_V_CHAN(0), 152fc167f62SPhilippe Reynes MAX1027_V_CHAN(1), 153fc167f62SPhilippe Reynes MAX1027_V_CHAN(2), 154fc167f62SPhilippe Reynes MAX1027_V_CHAN(3), 155fc167f62SPhilippe Reynes MAX1027_V_CHAN(4), 156fc167f62SPhilippe Reynes MAX1027_V_CHAN(5), 157fc167f62SPhilippe Reynes MAX1027_V_CHAN(6), 158fc167f62SPhilippe Reynes MAX1027_V_CHAN(7), 159fc167f62SPhilippe Reynes MAX1027_V_CHAN(8), 160fc167f62SPhilippe Reynes MAX1027_V_CHAN(9), 161fc167f62SPhilippe Reynes MAX1027_V_CHAN(10), 162fc167f62SPhilippe Reynes MAX1027_V_CHAN(11), 163fc167f62SPhilippe Reynes MAX1027_V_CHAN(12), 164fc167f62SPhilippe Reynes MAX1027_V_CHAN(13), 165fc167f62SPhilippe Reynes MAX1027_V_CHAN(14), 166fc167f62SPhilippe Reynes MAX1027_V_CHAN(15) 167fc167f62SPhilippe Reynes }; 168fc167f62SPhilippe Reynes 169fc167f62SPhilippe Reynes static const unsigned long max1027_available_scan_masks[] = { 170fc167f62SPhilippe Reynes 0x000001ff, 171fc167f62SPhilippe Reynes 0x00000000, 172fc167f62SPhilippe Reynes }; 173fc167f62SPhilippe Reynes 174fc167f62SPhilippe Reynes static const unsigned long max1029_available_scan_masks[] = { 175fc167f62SPhilippe Reynes 0x00001fff, 176fc167f62SPhilippe Reynes 0x00000000, 177fc167f62SPhilippe Reynes }; 178fc167f62SPhilippe Reynes 179fc167f62SPhilippe Reynes static const unsigned long max1031_available_scan_masks[] = { 180fc167f62SPhilippe Reynes 0x0001ffff, 181fc167f62SPhilippe Reynes 0x00000000, 182fc167f62SPhilippe Reynes }; 183fc167f62SPhilippe Reynes 184fc167f62SPhilippe Reynes struct max1027_chip_info { 185fc167f62SPhilippe Reynes const struct iio_chan_spec *channels; 186fc167f62SPhilippe Reynes unsigned int num_channels; 187fc167f62SPhilippe Reynes const unsigned long *available_scan_masks; 188fc167f62SPhilippe Reynes }; 189fc167f62SPhilippe Reynes 190fc167f62SPhilippe Reynes static const struct max1027_chip_info max1027_chip_info_tbl[] = { 191fc167f62SPhilippe Reynes [max1027] = { 192fc167f62SPhilippe Reynes .channels = max1027_channels, 193fc167f62SPhilippe Reynes .num_channels = ARRAY_SIZE(max1027_channels), 194fc167f62SPhilippe Reynes .available_scan_masks = max1027_available_scan_masks, 195fc167f62SPhilippe Reynes }, 196fc167f62SPhilippe Reynes [max1029] = { 197fc167f62SPhilippe Reynes .channels = max1029_channels, 198fc167f62SPhilippe Reynes .num_channels = ARRAY_SIZE(max1029_channels), 199fc167f62SPhilippe Reynes .available_scan_masks = max1029_available_scan_masks, 200fc167f62SPhilippe Reynes }, 201fc167f62SPhilippe Reynes [max1031] = { 202fc167f62SPhilippe Reynes .channels = max1031_channels, 203fc167f62SPhilippe Reynes .num_channels = ARRAY_SIZE(max1031_channels), 204fc167f62SPhilippe Reynes .available_scan_masks = max1031_available_scan_masks, 205fc167f62SPhilippe Reynes }, 206fc167f62SPhilippe Reynes }; 207fc167f62SPhilippe Reynes 208fc167f62SPhilippe Reynes struct max1027_state { 209fc167f62SPhilippe Reynes const struct max1027_chip_info *info; 210fc167f62SPhilippe Reynes struct spi_device *spi; 211fc167f62SPhilippe Reynes struct iio_trigger *trig; 212fc167f62SPhilippe Reynes __be16 *buffer; 213fc167f62SPhilippe Reynes struct mutex lock; 214fc167f62SPhilippe Reynes 215fc167f62SPhilippe Reynes u8 reg ____cacheline_aligned; 216fc167f62SPhilippe Reynes }; 217fc167f62SPhilippe Reynes 218fc167f62SPhilippe Reynes static int max1027_read_single_value(struct iio_dev *indio_dev, 219fc167f62SPhilippe Reynes struct iio_chan_spec const *chan, 220fc167f62SPhilippe Reynes int *val) 221fc167f62SPhilippe Reynes { 222fc167f62SPhilippe Reynes int ret; 223fc167f62SPhilippe Reynes struct max1027_state *st = iio_priv(indio_dev); 224fc167f62SPhilippe Reynes 225fc167f62SPhilippe Reynes if (iio_buffer_enabled(indio_dev)) { 226fc167f62SPhilippe Reynes dev_warn(&indio_dev->dev, "trigger mode already enabled"); 227fc167f62SPhilippe Reynes return -EBUSY; 228fc167f62SPhilippe Reynes } 229fc167f62SPhilippe Reynes 230fc167f62SPhilippe Reynes /* Start acquisition on conversion register write */ 231fc167f62SPhilippe Reynes st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2; 232fc167f62SPhilippe Reynes ret = spi_write(st->spi, &st->reg, 1); 233fc167f62SPhilippe Reynes if (ret < 0) { 234fc167f62SPhilippe Reynes dev_err(&indio_dev->dev, 235fc167f62SPhilippe Reynes "Failed to configure setup register\n"); 236fc167f62SPhilippe Reynes return ret; 237fc167f62SPhilippe Reynes } 238fc167f62SPhilippe Reynes 239fc167f62SPhilippe Reynes /* Configure conversion register with the requested chan */ 240fc167f62SPhilippe Reynes st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) | 24158b90a8dSSandhya Bankar MAX1027_NOSCAN; 24258b90a8dSSandhya Bankar if (chan->type == IIO_TEMP) 24358b90a8dSSandhya Bankar st->reg |= MAX1027_TEMP; 244fc167f62SPhilippe Reynes ret = spi_write(st->spi, &st->reg, 1); 245fc167f62SPhilippe Reynes if (ret < 0) { 246fc167f62SPhilippe Reynes dev_err(&indio_dev->dev, 247fc167f62SPhilippe Reynes "Failed to configure conversion register\n"); 248fc167f62SPhilippe Reynes return ret; 249fc167f62SPhilippe Reynes } 250fc167f62SPhilippe Reynes 251fc167f62SPhilippe Reynes /* 252fc167f62SPhilippe Reynes * For an unknown reason, when we use the mode "10" (write 253fc167f62SPhilippe Reynes * conversion register), the interrupt doesn't occur every time. 254fc167f62SPhilippe Reynes * So we just wait 1 ms. 255fc167f62SPhilippe Reynes */ 256fc167f62SPhilippe Reynes mdelay(1); 257fc167f62SPhilippe Reynes 258fc167f62SPhilippe Reynes /* Read result */ 259fc167f62SPhilippe Reynes ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2); 260fc167f62SPhilippe Reynes if (ret < 0) 261fc167f62SPhilippe Reynes return ret; 262fc167f62SPhilippe Reynes 263fc167f62SPhilippe Reynes *val = be16_to_cpu(st->buffer[0]); 264fc167f62SPhilippe Reynes 265fc167f62SPhilippe Reynes return IIO_VAL_INT; 266fc167f62SPhilippe Reynes } 267fc167f62SPhilippe Reynes 268fc167f62SPhilippe Reynes static int max1027_read_raw(struct iio_dev *indio_dev, 269fc167f62SPhilippe Reynes struct iio_chan_spec const *chan, 270fc167f62SPhilippe Reynes int *val, int *val2, long mask) 271fc167f62SPhilippe Reynes { 272fc167f62SPhilippe Reynes int ret = 0; 273fc167f62SPhilippe Reynes struct max1027_state *st = iio_priv(indio_dev); 274fc167f62SPhilippe Reynes 275fc167f62SPhilippe Reynes mutex_lock(&st->lock); 276fc167f62SPhilippe Reynes 277fc167f62SPhilippe Reynes switch (mask) { 278fc167f62SPhilippe Reynes case IIO_CHAN_INFO_RAW: 279fc167f62SPhilippe Reynes ret = max1027_read_single_value(indio_dev, chan, val); 280fc167f62SPhilippe Reynes break; 281fc167f62SPhilippe Reynes case IIO_CHAN_INFO_SCALE: 282fc167f62SPhilippe Reynes switch (chan->type) { 283fc167f62SPhilippe Reynes case IIO_TEMP: 284fc167f62SPhilippe Reynes *val = 1; 285fc167f62SPhilippe Reynes *val2 = 8; 286fc167f62SPhilippe Reynes ret = IIO_VAL_FRACTIONAL; 287fc167f62SPhilippe Reynes break; 288fc167f62SPhilippe Reynes case IIO_VOLTAGE: 289fc167f62SPhilippe Reynes *val = 2500; 290fc167f62SPhilippe Reynes *val2 = 10; 291fc167f62SPhilippe Reynes ret = IIO_VAL_FRACTIONAL_LOG2; 292fc167f62SPhilippe Reynes break; 293fc167f62SPhilippe Reynes default: 294fc167f62SPhilippe Reynes ret = -EINVAL; 295fc167f62SPhilippe Reynes break; 296fc167f62SPhilippe Reynes } 297fc167f62SPhilippe Reynes break; 298fc167f62SPhilippe Reynes default: 299fc167f62SPhilippe Reynes ret = -EINVAL; 300fc167f62SPhilippe Reynes break; 301fc167f62SPhilippe Reynes } 302fc167f62SPhilippe Reynes 303fc167f62SPhilippe Reynes mutex_unlock(&st->lock); 304fc167f62SPhilippe Reynes 305fc167f62SPhilippe Reynes return ret; 306fc167f62SPhilippe Reynes } 307fc167f62SPhilippe Reynes 308fc167f62SPhilippe Reynes static int max1027_debugfs_reg_access(struct iio_dev *indio_dev, 309fc167f62SPhilippe Reynes unsigned reg, unsigned writeval, 310fc167f62SPhilippe Reynes unsigned *readval) 311fc167f62SPhilippe Reynes { 312fc167f62SPhilippe Reynes struct max1027_state *st = iio_priv(indio_dev); 313fc167f62SPhilippe Reynes u8 *val = (u8 *)st->buffer; 314fc167f62SPhilippe Reynes 315fc167f62SPhilippe Reynes if (readval != NULL) 316fc167f62SPhilippe Reynes return -EINVAL; 317fc167f62SPhilippe Reynes 318fc167f62SPhilippe Reynes *val = (u8)writeval; 319fc167f62SPhilippe Reynes return spi_write(st->spi, val, 1); 320fc167f62SPhilippe Reynes } 321fc167f62SPhilippe Reynes 322fc167f62SPhilippe Reynes static int max1027_validate_trigger(struct iio_dev *indio_dev, 323fc167f62SPhilippe Reynes struct iio_trigger *trig) 324fc167f62SPhilippe Reynes { 325fc167f62SPhilippe Reynes struct max1027_state *st = iio_priv(indio_dev); 326fc167f62SPhilippe Reynes 327fc167f62SPhilippe Reynes if (st->trig != trig) 328fc167f62SPhilippe Reynes return -EINVAL; 329fc167f62SPhilippe Reynes 330fc167f62SPhilippe Reynes return 0; 331fc167f62SPhilippe Reynes } 332fc167f62SPhilippe Reynes 333fc167f62SPhilippe Reynes static int max1027_set_trigger_state(struct iio_trigger *trig, bool state) 334fc167f62SPhilippe Reynes { 335fc167f62SPhilippe Reynes struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 336fc167f62SPhilippe Reynes struct max1027_state *st = iio_priv(indio_dev); 337fc167f62SPhilippe Reynes int ret; 338fc167f62SPhilippe Reynes 339fc167f62SPhilippe Reynes if (state) { 340fc167f62SPhilippe Reynes /* Start acquisition on cnvst */ 341fc167f62SPhilippe Reynes st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 | 342fc167f62SPhilippe Reynes MAX1027_REF_MODE2; 343fc167f62SPhilippe Reynes ret = spi_write(st->spi, &st->reg, 1); 344fc167f62SPhilippe Reynes if (ret < 0) 345fc167f62SPhilippe Reynes return ret; 346fc167f62SPhilippe Reynes 347fc167f62SPhilippe Reynes /* Scan from 0 to max */ 348fc167f62SPhilippe Reynes st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) | 349fc167f62SPhilippe Reynes MAX1027_SCAN_N_M | MAX1027_TEMP; 350fc167f62SPhilippe Reynes ret = spi_write(st->spi, &st->reg, 1); 351fc167f62SPhilippe Reynes if (ret < 0) 352fc167f62SPhilippe Reynes return ret; 353fc167f62SPhilippe Reynes } else { 354fc167f62SPhilippe Reynes /* Start acquisition on conversion register write */ 355fc167f62SPhilippe Reynes st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 | 356fc167f62SPhilippe Reynes MAX1027_REF_MODE2; 357fc167f62SPhilippe Reynes ret = spi_write(st->spi, &st->reg, 1); 358fc167f62SPhilippe Reynes if (ret < 0) 359fc167f62SPhilippe Reynes return ret; 360fc167f62SPhilippe Reynes } 361fc167f62SPhilippe Reynes 362fc167f62SPhilippe Reynes return 0; 363fc167f62SPhilippe Reynes } 364fc167f62SPhilippe Reynes 365fc167f62SPhilippe Reynes static irqreturn_t max1027_trigger_handler(int irq, void *private) 366fc167f62SPhilippe Reynes { 3670b568b3cSsimran singhal struct iio_poll_func *pf = private; 368fc167f62SPhilippe Reynes struct iio_dev *indio_dev = pf->indio_dev; 369fc167f62SPhilippe Reynes struct max1027_state *st = iio_priv(indio_dev); 370fc167f62SPhilippe Reynes 371fc167f62SPhilippe Reynes pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private); 372fc167f62SPhilippe Reynes 373fc167f62SPhilippe Reynes /* fill buffer with all channel */ 374fc167f62SPhilippe Reynes spi_read(st->spi, st->buffer, indio_dev->masklength * 2); 375fc167f62SPhilippe Reynes 376fc167f62SPhilippe Reynes iio_push_to_buffers(indio_dev, st->buffer); 377fc167f62SPhilippe Reynes 378fc167f62SPhilippe Reynes iio_trigger_notify_done(indio_dev->trig); 379fc167f62SPhilippe Reynes 380fc167f62SPhilippe Reynes return IRQ_HANDLED; 381fc167f62SPhilippe Reynes } 382fc167f62SPhilippe Reynes 383fc167f62SPhilippe Reynes static const struct iio_trigger_ops max1027_trigger_ops = { 384bea15d51SLars-Peter Clausen .validate_device = &iio_trigger_validate_own_device, 385fc167f62SPhilippe Reynes .set_trigger_state = &max1027_set_trigger_state, 386fc167f62SPhilippe Reynes }; 387fc167f62SPhilippe Reynes 388fc167f62SPhilippe Reynes static const struct iio_info max1027_info = { 389fc167f62SPhilippe Reynes .read_raw = &max1027_read_raw, 390fc167f62SPhilippe Reynes .validate_trigger = &max1027_validate_trigger, 391fc167f62SPhilippe Reynes .debugfs_reg_access = &max1027_debugfs_reg_access, 392fc167f62SPhilippe Reynes }; 393fc167f62SPhilippe Reynes 394fc167f62SPhilippe Reynes static int max1027_probe(struct spi_device *spi) 395fc167f62SPhilippe Reynes { 396fc167f62SPhilippe Reynes int ret; 397fc167f62SPhilippe Reynes struct iio_dev *indio_dev; 398fc167f62SPhilippe Reynes struct max1027_state *st; 399fc167f62SPhilippe Reynes 400fc167f62SPhilippe Reynes pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi); 401fc167f62SPhilippe Reynes 402fc167f62SPhilippe Reynes indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 403fc167f62SPhilippe Reynes if (indio_dev == NULL) { 404fc167f62SPhilippe Reynes pr_err("Can't allocate iio device\n"); 405fc167f62SPhilippe Reynes return -ENOMEM; 406fc167f62SPhilippe Reynes } 407fc167f62SPhilippe Reynes 408fc167f62SPhilippe Reynes spi_set_drvdata(spi, indio_dev); 409fc167f62SPhilippe Reynes 410fc167f62SPhilippe Reynes st = iio_priv(indio_dev); 411fc167f62SPhilippe Reynes st->spi = spi; 412fc167f62SPhilippe Reynes st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data]; 413fc167f62SPhilippe Reynes 414fc167f62SPhilippe Reynes mutex_init(&st->lock); 415fc167f62SPhilippe Reynes 416fc167f62SPhilippe Reynes indio_dev->name = spi_get_device_id(spi)->name; 417fc167f62SPhilippe Reynes indio_dev->dev.parent = &spi->dev; 418b541eaffSMatt Ranostay indio_dev->dev.of_node = spi->dev.of_node; 419fc167f62SPhilippe Reynes indio_dev->info = &max1027_info; 420fc167f62SPhilippe Reynes indio_dev->modes = INDIO_DIRECT_MODE; 421fc167f62SPhilippe Reynes indio_dev->channels = st->info->channels; 422fc167f62SPhilippe Reynes indio_dev->num_channels = st->info->num_channels; 423fc167f62SPhilippe Reynes indio_dev->available_scan_masks = st->info->available_scan_masks; 424fc167f62SPhilippe Reynes 425*3c4211baSKees Cook st->buffer = devm_kmalloc_array(&indio_dev->dev, 426*3c4211baSKees Cook indio_dev->num_channels, 2, 427fc167f62SPhilippe Reynes GFP_KERNEL); 428fc167f62SPhilippe Reynes if (st->buffer == NULL) { 429d939be3aSMasanari Iida dev_err(&indio_dev->dev, "Can't allocate buffer\n"); 430fc167f62SPhilippe Reynes return -ENOMEM; 431fc167f62SPhilippe Reynes } 432fc167f62SPhilippe Reynes 433fc167f62SPhilippe Reynes ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, 434fc167f62SPhilippe Reynes &max1027_trigger_handler, NULL); 435fc167f62SPhilippe Reynes if (ret < 0) { 436fc167f62SPhilippe Reynes dev_err(&indio_dev->dev, "Failed to setup buffer\n"); 437fc167f62SPhilippe Reynes return ret; 438fc167f62SPhilippe Reynes } 439fc167f62SPhilippe Reynes 440fc167f62SPhilippe Reynes st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger", 441fc167f62SPhilippe Reynes indio_dev->name); 442fc167f62SPhilippe Reynes if (st->trig == NULL) { 443fc167f62SPhilippe Reynes ret = -ENOMEM; 444fc167f62SPhilippe Reynes dev_err(&indio_dev->dev, "Failed to allocate iio trigger\n"); 445fc167f62SPhilippe Reynes goto fail_trigger_alloc; 446fc167f62SPhilippe Reynes } 447fc167f62SPhilippe Reynes 448fc167f62SPhilippe Reynes st->trig->ops = &max1027_trigger_ops; 449fc167f62SPhilippe Reynes st->trig->dev.parent = &spi->dev; 450fc167f62SPhilippe Reynes iio_trigger_set_drvdata(st->trig, indio_dev); 451fc167f62SPhilippe Reynes iio_trigger_register(st->trig); 452fc167f62SPhilippe Reynes 453fc167f62SPhilippe Reynes ret = devm_request_threaded_irq(&spi->dev, spi->irq, 454fc167f62SPhilippe Reynes iio_trigger_generic_data_rdy_poll, 455fc167f62SPhilippe Reynes NULL, 456fc167f62SPhilippe Reynes IRQF_TRIGGER_FALLING, 457fc167f62SPhilippe Reynes spi->dev.driver->name, st->trig); 458fc167f62SPhilippe Reynes if (ret < 0) { 459fc167f62SPhilippe Reynes dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n"); 460fc167f62SPhilippe Reynes goto fail_dev_register; 461fc167f62SPhilippe Reynes } 462fc167f62SPhilippe Reynes 463fc167f62SPhilippe Reynes /* Disable averaging */ 464fc167f62SPhilippe Reynes st->reg = MAX1027_AVG_REG; 465fc167f62SPhilippe Reynes ret = spi_write(st->spi, &st->reg, 1); 466fc167f62SPhilippe Reynes if (ret < 0) { 467fc167f62SPhilippe Reynes dev_err(&indio_dev->dev, "Failed to configure averaging register\n"); 468fc167f62SPhilippe Reynes goto fail_dev_register; 469fc167f62SPhilippe Reynes } 470fc167f62SPhilippe Reynes 471fc167f62SPhilippe Reynes ret = iio_device_register(indio_dev); 472fc167f62SPhilippe Reynes if (ret < 0) { 473fc167f62SPhilippe Reynes dev_err(&indio_dev->dev, "Failed to register iio device\n"); 474fc167f62SPhilippe Reynes goto fail_dev_register; 475fc167f62SPhilippe Reynes } 476fc167f62SPhilippe Reynes 477fc167f62SPhilippe Reynes return 0; 478fc167f62SPhilippe Reynes 479fc167f62SPhilippe Reynes fail_dev_register: 480fc167f62SPhilippe Reynes fail_trigger_alloc: 481fc167f62SPhilippe Reynes iio_triggered_buffer_cleanup(indio_dev); 482fc167f62SPhilippe Reynes 483fc167f62SPhilippe Reynes return ret; 484fc167f62SPhilippe Reynes } 485fc167f62SPhilippe Reynes 486fc167f62SPhilippe Reynes static int max1027_remove(struct spi_device *spi) 487fc167f62SPhilippe Reynes { 488fc167f62SPhilippe Reynes struct iio_dev *indio_dev = spi_get_drvdata(spi); 489fc167f62SPhilippe Reynes 490fc167f62SPhilippe Reynes pr_debug("%s: remove(spi = 0x%p)\n", __func__, spi); 491fc167f62SPhilippe Reynes 492fc167f62SPhilippe Reynes iio_device_unregister(indio_dev); 493fc167f62SPhilippe Reynes iio_triggered_buffer_cleanup(indio_dev); 494fc167f62SPhilippe Reynes 495fc167f62SPhilippe Reynes return 0; 496fc167f62SPhilippe Reynes } 497fc167f62SPhilippe Reynes 498fc167f62SPhilippe Reynes static struct spi_driver max1027_driver = { 499fc167f62SPhilippe Reynes .driver = { 500fc167f62SPhilippe Reynes .name = "max1027", 501d1b895feSJavier Martinez Canillas .of_match_table = of_match_ptr(max1027_adc_dt_ids), 502fc167f62SPhilippe Reynes }, 503fc167f62SPhilippe Reynes .probe = max1027_probe, 504fc167f62SPhilippe Reynes .remove = max1027_remove, 505fc167f62SPhilippe Reynes .id_table = max1027_id, 506fc167f62SPhilippe Reynes }; 507fc167f62SPhilippe Reynes module_spi_driver(max1027_driver); 508fc167f62SPhilippe Reynes 509fc167f62SPhilippe Reynes MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>"); 510fc167f62SPhilippe Reynes MODULE_DESCRIPTION("MAX1027/MAX1029/MAX1031 ADC"); 511fc167f62SPhilippe Reynes MODULE_LICENSE("GPL v2"); 512