1 /* 2 * INA2XX Current and Power Monitors 3 * 4 * Copyright 2015 Baylibre SAS. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Based on linux/drivers/iio/adc/ad7291.c 11 * Copyright 2010-2011 Analog Devices Inc. 12 * 13 * Based on linux/drivers/hwmon/ina2xx.c 14 * Copyright 2012 Lothar Felten <l-felten@ti.com> 15 * 16 * Licensed under the GPL-2 or later. 17 * 18 * IIO driver for INA219-220-226-230-231 19 * 20 * Configurable 7-bit I2C slave address from 0x40 to 0x4F 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/i2c.h> 25 #include <linux/iio/kfifo_buf.h> 26 #include <linux/iio/sysfs.h> 27 #include <linux/kthread.h> 28 #include <linux/module.h> 29 #include <linux/regmap.h> 30 #include <linux/util_macros.h> 31 32 #include <linux/platform_data/ina2xx.h> 33 34 /* INA2XX registers definition */ 35 #define INA2XX_CONFIG 0x00 36 #define INA2XX_SHUNT_VOLTAGE 0x01 /* readonly */ 37 #define INA2XX_BUS_VOLTAGE 0x02 /* readonly */ 38 #define INA2XX_POWER 0x03 /* readonly */ 39 #define INA2XX_CURRENT 0x04 /* readonly */ 40 #define INA2XX_CALIBRATION 0x05 41 42 #define INA226_ALERT_MASK GENMASK(2, 1) 43 #define INA266_CVRF BIT(3) 44 45 #define INA2XX_MAX_REGISTERS 8 46 47 /* settings - depend on use case */ 48 #define INA219_CONFIG_DEFAULT 0x399F /* PGA=8 */ 49 #define INA226_CONFIG_DEFAULT 0x4327 50 #define INA226_DEFAULT_AVG 4 51 #define INA226_DEFAULT_IT 1110 52 53 #define INA2XX_RSHUNT_DEFAULT 10000 54 55 /* 56 * bit mask for reading the averaging setting in the configuration register 57 * FIXME: use regmap_fields. 58 */ 59 #define INA2XX_MODE_MASK GENMASK(3, 0) 60 61 #define INA226_AVG_MASK GENMASK(11, 9) 62 #define INA226_SHIFT_AVG(val) ((val) << 9) 63 64 /* Integration time for VBus */ 65 #define INA226_ITB_MASK GENMASK(8, 6) 66 #define INA226_SHIFT_ITB(val) ((val) << 6) 67 68 /* Integration time for VShunt */ 69 #define INA226_ITS_MASK GENMASK(5, 3) 70 #define INA226_SHIFT_ITS(val) ((val) << 3) 71 72 /* Cosmetic macro giving the sampling period for a full P=UxI cycle */ 73 #define SAMPLING_PERIOD(c) ((c->int_time_vbus + c->int_time_vshunt) \ 74 * c->avg) 75 76 static bool ina2xx_is_writeable_reg(struct device *dev, unsigned int reg) 77 { 78 return (reg == INA2XX_CONFIG) || (reg > INA2XX_CURRENT); 79 } 80 81 static bool ina2xx_is_volatile_reg(struct device *dev, unsigned int reg) 82 { 83 return (reg != INA2XX_CONFIG); 84 } 85 86 static inline bool is_signed_reg(unsigned int reg) 87 { 88 return (reg == INA2XX_SHUNT_VOLTAGE) || (reg == INA2XX_CURRENT); 89 } 90 91 static const struct regmap_config ina2xx_regmap_config = { 92 .reg_bits = 8, 93 .val_bits = 16, 94 .max_register = INA2XX_MAX_REGISTERS, 95 .writeable_reg = ina2xx_is_writeable_reg, 96 .volatile_reg = ina2xx_is_volatile_reg, 97 }; 98 99 enum ina2xx_ids { ina219, ina226 }; 100 101 struct ina2xx_config { 102 u16 config_default; 103 int calibration_factor; 104 int shunt_div; 105 int bus_voltage_shift; 106 int bus_voltage_lsb; /* uV */ 107 int power_lsb; /* uW */ 108 }; 109 110 struct ina2xx_chip_info { 111 struct regmap *regmap; 112 struct task_struct *task; 113 const struct ina2xx_config *config; 114 struct mutex state_lock; 115 unsigned int shunt_resistor; 116 int avg; 117 s64 prev_ns; /* track buffer capture time, check for underruns */ 118 int int_time_vbus; /* Bus voltage integration time uS */ 119 int int_time_vshunt; /* Shunt voltage integration time uS */ 120 bool allow_async_readout; 121 }; 122 123 static const struct ina2xx_config ina2xx_config[] = { 124 [ina219] = { 125 .config_default = INA219_CONFIG_DEFAULT, 126 .calibration_factor = 40960000, 127 .shunt_div = 100, 128 .bus_voltage_shift = 3, 129 .bus_voltage_lsb = 4000, 130 .power_lsb = 20000, 131 }, 132 [ina226] = { 133 .config_default = INA226_CONFIG_DEFAULT, 134 .calibration_factor = 5120000, 135 .shunt_div = 400, 136 .bus_voltage_shift = 0, 137 .bus_voltage_lsb = 1250, 138 .power_lsb = 25000, 139 }, 140 }; 141 142 static int ina2xx_read_raw(struct iio_dev *indio_dev, 143 struct iio_chan_spec const *chan, 144 int *val, int *val2, long mask) 145 { 146 int ret; 147 struct ina2xx_chip_info *chip = iio_priv(indio_dev); 148 unsigned int regval; 149 150 switch (mask) { 151 case IIO_CHAN_INFO_RAW: 152 ret = regmap_read(chip->regmap, chan->address, ®val); 153 if (ret) 154 return ret; 155 156 if (is_signed_reg(chan->address)) 157 *val = (s16) regval; 158 else 159 *val = regval; 160 161 return IIO_VAL_INT; 162 163 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 164 *val = chip->avg; 165 return IIO_VAL_INT; 166 167 case IIO_CHAN_INFO_INT_TIME: 168 *val = 0; 169 if (chan->address == INA2XX_SHUNT_VOLTAGE) 170 *val2 = chip->int_time_vshunt; 171 else 172 *val2 = chip->int_time_vbus; 173 174 return IIO_VAL_INT_PLUS_MICRO; 175 176 case IIO_CHAN_INFO_SAMP_FREQ: 177 /* 178 * Sample freq is read only, it is a consequence of 179 * 1/AVG*(CT_bus+CT_shunt). 180 */ 181 *val = DIV_ROUND_CLOSEST(1000000, SAMPLING_PERIOD(chip)); 182 183 return IIO_VAL_INT; 184 185 case IIO_CHAN_INFO_SCALE: 186 switch (chan->address) { 187 case INA2XX_SHUNT_VOLTAGE: 188 /* processed (mV) = raw*1000/shunt_div */ 189 *val2 = chip->config->shunt_div; 190 *val = 1000; 191 return IIO_VAL_FRACTIONAL; 192 193 case INA2XX_BUS_VOLTAGE: 194 /* processed (mV) = raw*lsb (uV) / (1000 << shift) */ 195 *val = chip->config->bus_voltage_lsb; 196 *val2 = 1000 << chip->config->bus_voltage_shift; 197 return IIO_VAL_FRACTIONAL; 198 199 case INA2XX_POWER: 200 /* processed (mW) = raw*lsb (uW) / 1000 */ 201 *val = chip->config->power_lsb; 202 *val2 = 1000; 203 return IIO_VAL_FRACTIONAL; 204 205 case INA2XX_CURRENT: 206 /* processed (mA) = raw (mA) */ 207 *val = 1; 208 return IIO_VAL_INT; 209 } 210 } 211 212 return -EINVAL; 213 } 214 215 /* 216 * Available averaging rates for ina226. The indices correspond with 217 * the bit values expected by the chip (according to the ina226 datasheet, 218 * table 3 AVG bit settings, found at 219 * http://www.ti.com/lit/ds/symlink/ina226.pdf. 220 */ 221 static const int ina226_avg_tab[] = { 1, 4, 16, 64, 128, 256, 512, 1024 }; 222 223 static int ina226_set_average(struct ina2xx_chip_info *chip, unsigned int val, 224 unsigned int *config) 225 { 226 int bits; 227 228 if (val > 1024 || val < 1) 229 return -EINVAL; 230 231 bits = find_closest(val, ina226_avg_tab, 232 ARRAY_SIZE(ina226_avg_tab)); 233 234 chip->avg = ina226_avg_tab[bits]; 235 236 *config &= ~INA226_AVG_MASK; 237 *config |= INA226_SHIFT_AVG(bits) & INA226_AVG_MASK; 238 239 return 0; 240 } 241 242 /* Conversion times in uS */ 243 static const int ina226_conv_time_tab[] = { 140, 204, 332, 588, 1100, 244 2116, 4156, 8244 }; 245 246 static int ina226_set_int_time_vbus(struct ina2xx_chip_info *chip, 247 unsigned int val_us, unsigned int *config) 248 { 249 int bits; 250 251 if (val_us > 8244 || val_us < 140) 252 return -EINVAL; 253 254 bits = find_closest(val_us, ina226_conv_time_tab, 255 ARRAY_SIZE(ina226_conv_time_tab)); 256 257 chip->int_time_vbus = ina226_conv_time_tab[bits]; 258 259 *config &= ~INA226_ITB_MASK; 260 *config |= INA226_SHIFT_ITB(bits) & INA226_ITB_MASK; 261 262 return 0; 263 } 264 265 static int ina226_set_int_time_vshunt(struct ina2xx_chip_info *chip, 266 unsigned int val_us, unsigned int *config) 267 { 268 int bits; 269 270 if (val_us > 8244 || val_us < 140) 271 return -EINVAL; 272 273 bits = find_closest(val_us, ina226_conv_time_tab, 274 ARRAY_SIZE(ina226_conv_time_tab)); 275 276 chip->int_time_vshunt = ina226_conv_time_tab[bits]; 277 278 *config &= ~INA226_ITS_MASK; 279 *config |= INA226_SHIFT_ITS(bits) & INA226_ITS_MASK; 280 281 return 0; 282 } 283 284 static int ina2xx_write_raw(struct iio_dev *indio_dev, 285 struct iio_chan_spec const *chan, 286 int val, int val2, long mask) 287 { 288 struct ina2xx_chip_info *chip = iio_priv(indio_dev); 289 unsigned int config, tmp; 290 int ret; 291 292 if (iio_buffer_enabled(indio_dev)) 293 return -EBUSY; 294 295 mutex_lock(&chip->state_lock); 296 297 ret = regmap_read(chip->regmap, INA2XX_CONFIG, &config); 298 if (ret) 299 goto err; 300 301 tmp = config; 302 303 switch (mask) { 304 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 305 ret = ina226_set_average(chip, val, &tmp); 306 break; 307 308 case IIO_CHAN_INFO_INT_TIME: 309 if (chan->address == INA2XX_SHUNT_VOLTAGE) 310 ret = ina226_set_int_time_vshunt(chip, val2, &tmp); 311 else 312 ret = ina226_set_int_time_vbus(chip, val2, &tmp); 313 break; 314 315 default: 316 ret = -EINVAL; 317 } 318 319 if (!ret && (tmp != config)) 320 ret = regmap_write(chip->regmap, INA2XX_CONFIG, tmp); 321 err: 322 mutex_unlock(&chip->state_lock); 323 324 return ret; 325 } 326 327 static ssize_t ina2xx_allow_async_readout_show(struct device *dev, 328 struct device_attribute *attr, 329 char *buf) 330 { 331 struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); 332 333 return sprintf(buf, "%d\n", chip->allow_async_readout); 334 } 335 336 static ssize_t ina2xx_allow_async_readout_store(struct device *dev, 337 struct device_attribute *attr, 338 const char *buf, size_t len) 339 { 340 struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); 341 bool val; 342 int ret; 343 344 ret = strtobool((const char *) buf, &val); 345 if (ret) 346 return ret; 347 348 chip->allow_async_readout = val; 349 350 return len; 351 } 352 353 static int set_shunt_resistor(struct ina2xx_chip_info *chip, unsigned int val) 354 { 355 if (val <= 0 || val > chip->config->calibration_factor) 356 return -EINVAL; 357 358 chip->shunt_resistor = val; 359 360 return 0; 361 } 362 363 static ssize_t ina2xx_shunt_resistor_show(struct device *dev, 364 struct device_attribute *attr, 365 char *buf) 366 { 367 struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); 368 369 return sprintf(buf, "%d\n", chip->shunt_resistor); 370 } 371 372 static ssize_t ina2xx_shunt_resistor_store(struct device *dev, 373 struct device_attribute *attr, 374 const char *buf, size_t len) 375 { 376 struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev)); 377 unsigned long val; 378 int ret; 379 380 ret = kstrtoul((const char *) buf, 10, &val); 381 if (ret) 382 return ret; 383 384 ret = set_shunt_resistor(chip, val); 385 if (ret) 386 return ret; 387 388 return len; 389 } 390 391 #define INA2XX_CHAN(_type, _index, _address) { \ 392 .type = (_type), \ 393 .address = (_address), \ 394 .indexed = 1, \ 395 .channel = (_index), \ 396 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ 397 | BIT(IIO_CHAN_INFO_SCALE), \ 398 .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 399 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 400 .scan_index = (_index), \ 401 .scan_type = { \ 402 .sign = 'u', \ 403 .realbits = 16, \ 404 .storagebits = 16, \ 405 .endianness = IIO_CPU, \ 406 } \ 407 } 408 409 /* 410 * Sampling Freq is a consequence of the integration times of 411 * the Voltage channels. 412 */ 413 #define INA2XX_CHAN_VOLTAGE(_index, _address) { \ 414 .type = IIO_VOLTAGE, \ 415 .address = (_address), \ 416 .indexed = 1, \ 417 .channel = (_index), \ 418 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 419 BIT(IIO_CHAN_INFO_SCALE) | \ 420 BIT(IIO_CHAN_INFO_INT_TIME), \ 421 .scan_index = (_index), \ 422 .scan_type = { \ 423 .sign = 'u', \ 424 .realbits = 16, \ 425 .storagebits = 16, \ 426 .endianness = IIO_LE, \ 427 } \ 428 } 429 430 static const struct iio_chan_spec ina2xx_channels[] = { 431 INA2XX_CHAN_VOLTAGE(0, INA2XX_SHUNT_VOLTAGE), 432 INA2XX_CHAN_VOLTAGE(1, INA2XX_BUS_VOLTAGE), 433 INA2XX_CHAN(IIO_POWER, 2, INA2XX_POWER), 434 INA2XX_CHAN(IIO_CURRENT, 3, INA2XX_CURRENT), 435 IIO_CHAN_SOFT_TIMESTAMP(4), 436 }; 437 438 static int ina2xx_work_buffer(struct iio_dev *indio_dev) 439 { 440 struct ina2xx_chip_info *chip = iio_priv(indio_dev); 441 unsigned short data[8]; 442 int bit, ret, i = 0; 443 s64 time_a, time_b; 444 unsigned int alert; 445 446 time_a = iio_get_time_ns(); 447 448 /* 449 * Because the timer thread and the chip conversion clock 450 * are asynchronous, the period difference will eventually 451 * result in reading V[k-1] again, or skip V[k] at time Tk. 452 * In order to resync the timer with the conversion process 453 * we check the ConVersionReadyFlag. 454 * On hardware that supports using the ALERT pin to toggle a 455 * GPIO a triggered buffer could be used instead. 456 * For now, we pay for that extra read of the ALERT register 457 */ 458 if (!chip->allow_async_readout) 459 do { 460 ret = regmap_read(chip->regmap, INA226_ALERT_MASK, 461 &alert); 462 if (ret < 0) 463 return ret; 464 465 alert &= INA266_CVRF; 466 } while (!alert); 467 468 /* 469 * Single register reads: bulk_read will not work with ina226 470 * as there is no auto-increment of the address register for 471 * data length longer than 16bits. 472 */ 473 for_each_set_bit(bit, indio_dev->active_scan_mask, 474 indio_dev->masklength) { 475 unsigned int val; 476 477 ret = regmap_read(chip->regmap, 478 INA2XX_SHUNT_VOLTAGE + bit, &val); 479 if (ret < 0) 480 return ret; 481 482 data[i++] = val; 483 } 484 485 time_b = iio_get_time_ns(); 486 487 iio_push_to_buffers_with_timestamp(indio_dev, 488 (unsigned int *)data, time_a); 489 490 chip->prev_ns = time_a; 491 492 return (unsigned long)(time_b - time_a) / 1000; 493 }; 494 495 static int ina2xx_capture_thread(void *data) 496 { 497 struct iio_dev *indio_dev = data; 498 struct ina2xx_chip_info *chip = iio_priv(indio_dev); 499 unsigned int sampling_us = SAMPLING_PERIOD(chip); 500 int buffer_us; 501 502 /* 503 * Poll a bit faster than the chip internal Fs, in case 504 * we wish to sync with the conversion ready flag. 505 */ 506 if (!chip->allow_async_readout) 507 sampling_us -= 200; 508 509 do { 510 buffer_us = ina2xx_work_buffer(indio_dev); 511 if (buffer_us < 0) 512 return buffer_us; 513 514 if (sampling_us > buffer_us) 515 udelay(sampling_us - buffer_us); 516 517 } while (!kthread_should_stop()); 518 519 return 0; 520 } 521 522 static int ina2xx_buffer_enable(struct iio_dev *indio_dev) 523 { 524 struct ina2xx_chip_info *chip = iio_priv(indio_dev); 525 unsigned int sampling_us = SAMPLING_PERIOD(chip); 526 527 dev_dbg(&indio_dev->dev, "Enabling buffer w/ scan_mask %02x, freq = %d, avg =%u\n", 528 (unsigned int)(*indio_dev->active_scan_mask), 529 1000000 / sampling_us, chip->avg); 530 531 dev_dbg(&indio_dev->dev, "Expected work period: %u us\n", sampling_us); 532 dev_dbg(&indio_dev->dev, "Async readout mode: %d\n", 533 chip->allow_async_readout); 534 535 chip->prev_ns = iio_get_time_ns(); 536 537 chip->task = kthread_run(ina2xx_capture_thread, (void *)indio_dev, 538 "%s:%d-%uus", indio_dev->name, indio_dev->id, 539 sampling_us); 540 541 return PTR_ERR_OR_ZERO(chip->task); 542 } 543 544 static int ina2xx_buffer_disable(struct iio_dev *indio_dev) 545 { 546 struct ina2xx_chip_info *chip = iio_priv(indio_dev); 547 548 if (chip->task) { 549 kthread_stop(chip->task); 550 chip->task = NULL; 551 } 552 553 return 0; 554 } 555 556 static const struct iio_buffer_setup_ops ina2xx_setup_ops = { 557 .postenable = &ina2xx_buffer_enable, 558 .predisable = &ina2xx_buffer_disable, 559 }; 560 561 static int ina2xx_debug_reg(struct iio_dev *indio_dev, 562 unsigned reg, unsigned writeval, unsigned *readval) 563 { 564 struct ina2xx_chip_info *chip = iio_priv(indio_dev); 565 566 if (!readval) 567 return regmap_write(chip->regmap, reg, writeval); 568 569 return regmap_read(chip->regmap, reg, readval); 570 } 571 572 /* Possible integration times for vshunt and vbus */ 573 static IIO_CONST_ATTR_INT_TIME_AVAIL("0.000140 0.000204 0.000332 0.000588 0.001100 0.002116 0.004156 0.008244"); 574 575 static IIO_DEVICE_ATTR(in_allow_async_readout, S_IRUGO | S_IWUSR, 576 ina2xx_allow_async_readout_show, 577 ina2xx_allow_async_readout_store, 0); 578 579 static IIO_DEVICE_ATTR(in_shunt_resistor, S_IRUGO | S_IWUSR, 580 ina2xx_shunt_resistor_show, 581 ina2xx_shunt_resistor_store, 0); 582 583 static struct attribute *ina2xx_attributes[] = { 584 &iio_dev_attr_in_allow_async_readout.dev_attr.attr, 585 &iio_const_attr_integration_time_available.dev_attr.attr, 586 &iio_dev_attr_in_shunt_resistor.dev_attr.attr, 587 NULL, 588 }; 589 590 static const struct attribute_group ina2xx_attribute_group = { 591 .attrs = ina2xx_attributes, 592 }; 593 594 static const struct iio_info ina2xx_info = { 595 .driver_module = THIS_MODULE, 596 .attrs = &ina2xx_attribute_group, 597 .read_raw = ina2xx_read_raw, 598 .write_raw = ina2xx_write_raw, 599 .debugfs_reg_access = ina2xx_debug_reg, 600 }; 601 602 /* Initialize the configuration and calibration registers. */ 603 static int ina2xx_init(struct ina2xx_chip_info *chip, unsigned int config) 604 { 605 u16 regval; 606 int ret; 607 608 ret = regmap_write(chip->regmap, INA2XX_CONFIG, config); 609 if (ret) 610 return ret; 611 612 /* 613 * Set current LSB to 1mA, shunt is in uOhms 614 * (equation 13 in datasheet). We hardcode a Current_LSB 615 * of 1.0 x10-6. The only remaining parameter is RShunt. 616 * There is no need to expose the CALIBRATION register 617 * to the user for now. 618 */ 619 regval = DIV_ROUND_CLOSEST(chip->config->calibration_factor, 620 chip->shunt_resistor); 621 622 return regmap_write(chip->regmap, INA2XX_CALIBRATION, regval); 623 } 624 625 static int ina2xx_probe(struct i2c_client *client, 626 const struct i2c_device_id *id) 627 { 628 struct ina2xx_chip_info *chip; 629 struct iio_dev *indio_dev; 630 struct iio_buffer *buffer; 631 unsigned int val; 632 int ret; 633 634 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip)); 635 if (!indio_dev) 636 return -ENOMEM; 637 638 chip = iio_priv(indio_dev); 639 640 /* This is only used for device removal purposes. */ 641 i2c_set_clientdata(client, indio_dev); 642 643 chip->regmap = devm_regmap_init_i2c(client, &ina2xx_regmap_config); 644 if (IS_ERR(chip->regmap)) { 645 dev_err(&client->dev, "failed to allocate register map\n"); 646 return PTR_ERR(chip->regmap); 647 } 648 649 chip->config = &ina2xx_config[id->driver_data]; 650 651 mutex_init(&chip->state_lock); 652 653 if (of_property_read_u32(client->dev.of_node, 654 "shunt-resistor", &val) < 0) { 655 struct ina2xx_platform_data *pdata = 656 dev_get_platdata(&client->dev); 657 658 if (pdata) 659 val = pdata->shunt_uohms; 660 else 661 val = INA2XX_RSHUNT_DEFAULT; 662 } 663 664 ret = set_shunt_resistor(chip, val); 665 if (ret) 666 return ret; 667 668 /* Patch the current config register with default. */ 669 val = chip->config->config_default; 670 671 if (id->driver_data == ina226) { 672 ina226_set_average(chip, INA226_DEFAULT_AVG, &val); 673 ina226_set_int_time_vbus(chip, INA226_DEFAULT_IT, &val); 674 ina226_set_int_time_vshunt(chip, INA226_DEFAULT_IT, &val); 675 } 676 677 ret = ina2xx_init(chip, val); 678 if (ret) { 679 dev_err(&client->dev, "error configuring the device\n"); 680 return ret; 681 } 682 683 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 684 indio_dev->dev.parent = &client->dev; 685 indio_dev->channels = ina2xx_channels; 686 indio_dev->num_channels = ARRAY_SIZE(ina2xx_channels); 687 indio_dev->name = id->name; 688 indio_dev->info = &ina2xx_info; 689 indio_dev->setup_ops = &ina2xx_setup_ops; 690 691 buffer = devm_iio_kfifo_allocate(&indio_dev->dev); 692 if (!buffer) 693 return -ENOMEM; 694 695 iio_device_attach_buffer(indio_dev, buffer); 696 697 return iio_device_register(indio_dev); 698 } 699 700 static int ina2xx_remove(struct i2c_client *client) 701 { 702 struct iio_dev *indio_dev = i2c_get_clientdata(client); 703 struct ina2xx_chip_info *chip = iio_priv(indio_dev); 704 705 iio_device_unregister(indio_dev); 706 707 /* Powerdown */ 708 return regmap_update_bits(chip->regmap, INA2XX_CONFIG, 709 INA2XX_MODE_MASK, 0); 710 } 711 712 static const struct i2c_device_id ina2xx_id[] = { 713 {"ina219", ina219}, 714 {"ina220", ina219}, 715 {"ina226", ina226}, 716 {"ina230", ina226}, 717 {"ina231", ina226}, 718 {} 719 }; 720 MODULE_DEVICE_TABLE(i2c, ina2xx_id); 721 722 static struct i2c_driver ina2xx_driver = { 723 .driver = { 724 .name = KBUILD_MODNAME, 725 }, 726 .probe = ina2xx_probe, 727 .remove = ina2xx_remove, 728 .id_table = ina2xx_id, 729 }; 730 module_i2c_driver(ina2xx_driver); 731 732 MODULE_AUTHOR("Marc Titinger <marc.titinger@baylibre.com>"); 733 MODULE_DESCRIPTION("Texas Instruments INA2XX ADC driver"); 734 MODULE_LICENSE("GPL v2"); 735