1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * NXP i.MX93 ADC driver 4 * 5 * Copyright 2023 NXP 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/err.h> 12 #include <linux/iio/iio.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regulator/consumer.h> 21 22 #define IMX93_ADC_DRIVER_NAME "imx93-adc" 23 24 /* Register map definition */ 25 #define IMX93_ADC_MCR 0x00 26 #define IMX93_ADC_MSR 0x04 27 #define IMX93_ADC_ISR 0x10 28 #define IMX93_ADC_IMR 0x20 29 #define IMX93_ADC_CIMR0 0x24 30 #define IMX93_ADC_CTR0 0x94 31 #define IMX93_ADC_NCMR0 0xA4 32 #define IMX93_ADC_PCDR0 0x100 33 #define IMX93_ADC_PCDR1 0x104 34 #define IMX93_ADC_PCDR2 0x108 35 #define IMX93_ADC_PCDR3 0x10C 36 #define IMX93_ADC_PCDR4 0x110 37 #define IMX93_ADC_PCDR5 0x114 38 #define IMX93_ADC_PCDR6 0x118 39 #define IMX93_ADC_PCDR7 0x11C 40 #define IMX93_ADC_CALSTAT 0x39C 41 #define IMX93_ADC_CALCFG0 0x3A0 42 43 /* ADC bit shift */ 44 #define IMX93_ADC_MCR_MODE_MASK BIT(29) 45 #define IMX93_ADC_MCR_NSTART_MASK BIT(24) 46 #define IMX93_ADC_MCR_CALSTART_MASK BIT(14) 47 #define IMX93_ADC_MCR_ADCLKSE_MASK BIT(8) 48 #define IMX93_ADC_MCR_PWDN_MASK BIT(0) 49 #define IMX93_ADC_MSR_CALFAIL_MASK BIT(30) 50 #define IMX93_ADC_MSR_CALBUSY_MASK BIT(29) 51 #define IMX93_ADC_MSR_ADCSTATUS_MASK GENMASK(2, 0) 52 #define IMX93_ADC_ISR_ECH_MASK BIT(0) 53 #define IMX93_ADC_ISR_EOC_MASK BIT(1) 54 #define IMX93_ADC_ISR_EOC_ECH_MASK (IMX93_ADC_ISR_EOC_MASK | \ 55 IMX93_ADC_ISR_ECH_MASK) 56 #define IMX93_ADC_IMR_JEOC_MASK BIT(3) 57 #define IMX93_ADC_IMR_JECH_MASK BIT(2) 58 #define IMX93_ADC_IMR_EOC_MASK BIT(1) 59 #define IMX93_ADC_IMR_ECH_MASK BIT(0) 60 #define IMX93_ADC_PCDR_CDATA_MASK GENMASK(11, 0) 61 62 #define IMX93_ADC_CALCFG0_LDFAIL_MASK BIT(4) 63 64 /* ADC status */ 65 #define IMX93_ADC_MSR_ADCSTATUS_IDLE 0 66 #define IMX93_ADC_MSR_ADCSTATUS_POWER_DOWN 1 67 #define IMX93_ADC_MSR_ADCSTATUS_WAIT_STATE 2 68 #define IMX93_ADC_MSR_ADCSTATUS_BUSY_IN_CALIBRATION 3 69 #define IMX93_ADC_MSR_ADCSTATUS_SAMPLE 4 70 #define IMX93_ADC_MSR_ADCSTATUS_CONVERSION 6 71 72 #define IMX93_ADC_TIMEOUT msecs_to_jiffies(100) 73 74 struct imx93_adc { 75 struct device *dev; 76 void __iomem *regs; 77 struct clk *ipg_clk; 78 int irq; 79 struct regulator *vref; 80 /* lock to protect against multiple access to the device */ 81 struct mutex lock; 82 struct completion completion; 83 }; 84 85 #define IMX93_ADC_CHAN(_idx) { \ 86 .type = IIO_VOLTAGE, \ 87 .indexed = 1, \ 88 .channel = (_idx), \ 89 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 90 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 91 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 92 } 93 94 static const struct iio_chan_spec imx93_adc_iio_channels[] = { 95 IMX93_ADC_CHAN(0), 96 IMX93_ADC_CHAN(1), 97 IMX93_ADC_CHAN(2), 98 IMX93_ADC_CHAN(3), 99 IMX93_ADC_CHAN(4), 100 IMX93_ADC_CHAN(5), 101 IMX93_ADC_CHAN(6), 102 IMX93_ADC_CHAN(7), 103 }; 104 105 static void imx93_adc_power_down(struct imx93_adc *adc) 106 { 107 u32 mcr, msr; 108 int ret; 109 110 mcr = readl(adc->regs + IMX93_ADC_MCR); 111 mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); 112 writel(mcr, adc->regs + IMX93_ADC_MCR); 113 114 ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr, 115 ((msr & IMX93_ADC_MSR_ADCSTATUS_MASK) == 116 IMX93_ADC_MSR_ADCSTATUS_POWER_DOWN), 117 1, 50); 118 if (ret == -ETIMEDOUT) 119 dev_warn(adc->dev, 120 "ADC do not in power down mode, current MSR is %x\n", 121 msr); 122 } 123 124 static void imx93_adc_power_up(struct imx93_adc *adc) 125 { 126 u32 mcr; 127 128 /* bring ADC out of power down state, in idle state */ 129 mcr = readl(adc->regs + IMX93_ADC_MCR); 130 mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); 131 writel(mcr, adc->regs + IMX93_ADC_MCR); 132 } 133 134 static void imx93_adc_config_ad_clk(struct imx93_adc *adc) 135 { 136 u32 mcr; 137 138 /* put adc in power down mode */ 139 imx93_adc_power_down(adc); 140 141 /* config the AD_CLK equal to bus clock */ 142 mcr = readl(adc->regs + IMX93_ADC_MCR); 143 mcr |= FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1); 144 writel(mcr, adc->regs + IMX93_ADC_MCR); 145 146 imx93_adc_power_up(adc); 147 } 148 149 static int imx93_adc_calibration(struct imx93_adc *adc) 150 { 151 u32 mcr, msr, calcfg; 152 int ret; 153 154 /* make sure ADC in power down mode */ 155 imx93_adc_power_down(adc); 156 157 /* config SAR controller operating clock */ 158 mcr = readl(adc->regs + IMX93_ADC_MCR); 159 mcr &= ~FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1); 160 writel(mcr, adc->regs + IMX93_ADC_MCR); 161 162 imx93_adc_power_up(adc); 163 164 /* Enable loading of calibrated values even in fail condition */ 165 calcfg = readl(adc->regs + IMX93_ADC_CALCFG0); 166 calcfg |= IMX93_ADC_CALCFG0_LDFAIL_MASK; 167 writel(calcfg, adc->regs + IMX93_ADC_CALCFG0); 168 169 /* 170 * TODO: we use the default TSAMP/NRSMPL/AVGEN in MCR, 171 * can add the setting of these bit if need in future. 172 */ 173 174 /* run calibration */ 175 mcr = readl(adc->regs + IMX93_ADC_MCR); 176 mcr |= FIELD_PREP(IMX93_ADC_MCR_CALSTART_MASK, 1); 177 writel(mcr, adc->regs + IMX93_ADC_MCR); 178 179 /* wait calibration to be finished */ 180 ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr, 181 !(msr & IMX93_ADC_MSR_CALBUSY_MASK), 1000, 2000000); 182 if (ret == -ETIMEDOUT) { 183 dev_warn(adc->dev, "ADC do not finish calibration in 2 min!\n"); 184 imx93_adc_power_down(adc); 185 return ret; 186 } 187 188 /* check whether calbration is success or not */ 189 msr = readl(adc->regs + IMX93_ADC_MSR); 190 if (msr & IMX93_ADC_MSR_CALFAIL_MASK) { 191 /* 192 * Only give warning here, this means the noise of the 193 * reference voltage do not meet the requirement: 194 * ADC reference voltage Noise < 1.8V * 1/2^ENOB 195 * And the resault of ADC is not that accurate. 196 */ 197 dev_warn(adc->dev, "ADC calibration failed!\n"); 198 } 199 200 return 0; 201 } 202 203 static int imx93_adc_read_channel_conversion(struct imx93_adc *adc, 204 int channel_number, 205 int *result) 206 { 207 u32 channel; 208 u32 imr, mcr, pcda; 209 long ret; 210 211 reinit_completion(&adc->completion); 212 213 /* config channel mask register */ 214 channel = 1 << channel_number; 215 writel(channel, adc->regs + IMX93_ADC_NCMR0); 216 217 /* TODO: can config desired sample time in CTRn if need */ 218 219 /* config interrupt mask */ 220 imr = FIELD_PREP(IMX93_ADC_IMR_EOC_MASK, 1); 221 writel(imr, adc->regs + IMX93_ADC_IMR); 222 writel(channel, adc->regs + IMX93_ADC_CIMR0); 223 224 /* config one-shot mode */ 225 mcr = readl(adc->regs + IMX93_ADC_MCR); 226 mcr &= ~FIELD_PREP(IMX93_ADC_MCR_MODE_MASK, 1); 227 writel(mcr, adc->regs + IMX93_ADC_MCR); 228 229 /* start normal conversion */ 230 mcr = readl(adc->regs + IMX93_ADC_MCR); 231 mcr |= FIELD_PREP(IMX93_ADC_MCR_NSTART_MASK, 1); 232 writel(mcr, adc->regs + IMX93_ADC_MCR); 233 234 ret = wait_for_completion_interruptible_timeout(&adc->completion, 235 IMX93_ADC_TIMEOUT); 236 if (ret == 0) 237 return -ETIMEDOUT; 238 239 if (ret < 0) 240 return ret; 241 242 pcda = readl(adc->regs + IMX93_ADC_PCDR0 + channel_number * 4); 243 244 *result = FIELD_GET(IMX93_ADC_PCDR_CDATA_MASK, pcda); 245 246 return ret; 247 } 248 249 static int imx93_adc_read_raw(struct iio_dev *indio_dev, 250 struct iio_chan_spec const *chan, 251 int *val, int *val2, long mask) 252 { 253 struct imx93_adc *adc = iio_priv(indio_dev); 254 struct device *dev = adc->dev; 255 int ret; 256 257 switch (mask) { 258 case IIO_CHAN_INFO_RAW: 259 pm_runtime_get_sync(dev); 260 mutex_lock(&adc->lock); 261 ret = imx93_adc_read_channel_conversion(adc, chan->channel, val); 262 mutex_unlock(&adc->lock); 263 pm_runtime_put_sync_autosuspend(dev); 264 if (ret < 0) 265 return ret; 266 267 return IIO_VAL_INT; 268 269 case IIO_CHAN_INFO_SCALE: 270 ret = regulator_get_voltage(adc->vref); 271 if (ret < 0) 272 return ret; 273 *val = ret / 1000; 274 *val2 = 12; 275 return IIO_VAL_FRACTIONAL_LOG2; 276 277 case IIO_CHAN_INFO_SAMP_FREQ: 278 *val = clk_get_rate(adc->ipg_clk); 279 return IIO_VAL_INT; 280 281 default: 282 return -EINVAL; 283 } 284 } 285 286 static irqreturn_t imx93_adc_isr(int irq, void *dev_id) 287 { 288 struct imx93_adc *adc = dev_id; 289 u32 isr, eoc, unexpected; 290 291 isr = readl(adc->regs + IMX93_ADC_ISR); 292 293 if (FIELD_GET(IMX93_ADC_ISR_EOC_ECH_MASK, isr)) { 294 eoc = isr & IMX93_ADC_ISR_EOC_ECH_MASK; 295 writel(eoc, adc->regs + IMX93_ADC_ISR); 296 complete(&adc->completion); 297 } 298 299 unexpected = isr & ~IMX93_ADC_ISR_EOC_ECH_MASK; 300 if (unexpected) { 301 writel(unexpected, adc->regs + IMX93_ADC_ISR); 302 dev_err(adc->dev, "Unexpected interrupt 0x%08x.\n", unexpected); 303 return IRQ_NONE; 304 } 305 306 return IRQ_HANDLED; 307 } 308 309 static const struct iio_info imx93_adc_iio_info = { 310 .read_raw = &imx93_adc_read_raw, 311 }; 312 313 static int imx93_adc_probe(struct platform_device *pdev) 314 { 315 struct imx93_adc *adc; 316 struct iio_dev *indio_dev; 317 struct device *dev = &pdev->dev; 318 int ret; 319 320 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 321 if (!indio_dev) 322 return -ENOMEM; 323 324 adc = iio_priv(indio_dev); 325 adc->dev = dev; 326 327 mutex_init(&adc->lock); 328 adc->regs = devm_platform_ioremap_resource(pdev, 0); 329 if (IS_ERR(adc->regs)) 330 return dev_err_probe(dev, PTR_ERR(adc->regs), 331 "Failed getting ioremap resource\n"); 332 333 /* The third irq is for ADC conversion usage */ 334 adc->irq = platform_get_irq(pdev, 2); 335 if (adc->irq < 0) 336 return adc->irq; 337 338 adc->ipg_clk = devm_clk_get(dev, "ipg"); 339 if (IS_ERR(adc->ipg_clk)) 340 return dev_err_probe(dev, PTR_ERR(adc->ipg_clk), 341 "Failed getting clock.\n"); 342 343 adc->vref = devm_regulator_get(dev, "vref"); 344 if (IS_ERR(adc->vref)) 345 return dev_err_probe(dev, PTR_ERR(adc->vref), 346 "Failed getting reference voltage.\n"); 347 348 ret = regulator_enable(adc->vref); 349 if (ret) 350 return dev_err_probe(dev, ret, 351 "Failed to enable reference voltage.\n"); 352 353 platform_set_drvdata(pdev, indio_dev); 354 355 init_completion(&adc->completion); 356 357 indio_dev->name = "imx93-adc"; 358 indio_dev->info = &imx93_adc_iio_info; 359 indio_dev->modes = INDIO_DIRECT_MODE; 360 indio_dev->channels = imx93_adc_iio_channels; 361 indio_dev->num_channels = ARRAY_SIZE(imx93_adc_iio_channels); 362 363 ret = clk_prepare_enable(adc->ipg_clk); 364 if (ret) { 365 dev_err_probe(dev, ret, 366 "Failed to enable ipg clock.\n"); 367 goto error_regulator_disable; 368 } 369 370 ret = request_irq(adc->irq, imx93_adc_isr, 0, IMX93_ADC_DRIVER_NAME, adc); 371 if (ret < 0) { 372 dev_err_probe(dev, ret, 373 "Failed requesting irq, irq = %d\n", adc->irq); 374 goto error_ipg_clk_disable; 375 } 376 377 ret = imx93_adc_calibration(adc); 378 if (ret < 0) 379 goto error_free_adc_irq; 380 381 imx93_adc_config_ad_clk(adc); 382 383 ret = iio_device_register(indio_dev); 384 if (ret) { 385 dev_err_probe(dev, ret, 386 "Failed to register this iio device.\n"); 387 goto error_adc_power_down; 388 } 389 390 pm_runtime_set_active(dev); 391 pm_runtime_set_autosuspend_delay(dev, 50); 392 pm_runtime_use_autosuspend(dev); 393 pm_runtime_enable(dev); 394 395 return 0; 396 397 error_adc_power_down: 398 imx93_adc_power_down(adc); 399 error_free_adc_irq: 400 free_irq(adc->irq, adc); 401 error_ipg_clk_disable: 402 clk_disable_unprepare(adc->ipg_clk); 403 error_regulator_disable: 404 regulator_disable(adc->vref); 405 406 return ret; 407 } 408 409 static void imx93_adc_remove(struct platform_device *pdev) 410 { 411 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 412 struct imx93_adc *adc = iio_priv(indio_dev); 413 struct device *dev = adc->dev; 414 415 /* adc power down need clock on */ 416 pm_runtime_get_sync(dev); 417 418 pm_runtime_disable(dev); 419 pm_runtime_dont_use_autosuspend(dev); 420 pm_runtime_put_noidle(dev); 421 422 iio_device_unregister(indio_dev); 423 imx93_adc_power_down(adc); 424 free_irq(adc->irq, adc); 425 clk_disable_unprepare(adc->ipg_clk); 426 regulator_disable(adc->vref); 427 } 428 429 static int imx93_adc_runtime_suspend(struct device *dev) 430 { 431 struct iio_dev *indio_dev = dev_get_drvdata(dev); 432 struct imx93_adc *adc = iio_priv(indio_dev); 433 434 imx93_adc_power_down(adc); 435 clk_disable_unprepare(adc->ipg_clk); 436 regulator_disable(adc->vref); 437 438 return 0; 439 } 440 441 static int imx93_adc_runtime_resume(struct device *dev) 442 { 443 struct iio_dev *indio_dev = dev_get_drvdata(dev); 444 struct imx93_adc *adc = iio_priv(indio_dev); 445 int ret; 446 447 ret = regulator_enable(adc->vref); 448 if (ret) { 449 dev_err(dev, 450 "Can't enable adc reference top voltage, err = %d\n", 451 ret); 452 return ret; 453 } 454 455 ret = clk_prepare_enable(adc->ipg_clk); 456 if (ret) { 457 dev_err(dev, "Could not prepare or enable clock.\n"); 458 goto err_disable_reg; 459 } 460 461 imx93_adc_power_up(adc); 462 463 return 0; 464 465 err_disable_reg: 466 regulator_disable(adc->vref); 467 468 return ret; 469 } 470 471 static DEFINE_RUNTIME_DEV_PM_OPS(imx93_adc_pm_ops, 472 imx93_adc_runtime_suspend, 473 imx93_adc_runtime_resume, NULL); 474 475 static const struct of_device_id imx93_adc_match[] = { 476 { .compatible = "nxp,imx93-adc", }, 477 { } 478 }; 479 MODULE_DEVICE_TABLE(of, imx93_adc_match); 480 481 static struct platform_driver imx93_adc_driver = { 482 .probe = imx93_adc_probe, 483 .remove = imx93_adc_remove, 484 .driver = { 485 .name = IMX93_ADC_DRIVER_NAME, 486 .of_match_table = imx93_adc_match, 487 .pm = pm_ptr(&imx93_adc_pm_ops), 488 }, 489 }; 490 491 module_platform_driver(imx93_adc_driver); 492 493 MODULE_DESCRIPTION("NXP i.MX93 ADC driver"); 494 MODULE_AUTHOR("Haibo Chen <haibo.chen@nxp.com>"); 495 MODULE_LICENSE("GPL"); 496