1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Holt Integrated Circuits HI-8435 threshold detector driver 4 * 5 * Copyright (C) 2015 Zodiac Inflight Innovations 6 * Copyright (C) 2015 Cogent Embedded, Inc. 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/iio/events.h> 11 #include <linux/iio/iio.h> 12 #include <linux/iio/sysfs.h> 13 #include <linux/iio/trigger.h> 14 #include <linux/iio/trigger_consumer.h> 15 #include <linux/iio/triggered_event.h> 16 #include <linux/interrupt.h> 17 #include <linux/module.h> 18 #include <linux/spi/spi.h> 19 #include <linux/gpio/consumer.h> 20 21 /* Register offsets for HI-8435 */ 22 #define HI8435_CTRL_REG 0x02 23 #define HI8435_PSEN_REG 0x04 24 #define HI8435_TMDATA_REG 0x1E 25 #define HI8435_GOCENHYS_REG 0x3A 26 #define HI8435_SOCENHYS_REG 0x3C 27 #define HI8435_SO7_0_REG 0x10 28 #define HI8435_SO15_8_REG 0x12 29 #define HI8435_SO23_16_REG 0x14 30 #define HI8435_SO31_24_REG 0x16 31 #define HI8435_SO31_0_REG 0x78 32 33 #define HI8435_WRITE_OPCODE 0x00 34 #define HI8435_READ_OPCODE 0x80 35 36 /* CTRL register bits */ 37 #define HI8435_CTRL_TEST 0x01 38 #define HI8435_CTRL_SRST 0x02 39 40 struct hi8435_priv { 41 struct spi_device *spi; 42 struct mutex lock; 43 44 unsigned long event_scan_mask; /* soft mask/unmask channels events */ 45 unsigned int event_prev_val; 46 47 unsigned threshold_lo[2]; /* GND-Open and Supply-Open thresholds */ 48 unsigned threshold_hi[2]; /* GND-Open and Supply-Open thresholds */ 49 u8 reg_buffer[3] __aligned(IIO_DMA_MINALIGN); 50 }; 51 52 static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val) 53 { 54 reg |= HI8435_READ_OPCODE; 55 return spi_write_then_read(priv->spi, ®, 1, val, 1); 56 } 57 58 static int hi8435_readw(struct hi8435_priv *priv, u8 reg, u16 *val) 59 { 60 int ret; 61 __be16 be_val; 62 63 reg |= HI8435_READ_OPCODE; 64 ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 2); 65 *val = be16_to_cpu(be_val); 66 67 return ret; 68 } 69 70 static int hi8435_readl(struct hi8435_priv *priv, u8 reg, u32 *val) 71 { 72 int ret; 73 __be32 be_val; 74 75 reg |= HI8435_READ_OPCODE; 76 ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 4); 77 *val = be32_to_cpu(be_val); 78 79 return ret; 80 } 81 82 static int hi8435_writeb(struct hi8435_priv *priv, u8 reg, u8 val) 83 { 84 priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE; 85 priv->reg_buffer[1] = val; 86 87 return spi_write(priv->spi, priv->reg_buffer, 2); 88 } 89 90 static int hi8435_writew(struct hi8435_priv *priv, u8 reg, u16 val) 91 { 92 priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE; 93 priv->reg_buffer[1] = (val >> 8) & 0xff; 94 priv->reg_buffer[2] = val & 0xff; 95 96 return spi_write(priv->spi, priv->reg_buffer, 3); 97 } 98 99 static int hi8435_read_raw(struct iio_dev *idev, 100 const struct iio_chan_spec *chan, 101 int *val, int *val2, long mask) 102 { 103 struct hi8435_priv *priv = iio_priv(idev); 104 u32 tmp; 105 int ret; 106 107 switch (mask) { 108 case IIO_CHAN_INFO_RAW: 109 ret = hi8435_readl(priv, HI8435_SO31_0_REG, &tmp); 110 if (ret < 0) 111 return ret; 112 *val = !!(tmp & BIT(chan->channel)); 113 return IIO_VAL_INT; 114 default: 115 return -EINVAL; 116 } 117 } 118 119 static int hi8435_read_event_config(struct iio_dev *idev, 120 const struct iio_chan_spec *chan, 121 enum iio_event_type type, 122 enum iio_event_direction dir) 123 { 124 struct hi8435_priv *priv = iio_priv(idev); 125 126 return !!(priv->event_scan_mask & BIT(chan->channel)); 127 } 128 129 static int hi8435_write_event_config(struct iio_dev *idev, 130 const struct iio_chan_spec *chan, 131 enum iio_event_type type, 132 enum iio_event_direction dir, bool state) 133 { 134 struct hi8435_priv *priv = iio_priv(idev); 135 int ret; 136 u32 tmp; 137 138 if (state) { 139 ret = hi8435_readl(priv, HI8435_SO31_0_REG, &tmp); 140 if (ret < 0) 141 return ret; 142 if (tmp & BIT(chan->channel)) 143 priv->event_prev_val |= BIT(chan->channel); 144 else 145 priv->event_prev_val &= ~BIT(chan->channel); 146 147 priv->event_scan_mask |= BIT(chan->channel); 148 } else 149 priv->event_scan_mask &= ~BIT(chan->channel); 150 151 return 0; 152 } 153 154 static int hi8435_read_event_value(struct iio_dev *idev, 155 const struct iio_chan_spec *chan, 156 enum iio_event_type type, 157 enum iio_event_direction dir, 158 enum iio_event_info info, 159 int *val, int *val2) 160 { 161 struct hi8435_priv *priv = iio_priv(idev); 162 int ret; 163 u8 mode, psen; 164 u16 reg; 165 166 ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen); 167 if (ret < 0) 168 return ret; 169 170 /* Supply-Open or GND-Open sensing mode */ 171 mode = !!(psen & BIT(chan->channel / 8)); 172 173 ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : 174 HI8435_GOCENHYS_REG, ®); 175 if (ret < 0) 176 return ret; 177 178 if (dir == IIO_EV_DIR_FALLING) 179 *val = ((reg & 0xff) - (reg >> 8)) / 2; 180 else if (dir == IIO_EV_DIR_RISING) 181 *val = ((reg & 0xff) + (reg >> 8)) / 2; 182 183 return IIO_VAL_INT; 184 } 185 186 static int hi8435_write_event_value(struct iio_dev *idev, 187 const struct iio_chan_spec *chan, 188 enum iio_event_type type, 189 enum iio_event_direction dir, 190 enum iio_event_info info, 191 int val, int val2) 192 { 193 struct hi8435_priv *priv = iio_priv(idev); 194 int ret; 195 u8 mode, psen; 196 u16 reg; 197 198 ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen); 199 if (ret < 0) 200 return ret; 201 202 /* Supply-Open or GND-Open sensing mode */ 203 mode = !!(psen & BIT(chan->channel / 8)); 204 205 ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : 206 HI8435_GOCENHYS_REG, ®); 207 if (ret < 0) 208 return ret; 209 210 if (dir == IIO_EV_DIR_FALLING) { 211 /* falling threshold range 2..21V, hysteresis minimum 2V */ 212 if (val < 2 || val > 21 || (val + 2) > priv->threshold_hi[mode]) 213 return -EINVAL; 214 215 if (val == priv->threshold_lo[mode]) 216 return 0; 217 218 priv->threshold_lo[mode] = val; 219 220 /* hysteresis must not be odd */ 221 if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2) 222 priv->threshold_hi[mode]--; 223 } else if (dir == IIO_EV_DIR_RISING) { 224 /* rising threshold range 3..22V, hysteresis minimum 2V */ 225 if (val < 3 || val > 22 || val < (priv->threshold_lo[mode] + 2)) 226 return -EINVAL; 227 228 if (val == priv->threshold_hi[mode]) 229 return 0; 230 231 priv->threshold_hi[mode] = val; 232 233 /* hysteresis must not be odd */ 234 if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2) 235 priv->threshold_lo[mode]++; 236 } 237 238 /* program thresholds */ 239 mutex_lock(&priv->lock); 240 241 ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : 242 HI8435_GOCENHYS_REG, ®); 243 if (ret < 0) { 244 mutex_unlock(&priv->lock); 245 return ret; 246 } 247 248 /* hysteresis */ 249 reg = priv->threshold_hi[mode] - priv->threshold_lo[mode]; 250 reg <<= 8; 251 /* threshold center */ 252 reg |= (priv->threshold_hi[mode] + priv->threshold_lo[mode]); 253 254 ret = hi8435_writew(priv, mode ? HI8435_SOCENHYS_REG : 255 HI8435_GOCENHYS_REG, reg); 256 257 mutex_unlock(&priv->lock); 258 259 return ret; 260 } 261 262 static int hi8435_debugfs_reg_access(struct iio_dev *idev, 263 unsigned reg, unsigned writeval, 264 unsigned *readval) 265 { 266 struct hi8435_priv *priv = iio_priv(idev); 267 int ret; 268 u8 val; 269 270 if (readval != NULL) { 271 ret = hi8435_readb(priv, reg, &val); 272 *readval = val; 273 } else { 274 val = (u8)writeval; 275 ret = hi8435_writeb(priv, reg, val); 276 } 277 278 return ret; 279 } 280 281 static const struct iio_event_spec hi8435_events[] = { 282 { 283 .type = IIO_EV_TYPE_THRESH, 284 .dir = IIO_EV_DIR_RISING, 285 .mask_separate = BIT(IIO_EV_INFO_VALUE), 286 }, { 287 .type = IIO_EV_TYPE_THRESH, 288 .dir = IIO_EV_DIR_FALLING, 289 .mask_separate = BIT(IIO_EV_INFO_VALUE), 290 }, { 291 .type = IIO_EV_TYPE_THRESH, 292 .dir = IIO_EV_DIR_EITHER, 293 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 294 }, 295 }; 296 297 static int hi8435_get_sensing_mode(struct iio_dev *idev, 298 const struct iio_chan_spec *chan) 299 { 300 struct hi8435_priv *priv = iio_priv(idev); 301 int ret; 302 u8 reg; 303 304 ret = hi8435_readb(priv, HI8435_PSEN_REG, ®); 305 if (ret < 0) 306 return ret; 307 308 return !!(reg & BIT(chan->channel / 8)); 309 } 310 311 static int hi8435_set_sensing_mode(struct iio_dev *idev, 312 const struct iio_chan_spec *chan, 313 unsigned int mode) 314 { 315 struct hi8435_priv *priv = iio_priv(idev); 316 int ret; 317 u8 reg; 318 319 mutex_lock(&priv->lock); 320 321 ret = hi8435_readb(priv, HI8435_PSEN_REG, ®); 322 if (ret < 0) { 323 mutex_unlock(&priv->lock); 324 return ret; 325 } 326 327 reg &= ~BIT(chan->channel / 8); 328 if (mode) 329 reg |= BIT(chan->channel / 8); 330 331 ret = hi8435_writeb(priv, HI8435_PSEN_REG, reg); 332 333 mutex_unlock(&priv->lock); 334 335 return ret; 336 } 337 338 static const char * const hi8435_sensing_modes[] = { "GND-Open", 339 "Supply-Open" }; 340 341 static const struct iio_enum hi8435_sensing_mode = { 342 .items = hi8435_sensing_modes, 343 .num_items = ARRAY_SIZE(hi8435_sensing_modes), 344 .get = hi8435_get_sensing_mode, 345 .set = hi8435_set_sensing_mode, 346 }; 347 348 static const struct iio_chan_spec_ext_info hi8435_ext_info[] = { 349 IIO_ENUM("sensing_mode", IIO_SEPARATE, &hi8435_sensing_mode), 350 IIO_ENUM_AVAILABLE("sensing_mode", IIO_SHARED_BY_TYPE, &hi8435_sensing_mode), 351 { } 352 }; 353 354 #define HI8435_VOLTAGE_CHANNEL(num) \ 355 { \ 356 .type = IIO_VOLTAGE, \ 357 .indexed = 1, \ 358 .channel = num, \ 359 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 360 .event_spec = hi8435_events, \ 361 .num_event_specs = ARRAY_SIZE(hi8435_events), \ 362 .ext_info = hi8435_ext_info, \ 363 } 364 365 static const struct iio_chan_spec hi8435_channels[] = { 366 HI8435_VOLTAGE_CHANNEL(0), 367 HI8435_VOLTAGE_CHANNEL(1), 368 HI8435_VOLTAGE_CHANNEL(2), 369 HI8435_VOLTAGE_CHANNEL(3), 370 HI8435_VOLTAGE_CHANNEL(4), 371 HI8435_VOLTAGE_CHANNEL(5), 372 HI8435_VOLTAGE_CHANNEL(6), 373 HI8435_VOLTAGE_CHANNEL(7), 374 HI8435_VOLTAGE_CHANNEL(8), 375 HI8435_VOLTAGE_CHANNEL(9), 376 HI8435_VOLTAGE_CHANNEL(10), 377 HI8435_VOLTAGE_CHANNEL(11), 378 HI8435_VOLTAGE_CHANNEL(12), 379 HI8435_VOLTAGE_CHANNEL(13), 380 HI8435_VOLTAGE_CHANNEL(14), 381 HI8435_VOLTAGE_CHANNEL(15), 382 HI8435_VOLTAGE_CHANNEL(16), 383 HI8435_VOLTAGE_CHANNEL(17), 384 HI8435_VOLTAGE_CHANNEL(18), 385 HI8435_VOLTAGE_CHANNEL(19), 386 HI8435_VOLTAGE_CHANNEL(20), 387 HI8435_VOLTAGE_CHANNEL(21), 388 HI8435_VOLTAGE_CHANNEL(22), 389 HI8435_VOLTAGE_CHANNEL(23), 390 HI8435_VOLTAGE_CHANNEL(24), 391 HI8435_VOLTAGE_CHANNEL(25), 392 HI8435_VOLTAGE_CHANNEL(26), 393 HI8435_VOLTAGE_CHANNEL(27), 394 HI8435_VOLTAGE_CHANNEL(28), 395 HI8435_VOLTAGE_CHANNEL(29), 396 HI8435_VOLTAGE_CHANNEL(30), 397 HI8435_VOLTAGE_CHANNEL(31), 398 IIO_CHAN_SOFT_TIMESTAMP(32), 399 }; 400 401 static const struct iio_info hi8435_info = { 402 .read_raw = hi8435_read_raw, 403 .read_event_config = hi8435_read_event_config, 404 .write_event_config = hi8435_write_event_config, 405 .read_event_value = hi8435_read_event_value, 406 .write_event_value = hi8435_write_event_value, 407 .debugfs_reg_access = hi8435_debugfs_reg_access, 408 }; 409 410 static void hi8435_iio_push_event(struct iio_dev *idev, unsigned int val) 411 { 412 struct hi8435_priv *priv = iio_priv(idev); 413 enum iio_event_direction dir; 414 unsigned int i; 415 unsigned int status = priv->event_prev_val ^ val; 416 417 if (!status) 418 return; 419 420 for_each_set_bit(i, &priv->event_scan_mask, 32) { 421 if (status & BIT(i)) { 422 dir = val & BIT(i) ? IIO_EV_DIR_RISING : 423 IIO_EV_DIR_FALLING; 424 iio_push_event(idev, 425 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i, 426 IIO_EV_TYPE_THRESH, dir), 427 iio_get_time_ns(idev)); 428 } 429 } 430 431 priv->event_prev_val = val; 432 } 433 434 static irqreturn_t hi8435_trigger_handler(int irq, void *private) 435 { 436 struct iio_poll_func *pf = private; 437 struct iio_dev *idev = pf->indio_dev; 438 struct hi8435_priv *priv = iio_priv(idev); 439 u32 val; 440 int ret; 441 442 ret = hi8435_readl(priv, HI8435_SO31_0_REG, &val); 443 if (ret < 0) 444 goto err_read; 445 446 hi8435_iio_push_event(idev, val); 447 448 err_read: 449 iio_trigger_notify_done(idev->trig); 450 451 return IRQ_HANDLED; 452 } 453 454 static void hi8435_triggered_event_cleanup(void *data) 455 { 456 iio_triggered_event_cleanup(data); 457 } 458 459 static int hi8435_probe(struct spi_device *spi) 460 { 461 struct iio_dev *idev; 462 struct hi8435_priv *priv; 463 struct gpio_desc *reset_gpio; 464 int ret; 465 466 idev = devm_iio_device_alloc(&spi->dev, sizeof(*priv)); 467 if (!idev) 468 return -ENOMEM; 469 470 priv = iio_priv(idev); 471 priv->spi = spi; 472 473 reset_gpio = devm_gpiod_get(&spi->dev, NULL, GPIOD_OUT_LOW); 474 if (IS_ERR(reset_gpio)) { 475 /* chip s/w reset if h/w reset failed */ 476 hi8435_writeb(priv, HI8435_CTRL_REG, HI8435_CTRL_SRST); 477 hi8435_writeb(priv, HI8435_CTRL_REG, 0); 478 } else { 479 udelay(5); 480 gpiod_set_value_cansleep(reset_gpio, 1); 481 } 482 483 mutex_init(&priv->lock); 484 485 idev->name = spi_get_device_id(spi)->name; 486 idev->modes = INDIO_DIRECT_MODE; 487 idev->info = &hi8435_info; 488 idev->channels = hi8435_channels; 489 idev->num_channels = ARRAY_SIZE(hi8435_channels); 490 491 /* unmask all events */ 492 priv->event_scan_mask = ~(0); 493 /* 494 * There is a restriction in the chip - the hysteresis can not be odd. 495 * If the hysteresis is set to odd value then chip gets into lock state 496 * and not functional anymore. 497 * After chip reset the thresholds are in undefined state, so we need to 498 * initialize thresholds to some initial values and then prevent 499 * userspace setting odd hysteresis. 500 * 501 * Set threshold low voltage to 2V, threshold high voltage to 4V 502 * for both GND-Open and Supply-Open sensing modes. 503 */ 504 priv->threshold_lo[0] = priv->threshold_lo[1] = 2; 505 priv->threshold_hi[0] = priv->threshold_hi[1] = 4; 506 hi8435_writew(priv, HI8435_GOCENHYS_REG, 0x206); 507 hi8435_writew(priv, HI8435_SOCENHYS_REG, 0x206); 508 509 ret = iio_triggered_event_setup(idev, NULL, hi8435_trigger_handler); 510 if (ret) 511 return ret; 512 513 ret = devm_add_action_or_reset(&spi->dev, 514 hi8435_triggered_event_cleanup, 515 idev); 516 if (ret) 517 return ret; 518 519 return devm_iio_device_register(&spi->dev, idev); 520 } 521 522 static const struct of_device_id hi8435_dt_ids[] = { 523 { .compatible = "holt,hi8435" }, 524 { } 525 }; 526 MODULE_DEVICE_TABLE(of, hi8435_dt_ids); 527 528 static const struct spi_device_id hi8435_id[] = { 529 { .name = "hi8435" }, 530 { } 531 }; 532 MODULE_DEVICE_TABLE(spi, hi8435_id); 533 534 static struct spi_driver hi8435_driver = { 535 .driver = { 536 .name = "hi8435", 537 .of_match_table = hi8435_dt_ids, 538 }, 539 .probe = hi8435_probe, 540 .id_table = hi8435_id, 541 }; 542 module_spi_driver(hi8435_driver); 543 544 MODULE_LICENSE("GPL"); 545 MODULE_AUTHOR("Vladimir Barinov"); 546 MODULE_DESCRIPTION("HI-8435 threshold detector"); 547