1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <mpa@pengutronix.de> 4 * 5 * This is the driver for the imx25 GCQ (Generic Conversion Queue) 6 * connected to the imx25 ADC. 7 */ 8 9 #include <dt-bindings/iio/adc/fsl-imx25-gcq.h> 10 #include <linux/clk.h> 11 #include <linux/iio/iio.h> 12 #include <linux/interrupt.h> 13 #include <linux/mfd/imx25-tsadc.h> 14 #include <linux/module.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 21 #define MX25_GCQ_TIMEOUT (msecs_to_jiffies(2000)) 22 23 static const char * const driver_name = "mx25-gcq"; 24 25 enum mx25_gcq_cfgs { 26 MX25_CFG_XP = 0, 27 MX25_CFG_YP, 28 MX25_CFG_XN, 29 MX25_CFG_YN, 30 MX25_CFG_WIPER, 31 MX25_CFG_INAUX0, 32 MX25_CFG_INAUX1, 33 MX25_CFG_INAUX2, 34 MX25_NUM_CFGS, 35 }; 36 37 struct mx25_gcq_priv { 38 struct regmap *regs; 39 struct completion completed; 40 struct clk *clk; 41 int irq; 42 struct regulator *vref[4]; 43 u32 channel_vref_mv[MX25_NUM_CFGS]; 44 /* 45 * Lock to protect the device state during a potential concurrent 46 * read access from userspace. Reading a raw value requires a sequence 47 * of register writes, then a wait for a completion callback, 48 * and finally a register read, during which userspace could issue 49 * another read request. This lock protects a read access from 50 * ocurring before another one has finished. 51 */ 52 struct mutex lock; 53 }; 54 55 #define MX25_CQG_CHAN(chan, id) {\ 56 .type = IIO_VOLTAGE,\ 57 .indexed = 1,\ 58 .channel = chan,\ 59 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 60 BIT(IIO_CHAN_INFO_SCALE),\ 61 .datasheet_name = id,\ 62 } 63 64 static const struct iio_chan_spec mx25_gcq_channels[MX25_NUM_CFGS] = { 65 MX25_CQG_CHAN(MX25_CFG_XP, "xp"), 66 MX25_CQG_CHAN(MX25_CFG_YP, "yp"), 67 MX25_CQG_CHAN(MX25_CFG_XN, "xn"), 68 MX25_CQG_CHAN(MX25_CFG_YN, "yn"), 69 MX25_CQG_CHAN(MX25_CFG_WIPER, "wiper"), 70 MX25_CQG_CHAN(MX25_CFG_INAUX0, "inaux0"), 71 MX25_CQG_CHAN(MX25_CFG_INAUX1, "inaux1"), 72 MX25_CQG_CHAN(MX25_CFG_INAUX2, "inaux2"), 73 }; 74 75 static const char * const mx25_gcq_refp_names[] = { 76 [MX25_ADC_REFP_YP] = "yp", 77 [MX25_ADC_REFP_XP] = "xp", 78 [MX25_ADC_REFP_INT] = "int", 79 [MX25_ADC_REFP_EXT] = "ext", 80 }; 81 82 static irqreturn_t mx25_gcq_irq(int irq, void *data) 83 { 84 struct mx25_gcq_priv *priv = data; 85 u32 stats; 86 87 regmap_read(priv->regs, MX25_ADCQ_SR, &stats); 88 89 if (stats & MX25_ADCQ_SR_EOQ) { 90 regmap_update_bits(priv->regs, MX25_ADCQ_MR, 91 MX25_ADCQ_MR_EOQ_IRQ, MX25_ADCQ_MR_EOQ_IRQ); 92 complete(&priv->completed); 93 } 94 95 /* Disable conversion queue run */ 96 regmap_update_bits(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_FQS, 0); 97 98 /* Acknowledge all possible irqs */ 99 regmap_write(priv->regs, MX25_ADCQ_SR, MX25_ADCQ_SR_FRR | 100 MX25_ADCQ_SR_FUR | MX25_ADCQ_SR_FOR | 101 MX25_ADCQ_SR_EOQ | MX25_ADCQ_SR_PD); 102 103 return IRQ_HANDLED; 104 } 105 106 static int mx25_gcq_get_raw_value(struct device *dev, 107 struct iio_chan_spec const *chan, 108 struct mx25_gcq_priv *priv, 109 int *val) 110 { 111 long time_left; 112 u32 data; 113 114 /* Setup the configuration we want to use */ 115 regmap_write(priv->regs, MX25_ADCQ_ITEM_7_0, 116 MX25_ADCQ_ITEM(0, chan->channel)); 117 118 regmap_update_bits(priv->regs, MX25_ADCQ_MR, MX25_ADCQ_MR_EOQ_IRQ, 0); 119 120 /* Trigger queue for one run */ 121 regmap_update_bits(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_FQS, 122 MX25_ADCQ_CR_FQS); 123 124 time_left = wait_for_completion_interruptible_timeout( 125 &priv->completed, MX25_GCQ_TIMEOUT); 126 if (time_left < 0) { 127 dev_err(dev, "ADC wait for measurement failed\n"); 128 return time_left; 129 } else if (time_left == 0) { 130 dev_err(dev, "ADC timed out\n"); 131 return -ETIMEDOUT; 132 } 133 134 regmap_read(priv->regs, MX25_ADCQ_FIFO, &data); 135 136 *val = MX25_ADCQ_FIFO_DATA(data); 137 138 return IIO_VAL_INT; 139 } 140 141 static int mx25_gcq_read_raw(struct iio_dev *indio_dev, 142 struct iio_chan_spec const *chan, int *val, 143 int *val2, long mask) 144 { 145 struct mx25_gcq_priv *priv = iio_priv(indio_dev); 146 int ret; 147 148 switch (mask) { 149 case IIO_CHAN_INFO_RAW: 150 mutex_lock(&priv->lock); 151 ret = mx25_gcq_get_raw_value(&indio_dev->dev, chan, priv, val); 152 mutex_unlock(&priv->lock); 153 return ret; 154 155 case IIO_CHAN_INFO_SCALE: 156 *val = priv->channel_vref_mv[chan->channel]; 157 *val2 = 12; 158 return IIO_VAL_FRACTIONAL_LOG2; 159 160 default: 161 return -EINVAL; 162 } 163 } 164 165 static const struct iio_info mx25_gcq_iio_info = { 166 .read_raw = mx25_gcq_read_raw, 167 }; 168 169 static const struct regmap_config mx25_gcq_regconfig = { 170 .max_register = 0x5c, 171 .reg_bits = 32, 172 .val_bits = 32, 173 .reg_stride = 4, 174 }; 175 176 static int mx25_gcq_ext_regulator_setup(struct device *dev, 177 struct mx25_gcq_priv *priv, u32 refp) 178 { 179 char reg_name[12]; 180 int ret; 181 182 if (priv->vref[refp]) 183 return 0; 184 185 ret = snprintf(reg_name, sizeof(reg_name), "vref-%s", 186 mx25_gcq_refp_names[refp]); 187 if (ret < 0) 188 return ret; 189 190 priv->vref[refp] = devm_regulator_get_optional(dev, reg_name); 191 if (IS_ERR(priv->vref[refp])) 192 return dev_err_probe(dev, PTR_ERR(priv->vref[refp]), 193 "Error, trying to use external voltage reference without a %s regulator.", 194 reg_name); 195 196 return 0; 197 } 198 199 static int mx25_gcq_setup_cfgs(struct platform_device *pdev, 200 struct mx25_gcq_priv *priv) 201 { 202 struct device *dev = &pdev->dev; 203 int ret, i; 204 205 /* 206 * Setup all configurations registers with a default conversion 207 * configuration for each input 208 */ 209 for (i = 0; i < MX25_NUM_CFGS; ++i) 210 regmap_write(priv->regs, MX25_ADCQ_CFG(i), 211 MX25_ADCQ_CFG_YPLL_OFF | 212 MX25_ADCQ_CFG_XNUR_OFF | 213 MX25_ADCQ_CFG_XPUL_OFF | 214 MX25_ADCQ_CFG_REFP_INT | 215 MX25_ADCQ_CFG_IN(i) | 216 MX25_ADCQ_CFG_REFN_NGND2); 217 218 device_for_each_child_node_scoped(dev, child) { 219 u32 reg; 220 u32 refp = MX25_ADCQ_CFG_REFP_INT; 221 u32 refn = MX25_ADCQ_CFG_REFN_NGND2; 222 223 ret = fwnode_property_read_u32(child, "reg", ®); 224 if (ret) 225 return dev_err_probe(dev, ret, 226 "Failed to get reg property\n"); 227 228 if (reg >= MX25_NUM_CFGS) 229 return dev_err_probe(dev, -EINVAL, 230 "reg value is greater than the number of available configuration registers\n"); 231 232 fwnode_property_read_u32(child, "fsl,adc-refp", &refp); 233 fwnode_property_read_u32(child, "fsl,adc-refn", &refn); 234 235 switch (refp) { 236 case MX25_ADC_REFP_EXT: 237 case MX25_ADC_REFP_XP: 238 case MX25_ADC_REFP_YP: 239 ret = mx25_gcq_ext_regulator_setup(&pdev->dev, priv, refp); 240 if (ret) 241 return ret; 242 priv->channel_vref_mv[reg] = 243 regulator_get_voltage(priv->vref[refp]); 244 /* Conversion from uV to mV */ 245 priv->channel_vref_mv[reg] /= 1000; 246 break; 247 case MX25_ADC_REFP_INT: 248 priv->channel_vref_mv[reg] = 2500; 249 break; 250 default: 251 return dev_err_probe(dev, -EINVAL, 252 "Invalid positive reference %d\n", refp); 253 } 254 255 /* 256 * Shift the read values to the correct positions within the 257 * register. 258 */ 259 refp = MX25_ADCQ_CFG_REFP(refp); 260 refn = MX25_ADCQ_CFG_REFN(refn); 261 262 if ((refp & MX25_ADCQ_CFG_REFP_MASK) != refp) 263 return dev_err_probe(dev, -EINVAL, 264 "Invalid fsl,adc-refp property value\n"); 265 266 if ((refn & MX25_ADCQ_CFG_REFN_MASK) != refn) 267 return dev_err_probe(dev, -EINVAL, 268 "Invalid fsl,adc-refn property value\n"); 269 270 regmap_update_bits(priv->regs, MX25_ADCQ_CFG(reg), 271 MX25_ADCQ_CFG_REFP_MASK | 272 MX25_ADCQ_CFG_REFN_MASK, 273 refp | refn); 274 } 275 regmap_update_bits(priv->regs, MX25_ADCQ_CR, 276 MX25_ADCQ_CR_FRST | MX25_ADCQ_CR_QRST, 277 MX25_ADCQ_CR_FRST | MX25_ADCQ_CR_QRST); 278 279 regmap_write(priv->regs, MX25_ADCQ_CR, 280 MX25_ADCQ_CR_PDMSK | MX25_ADCQ_CR_QSM_FQS); 281 282 return 0; 283 } 284 285 static void mx25_gcq_reg_disable(void *reg) 286 { 287 regulator_disable(reg); 288 } 289 290 /* Custom handling needed as this driver doesn't own the clock */ 291 static void mx25_gcq_clk_disable(void *clk) 292 { 293 clk_disable_unprepare(clk); 294 } 295 296 static int mx25_gcq_probe(struct platform_device *pdev) 297 { 298 struct iio_dev *indio_dev; 299 struct mx25_gcq_priv *priv; 300 struct mx25_tsadc *tsadc = dev_get_drvdata(pdev->dev.parent); 301 struct device *dev = &pdev->dev; 302 void __iomem *mem; 303 int ret; 304 int i; 305 306 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv)); 307 if (!indio_dev) 308 return -ENOMEM; 309 310 priv = iio_priv(indio_dev); 311 312 mem = devm_platform_ioremap_resource(pdev, 0); 313 if (IS_ERR(mem)) 314 return PTR_ERR(mem); 315 316 priv->regs = devm_regmap_init_mmio(dev, mem, &mx25_gcq_regconfig); 317 if (IS_ERR(priv->regs)) 318 return dev_err_probe(dev, PTR_ERR(priv->regs), 319 "Failed to initialize regmap\n"); 320 321 mutex_init(&priv->lock); 322 323 init_completion(&priv->completed); 324 325 ret = mx25_gcq_setup_cfgs(pdev, priv); 326 if (ret) 327 return ret; 328 329 for (i = 0; i != 4; ++i) { 330 if (!priv->vref[i]) 331 continue; 332 333 ret = regulator_enable(priv->vref[i]); 334 if (ret) 335 return ret; 336 337 ret = devm_add_action_or_reset(dev, mx25_gcq_reg_disable, 338 priv->vref[i]); 339 if (ret) 340 return ret; 341 } 342 343 priv->clk = tsadc->clk; 344 ret = clk_prepare_enable(priv->clk); 345 if (ret) 346 return dev_err_probe(dev, ret, "Failed to enable clock\n"); 347 348 ret = devm_add_action_or_reset(dev, mx25_gcq_clk_disable, 349 priv->clk); 350 if (ret) 351 return ret; 352 353 ret = platform_get_irq(pdev, 0); 354 if (ret < 0) 355 return ret; 356 357 priv->irq = ret; 358 ret = devm_request_irq(dev, priv->irq, mx25_gcq_irq, 0, pdev->name, 359 priv); 360 if (ret) 361 return dev_err_probe(dev, ret, "Failed requesting IRQ\n"); 362 363 indio_dev->channels = mx25_gcq_channels; 364 indio_dev->num_channels = ARRAY_SIZE(mx25_gcq_channels); 365 indio_dev->info = &mx25_gcq_iio_info; 366 indio_dev->name = driver_name; 367 368 ret = devm_iio_device_register(dev, indio_dev); 369 if (ret) 370 return dev_err_probe(dev, ret, "Failed to register iio device\n"); 371 372 return 0; 373 } 374 375 static const struct of_device_id mx25_gcq_ids[] = { 376 { .compatible = "fsl,imx25-gcq", }, 377 { /* Sentinel */ } 378 }; 379 MODULE_DEVICE_TABLE(of, mx25_gcq_ids); 380 381 static struct platform_driver mx25_gcq_driver = { 382 .driver = { 383 .name = "mx25-gcq", 384 .of_match_table = mx25_gcq_ids, 385 }, 386 .probe = mx25_gcq_probe, 387 }; 388 module_platform_driver(mx25_gcq_driver); 389 390 MODULE_DESCRIPTION("ADC driver for Freescale mx25"); 391 MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>"); 392 MODULE_LICENSE("GPL v2"); 393