1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel ADC driver for SAMA5D2 devices and compatible. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 * 2021 Microchip Technology, Inc. and its subsidiaries 8 * 2021 Eugen Hristev <eugen.hristev@microchip.com> 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/cleanup.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/dmaengine.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/platform_device.h> 22 #include <linux/property.h> 23 #include <linux/sched.h> 24 #include <linux/units.h> 25 #include <linux/wait.h> 26 #include <linux/iio/iio.h> 27 #include <linux/iio/sysfs.h> 28 #include <linux/iio/buffer.h> 29 #include <linux/iio/trigger.h> 30 #include <linux/iio/trigger_consumer.h> 31 #include <linux/iio/triggered_buffer.h> 32 #include <linux/nvmem-consumer.h> 33 #include <linux/pinctrl/consumer.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/regulator/consumer.h> 36 37 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 38 39 struct at91_adc_reg_layout { 40 /* Control Register */ 41 u16 CR; 42 /* Software Reset */ 43 #define AT91_SAMA5D2_CR_SWRST BIT(0) 44 /* Start Conversion */ 45 #define AT91_SAMA5D2_CR_START BIT(1) 46 /* Touchscreen Calibration */ 47 #define AT91_SAMA5D2_CR_TSCALIB BIT(2) 48 /* Comparison Restart */ 49 #define AT91_SAMA5D2_CR_CMPRST BIT(4) 50 51 /* Mode Register */ 52 u16 MR; 53 /* Trigger Selection */ 54 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1) 55 /* ADTRG */ 56 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0 57 /* TIOA0 */ 58 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1 59 /* TIOA1 */ 60 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2 61 /* TIOA2 */ 62 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3 63 /* PWM event line 0 */ 64 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4 65 /* PWM event line 1 */ 66 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5 67 /* TIOA3 */ 68 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6 69 /* RTCOUT0 */ 70 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7 71 /* Sleep Mode */ 72 #define AT91_SAMA5D2_MR_SLEEP BIT(5) 73 /* Fast Wake Up */ 74 #define AT91_SAMA5D2_MR_FWUP BIT(6) 75 /* Prescaler Rate Selection */ 76 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET) 77 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8 78 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff 79 #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8) 80 /* Startup Time */ 81 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16) 82 #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16) 83 /* Minimum startup time for temperature sensor */ 84 #define AT91_SAMA5D2_MR_STARTUP_TS_MIN (50) 85 /* Analog Change */ 86 #define AT91_SAMA5D2_MR_ANACH BIT(23) 87 /* Tracking Time */ 88 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24) 89 #define AT91_SAMA5D2_MR_TRACKTIM_TS 6 90 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xf 91 /* Transfer Time */ 92 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28) 93 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3 94 /* Use Sequence Enable */ 95 #define AT91_SAMA5D2_MR_USEQ BIT(31) 96 97 /* Channel Sequence Register 1 */ 98 u16 SEQR1; 99 /* Channel Sequence Register 2 */ 100 u16 SEQR2; 101 /* Channel Enable Register */ 102 u16 CHER; 103 /* Channel Disable Register */ 104 u16 CHDR; 105 /* Channel Status Register */ 106 u16 CHSR; 107 /* Last Converted Data Register */ 108 u16 LCDR; 109 /* Interrupt Enable Register */ 110 u16 IER; 111 /* Interrupt Enable Register - TS X measurement ready */ 112 #define AT91_SAMA5D2_IER_XRDY BIT(20) 113 /* Interrupt Enable Register - TS Y measurement ready */ 114 #define AT91_SAMA5D2_IER_YRDY BIT(21) 115 /* Interrupt Enable Register - TS pressure measurement ready */ 116 #define AT91_SAMA5D2_IER_PRDY BIT(22) 117 /* Interrupt Enable Register - Data ready */ 118 #define AT91_SAMA5D2_IER_DRDY BIT(24) 119 /* Interrupt Enable Register - general overrun error */ 120 #define AT91_SAMA5D2_IER_GOVRE BIT(25) 121 /* Interrupt Enable Register - Pen detect */ 122 #define AT91_SAMA5D2_IER_PEN BIT(29) 123 /* Interrupt Enable Register - No pen detect */ 124 #define AT91_SAMA5D2_IER_NOPEN BIT(30) 125 126 /* Interrupt Disable Register */ 127 u16 IDR; 128 /* Interrupt Mask Register */ 129 u16 IMR; 130 /* Interrupt Status Register */ 131 u16 ISR; 132 /* End of Conversion Interrupt Enable Register */ 133 u16 EOC_IER; 134 /* End of Conversion Interrupt Disable Register */ 135 u16 EOC_IDR; 136 /* End of Conversion Interrupt Mask Register */ 137 u16 EOC_IMR; 138 /* End of Conversion Interrupt Status Register */ 139 u16 EOC_ISR; 140 /* Interrupt Status Register - Pen touching sense status */ 141 #define AT91_SAMA5D2_ISR_PENS BIT(31) 142 /* Last Channel Trigger Mode Register */ 143 u16 LCTMR; 144 /* Last Channel Compare Window Register */ 145 u16 LCCWR; 146 /* Overrun Status Register */ 147 u16 OVER; 148 /* Extended Mode Register */ 149 u16 EMR; 150 /* Extended Mode Register - Oversampling rate */ 151 #define AT91_SAMA5D2_EMR_OSR(V, M) (((V) << 16) & (M)) 152 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0 153 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1 154 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2 155 #define AT91_SAMA5D2_EMR_OSR_64SAMPLES 3 156 #define AT91_SAMA5D2_EMR_OSR_256SAMPLES 4 157 158 /* Extended Mode Register - TRACKX */ 159 #define AT91_SAMA5D2_TRACKX_MASK GENMASK(23, 22) 160 #define AT91_SAMA5D2_TRACKX(x) (((x) << 22) & \ 161 AT91_SAMA5D2_TRACKX_MASK) 162 /* TRACKX for temperature sensor. */ 163 #define AT91_SAMA5D2_TRACKX_TS (1) 164 165 /* Extended Mode Register - Averaging on single trigger event */ 166 #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) 167 168 /* Compare Window Register */ 169 u16 CWR; 170 /* Channel Gain Register */ 171 u16 CGR; 172 /* Channel Offset Register */ 173 u16 COR; 174 /* Channel Offset Register differential offset - constant, not a register */ 175 u16 COR_diff_offset; 176 /* Analog Control Register */ 177 u16 ACR; 178 /* Analog Control Register - Pen detect sensitivity mask */ 179 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0) 180 /* Analog Control Register - Source last channel */ 181 #define AT91_SAMA5D2_ACR_SRCLCH BIT(16) 182 183 /* Touchscreen Mode Register */ 184 u16 TSMR; 185 /* Touchscreen Mode Register - No touch mode */ 186 #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0 187 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */ 188 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1 189 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */ 190 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2 191 /* Touchscreen Mode Register - 5 wire screen */ 192 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3 193 /* Touchscreen Mode Register - Average samples mask */ 194 #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4) 195 /* Touchscreen Mode Register - Average samples */ 196 #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4) 197 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */ 198 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8) 199 /* Touchscreen Mode Register - Touch/trigger frequency ratio */ 200 #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8) 201 /* Touchscreen Mode Register - Pen Debounce Time mask */ 202 #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28) 203 /* Touchscreen Mode Register - Pen Debounce Time */ 204 #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28) 205 /* Touchscreen Mode Register - No DMA for touch measurements */ 206 #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22) 207 /* Touchscreen Mode Register - Disable pen detection */ 208 #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24) 209 /* Touchscreen Mode Register - Enable pen detection */ 210 #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24) 211 212 /* Touchscreen X Position Register */ 213 u16 XPOSR; 214 /* Touchscreen Y Position Register */ 215 u16 YPOSR; 216 /* Touchscreen Pressure Register */ 217 u16 PRESSR; 218 /* Trigger Register */ 219 u16 TRGR; 220 /* Mask for TRGMOD field of TRGR register */ 221 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0) 222 /* No trigger, only software trigger can start conversions */ 223 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0 224 /* Trigger Mode external trigger rising edge */ 225 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1 226 /* Trigger Mode external trigger falling edge */ 227 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2 228 /* Trigger Mode external trigger any edge */ 229 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3 230 /* Trigger Mode internal periodic */ 231 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5 232 /* Trigger Mode - trigger period mask */ 233 #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16) 234 /* Trigger Mode - trigger period */ 235 #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16) 236 237 /* Correction Select Register */ 238 u16 COSR; 239 /* Correction Value Register */ 240 u16 CVR; 241 /* Channel Error Correction Register */ 242 u16 CECR; 243 /* Write Protection Mode Register */ 244 u16 WPMR; 245 /* Write Protection Status Register */ 246 u16 WPSR; 247 /* Version Register */ 248 u16 VERSION; 249 /* Temperature Sensor Mode Register */ 250 u16 TEMPMR; 251 /* Temperature Sensor Mode - Temperature sensor on */ 252 #define AT91_SAMA5D2_TEMPMR_TEMPON BIT(0) 253 }; 254 255 static const struct at91_adc_reg_layout sama5d2_layout = { 256 .CR = 0x00, 257 .MR = 0x04, 258 .SEQR1 = 0x08, 259 .SEQR2 = 0x0c, 260 .CHER = 0x10, 261 .CHDR = 0x14, 262 .CHSR = 0x18, 263 .LCDR = 0x20, 264 .IER = 0x24, 265 .IDR = 0x28, 266 .IMR = 0x2c, 267 .ISR = 0x30, 268 .LCTMR = 0x34, 269 .LCCWR = 0x38, 270 .OVER = 0x3c, 271 .EMR = 0x40, 272 .CWR = 0x44, 273 .CGR = 0x48, 274 .COR = 0x4c, 275 .COR_diff_offset = 16, 276 .ACR = 0x94, 277 .TSMR = 0xb0, 278 .XPOSR = 0xb4, 279 .YPOSR = 0xb8, 280 .PRESSR = 0xbc, 281 .TRGR = 0xc0, 282 .COSR = 0xd0, 283 .CVR = 0xd4, 284 .CECR = 0xd8, 285 .WPMR = 0xe4, 286 .WPSR = 0xe8, 287 .VERSION = 0xfc, 288 }; 289 290 static const struct at91_adc_reg_layout sama7g5_layout = { 291 .CR = 0x00, 292 .MR = 0x04, 293 .SEQR1 = 0x08, 294 .SEQR2 = 0x0c, 295 .CHER = 0x10, 296 .CHDR = 0x14, 297 .CHSR = 0x18, 298 .LCDR = 0x20, 299 .IER = 0x24, 300 .IDR = 0x28, 301 .IMR = 0x2c, 302 .ISR = 0x30, 303 .EOC_IER = 0x34, 304 .EOC_IDR = 0x38, 305 .EOC_IMR = 0x3c, 306 .EOC_ISR = 0x40, 307 .TEMPMR = 0x44, 308 .OVER = 0x4c, 309 .EMR = 0x50, 310 .CWR = 0x54, 311 .COR = 0x5c, 312 .COR_diff_offset = 0, 313 .ACR = 0xe0, 314 .TRGR = 0x100, 315 .COSR = 0x104, 316 .CVR = 0x108, 317 .CECR = 0x10c, 318 .WPMR = 0x118, 319 .WPSR = 0x11c, 320 .VERSION = 0x130, 321 }; 322 323 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ 324 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200 325 326 #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0) 327 328 #define AT91_SAMA5D2_MAX_POS_BITS 12 329 330 #define AT91_HWFIFO_MAX_SIZE_STR "128" 331 #define AT91_HWFIFO_MAX_SIZE 128 332 333 #define AT91_SAMA_CHAN_SINGLE(index, num, addr, rbits) \ 334 { \ 335 .type = IIO_VOLTAGE, \ 336 .channel = num, \ 337 .address = addr, \ 338 .scan_index = index, \ 339 .scan_type = { \ 340 .sign = 'u', \ 341 .realbits = rbits, \ 342 .storagebits = 16, \ 343 }, \ 344 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 345 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 346 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 347 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 348 .info_mask_shared_by_all_available = \ 349 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 350 .datasheet_name = "CH"#num, \ 351 .indexed = 1, \ 352 } 353 354 #define AT91_SAMA5D2_CHAN_SINGLE(index, num, addr) \ 355 AT91_SAMA_CHAN_SINGLE(index, num, addr, 14) 356 357 #define AT91_SAMA7G5_CHAN_SINGLE(index, num, addr) \ 358 AT91_SAMA_CHAN_SINGLE(index, num, addr, 16) 359 360 #define AT91_SAMA_CHAN_DIFF(index, num, num2, addr, rbits) \ 361 { \ 362 .type = IIO_VOLTAGE, \ 363 .differential = 1, \ 364 .channel = num, \ 365 .channel2 = num2, \ 366 .address = addr, \ 367 .scan_index = index, \ 368 .scan_type = { \ 369 .sign = 's', \ 370 .realbits = rbits, \ 371 .storagebits = 16, \ 372 }, \ 373 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 374 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 375 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 376 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 377 .info_mask_shared_by_all_available = \ 378 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 379 .datasheet_name = "CH"#num"-CH"#num2, \ 380 .indexed = 1, \ 381 } 382 383 #define AT91_SAMA5D2_CHAN_DIFF(index, num, num2, addr) \ 384 AT91_SAMA_CHAN_DIFF(index, num, num2, addr, 14) 385 386 #define AT91_SAMA7G5_CHAN_DIFF(index, num, num2, addr) \ 387 AT91_SAMA_CHAN_DIFF(index, num, num2, addr, 16) 388 389 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \ 390 { \ 391 .type = IIO_POSITIONRELATIVE, \ 392 .modified = 1, \ 393 .channel = num, \ 394 .channel2 = mod, \ 395 .scan_index = num, \ 396 .scan_type = { \ 397 .sign = 'u', \ 398 .realbits = 12, \ 399 .storagebits = 16, \ 400 }, \ 401 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 402 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 403 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 404 .info_mask_shared_by_all_available = \ 405 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 406 .datasheet_name = name, \ 407 } 408 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \ 409 { \ 410 .type = IIO_PRESSURE, \ 411 .channel = num, \ 412 .scan_index = num, \ 413 .scan_type = { \ 414 .sign = 'u', \ 415 .realbits = 12, \ 416 .storagebits = 16, \ 417 }, \ 418 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 419 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 420 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 421 .info_mask_shared_by_all_available = \ 422 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 423 .datasheet_name = name, \ 424 } 425 426 #define AT91_SAMA5D2_CHAN_TEMP(num, name, addr) \ 427 { \ 428 .type = IIO_TEMP, \ 429 .channel = num, \ 430 .address = addr, \ 431 .scan_index = num, \ 432 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 433 .info_mask_shared_by_all = \ 434 BIT(IIO_CHAN_INFO_PROCESSED) | \ 435 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 436 .info_mask_shared_by_all_available = \ 437 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 438 .datasheet_name = name, \ 439 } 440 441 #define at91_adc_readl(st, reg) \ 442 readl_relaxed((st)->base + (st)->soc_info.platform->layout->reg) 443 #define at91_adc_read_chan(st, reg) \ 444 readl_relaxed((st)->base + reg) 445 #define at91_adc_writel(st, reg, val) \ 446 writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg) 447 448 /** 449 * struct at91_adc_platform - at91-sama5d2 platform information struct 450 * @layout: pointer to the reg layout struct 451 * @adc_channels: pointer to an array of channels for registering in 452 * the iio subsystem 453 * @nr_channels: number of physical channels available 454 * @touch_chan_x: index of the touchscreen X channel 455 * @touch_chan_y: index of the touchscreen Y channel 456 * @touch_chan_p: index of the touchscreen P channel 457 * @max_channels: number of total channels 458 * @max_index: highest channel index (highest index may be higher 459 * than the total channel number) 460 * @hw_trig_cnt: number of possible hardware triggers 461 * @osr_mask: oversampling ratio bitmask on EMR register 462 * @oversampling_avail: available oversampling values 463 * @oversampling_avail_no: number of available oversampling values 464 * @chan_realbits: realbits for registered channels 465 * @temp_chan: temperature channel index 466 * @temp_sensor: temperature sensor supported 467 */ 468 struct at91_adc_platform { 469 const struct at91_adc_reg_layout *layout; 470 const struct iio_chan_spec (*adc_channels)[]; 471 unsigned int nr_channels; 472 unsigned int touch_chan_x; 473 unsigned int touch_chan_y; 474 unsigned int touch_chan_p; 475 unsigned int max_channels; 476 unsigned int max_index; 477 unsigned int hw_trig_cnt; 478 unsigned int osr_mask; 479 unsigned int oversampling_avail[5]; 480 unsigned int oversampling_avail_no; 481 unsigned int chan_realbits; 482 unsigned int temp_chan; 483 bool temp_sensor; 484 }; 485 486 /** 487 * struct at91_adc_temp_sensor_clb - at91-sama5d2 temperature sensor 488 * calibration data structure 489 * @p1: P1 calibration temperature 490 * @p4: P4 calibration voltage 491 * @p6: P6 calibration voltage 492 */ 493 struct at91_adc_temp_sensor_clb { 494 u32 p1; 495 u32 p4; 496 u32 p6; 497 }; 498 499 /** 500 * enum at91_adc_ts_clb_idx - calibration indexes in NVMEM buffer 501 * @AT91_ADC_TS_CLB_IDX_P1: index for P1 502 * @AT91_ADC_TS_CLB_IDX_P4: index for P4 503 * @AT91_ADC_TS_CLB_IDX_P6: index for P6 504 * @AT91_ADC_TS_CLB_IDX_MAX: max index for temperature calibration packet in OTP 505 */ 506 enum at91_adc_ts_clb_idx { 507 AT91_ADC_TS_CLB_IDX_P1 = 2, 508 AT91_ADC_TS_CLB_IDX_P4 = 5, 509 AT91_ADC_TS_CLB_IDX_P6 = 7, 510 AT91_ADC_TS_CLB_IDX_MAX = 19, 511 }; 512 513 /* Temperature sensor calibration - Vtemp voltage sensitivity to temperature. */ 514 #define AT91_ADC_TS_VTEMP_DT (2080U) 515 516 /** 517 * struct at91_adc_soc_info - at91-sama5d2 soc information struct 518 * @startup_time: device startup time 519 * @min_sample_rate: minimum sample rate in Hz 520 * @max_sample_rate: maximum sample rate in Hz 521 * @platform: pointer to the platform structure 522 * @temp_sensor_clb: temperature sensor calibration data structure 523 */ 524 struct at91_adc_soc_info { 525 unsigned startup_time; 526 unsigned min_sample_rate; 527 unsigned max_sample_rate; 528 const struct at91_adc_platform *platform; 529 struct at91_adc_temp_sensor_clb temp_sensor_clb; 530 }; 531 532 struct at91_adc_trigger { 533 char *name; 534 unsigned int trgmod_value; 535 unsigned int edge_type; 536 bool hw_trig; 537 }; 538 539 /** 540 * struct at91_adc_dma - at91-sama5d2 dma information struct 541 * @dma_chan: the dma channel acquired 542 * @rx_buf: dma coherent allocated area 543 * @rx_dma_buf: dma handler for the buffer 544 * @phys_addr: physical address of the ADC base register 545 * @buf_idx: index inside the dma buffer where reading was last done 546 * @rx_buf_sz: size of buffer used by DMA operation 547 * @watermark: number of conversions to copy before DMA triggers irq 548 * @dma_ts: hold the start timestamp of dma operation 549 */ 550 struct at91_adc_dma { 551 struct dma_chan *dma_chan; 552 u8 *rx_buf; 553 dma_addr_t rx_dma_buf; 554 phys_addr_t phys_addr; 555 int buf_idx; 556 int rx_buf_sz; 557 int watermark; 558 s64 dma_ts; 559 }; 560 561 /** 562 * struct at91_adc_touch - at91-sama5d2 touchscreen information struct 563 * @sample_period_val: the value for periodic trigger interval 564 * @touching: is the pen touching the screen or not 565 * @x_pos: temporary placeholder for pressure computation 566 * @channels_bitmask: bitmask with the touchscreen channels enabled 567 * @workq: workqueue for buffer data pushing 568 */ 569 struct at91_adc_touch { 570 u16 sample_period_val; 571 bool touching; 572 u16 x_pos; 573 unsigned long channels_bitmask; 574 struct work_struct workq; 575 }; 576 577 /** 578 * struct at91_adc_temp - at91-sama5d2 temperature information structure 579 * @sample_period_val: sample period value 580 * @saved_sample_rate: saved sample rate 581 * @saved_oversampling: saved oversampling 582 */ 583 struct at91_adc_temp { 584 u16 sample_period_val; 585 u16 saved_sample_rate; 586 u16 saved_oversampling; 587 }; 588 589 /* 590 * Buffer size requirements: 591 * No channels * bytes_per_channel(2) + timestamp bytes (8) 592 * Divided by 2 because we need half words. 593 * We assume 32 channels for now, has to be increased if needed. 594 * Nobody minds a buffer being too big. 595 */ 596 #define AT91_BUFFER_MAX_HWORDS ((32 * 2 + 8) / 2) 597 598 struct at91_adc_state { 599 void __iomem *base; 600 int irq; 601 struct clk *per_clk; 602 struct regulator *reg; 603 struct regulator *vref; 604 int vref_uv; 605 unsigned int current_sample_rate; 606 struct iio_trigger *trig; 607 const struct at91_adc_trigger *selected_trig; 608 const struct iio_chan_spec *chan; 609 bool conversion_done; 610 u32 conversion_value; 611 unsigned int oversampling_ratio; 612 struct at91_adc_soc_info soc_info; 613 wait_queue_head_t wq_data_available; 614 struct at91_adc_dma dma_st; 615 struct at91_adc_touch touch_st; 616 struct at91_adc_temp temp_st; 617 struct iio_dev *indio_dev; 618 struct device *dev; 619 /* Ensure naturally aligned timestamp */ 620 u16 buffer[AT91_BUFFER_MAX_HWORDS] __aligned(8); 621 /* 622 * lock to prevent concurrent 'single conversion' requests through 623 * sysfs. 624 */ 625 struct mutex lock; 626 }; 627 628 static const struct at91_adc_trigger at91_adc_trigger_list[] = { 629 { 630 .name = "external_rising", 631 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE, 632 .edge_type = IRQ_TYPE_EDGE_RISING, 633 .hw_trig = true, 634 }, 635 { 636 .name = "external_falling", 637 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL, 638 .edge_type = IRQ_TYPE_EDGE_FALLING, 639 .hw_trig = true, 640 }, 641 { 642 .name = "external_any", 643 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY, 644 .edge_type = IRQ_TYPE_EDGE_BOTH, 645 .hw_trig = true, 646 }, 647 { 648 .name = "software", 649 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER, 650 .edge_type = IRQ_TYPE_NONE, 651 .hw_trig = false, 652 }, 653 }; 654 655 static const struct iio_chan_spec at91_sama5d2_adc_channels[] = { 656 AT91_SAMA5D2_CHAN_SINGLE(0, 0, 0x50), 657 AT91_SAMA5D2_CHAN_SINGLE(1, 1, 0x54), 658 AT91_SAMA5D2_CHAN_SINGLE(2, 2, 0x58), 659 AT91_SAMA5D2_CHAN_SINGLE(3, 3, 0x5c), 660 AT91_SAMA5D2_CHAN_SINGLE(4, 4, 0x60), 661 AT91_SAMA5D2_CHAN_SINGLE(5, 5, 0x64), 662 AT91_SAMA5D2_CHAN_SINGLE(6, 6, 0x68), 663 AT91_SAMA5D2_CHAN_SINGLE(7, 7, 0x6c), 664 AT91_SAMA5D2_CHAN_SINGLE(8, 8, 0x70), 665 AT91_SAMA5D2_CHAN_SINGLE(9, 9, 0x74), 666 AT91_SAMA5D2_CHAN_SINGLE(10, 10, 0x78), 667 AT91_SAMA5D2_CHAN_SINGLE(11, 11, 0x7c), 668 /* original ABI has the differential channels with a gap in between */ 669 AT91_SAMA5D2_CHAN_DIFF(12, 0, 1, 0x50), 670 AT91_SAMA5D2_CHAN_DIFF(14, 2, 3, 0x58), 671 AT91_SAMA5D2_CHAN_DIFF(16, 4, 5, 0x60), 672 AT91_SAMA5D2_CHAN_DIFF(18, 6, 7, 0x68), 673 AT91_SAMA5D2_CHAN_DIFF(20, 8, 9, 0x70), 674 AT91_SAMA5D2_CHAN_DIFF(22, 10, 11, 0x78), 675 IIO_CHAN_SOFT_TIMESTAMP(23), 676 AT91_SAMA5D2_CHAN_TOUCH(24, "x", IIO_MOD_X), 677 AT91_SAMA5D2_CHAN_TOUCH(25, "y", IIO_MOD_Y), 678 AT91_SAMA5D2_CHAN_PRESSURE(26, "pressure"), 679 }; 680 681 static const struct iio_chan_spec at91_sama7g5_adc_channels[] = { 682 AT91_SAMA7G5_CHAN_SINGLE(0, 0, 0x60), 683 AT91_SAMA7G5_CHAN_SINGLE(1, 1, 0x64), 684 AT91_SAMA7G5_CHAN_SINGLE(2, 2, 0x68), 685 AT91_SAMA7G5_CHAN_SINGLE(3, 3, 0x6c), 686 AT91_SAMA7G5_CHAN_SINGLE(4, 4, 0x70), 687 AT91_SAMA7G5_CHAN_SINGLE(5, 5, 0x74), 688 AT91_SAMA7G5_CHAN_SINGLE(6, 6, 0x78), 689 AT91_SAMA7G5_CHAN_SINGLE(7, 7, 0x7c), 690 AT91_SAMA7G5_CHAN_SINGLE(8, 8, 0x80), 691 AT91_SAMA7G5_CHAN_SINGLE(9, 9, 0x84), 692 AT91_SAMA7G5_CHAN_SINGLE(10, 10, 0x88), 693 AT91_SAMA7G5_CHAN_SINGLE(11, 11, 0x8c), 694 AT91_SAMA7G5_CHAN_SINGLE(12, 12, 0x90), 695 AT91_SAMA7G5_CHAN_SINGLE(13, 13, 0x94), 696 AT91_SAMA7G5_CHAN_SINGLE(14, 14, 0x98), 697 AT91_SAMA7G5_CHAN_SINGLE(15, 15, 0x9c), 698 AT91_SAMA7G5_CHAN_DIFF(16, 0, 1, 0x60), 699 AT91_SAMA7G5_CHAN_DIFF(17, 2, 3, 0x68), 700 AT91_SAMA7G5_CHAN_DIFF(18, 4, 5, 0x70), 701 AT91_SAMA7G5_CHAN_DIFF(19, 6, 7, 0x78), 702 AT91_SAMA7G5_CHAN_DIFF(20, 8, 9, 0x80), 703 AT91_SAMA7G5_CHAN_DIFF(21, 10, 11, 0x88), 704 AT91_SAMA7G5_CHAN_DIFF(22, 12, 13, 0x90), 705 AT91_SAMA7G5_CHAN_DIFF(23, 14, 15, 0x98), 706 IIO_CHAN_SOFT_TIMESTAMP(24), 707 AT91_SAMA5D2_CHAN_TEMP(AT91_SAMA7G5_ADC_TEMP_CHANNEL, "temp", 0xdc), 708 }; 709 710 static const struct at91_adc_platform sama5d2_platform = { 711 .layout = &sama5d2_layout, 712 .adc_channels = &at91_sama5d2_adc_channels, 713 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12 714 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6 715 .nr_channels = AT91_SAMA5D2_SINGLE_CHAN_CNT + 716 AT91_SAMA5D2_DIFF_CHAN_CNT, 717 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 718 AT91_SAMA5D2_DIFF_CHAN_CNT * 2) 719 .touch_chan_x = AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 720 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1) 721 .touch_chan_y = AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 722 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1) 723 .touch_chan_p = AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 724 #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX 725 .max_channels = ARRAY_SIZE(at91_sama5d2_adc_channels), 726 .max_index = AT91_SAMA5D2_MAX_CHAN_IDX, 727 #define AT91_SAMA5D2_HW_TRIG_CNT 3 728 .hw_trig_cnt = AT91_SAMA5D2_HW_TRIG_CNT, 729 .osr_mask = GENMASK(17, 16), 730 .oversampling_avail = { 1, 4, 16, }, 731 .oversampling_avail_no = 3, 732 .chan_realbits = 14, 733 }; 734 735 static const struct at91_adc_platform sama7g5_platform = { 736 .layout = &sama7g5_layout, 737 .adc_channels = &at91_sama7g5_adc_channels, 738 #define AT91_SAMA7G5_SINGLE_CHAN_CNT 16 739 #define AT91_SAMA7G5_DIFF_CHAN_CNT 8 740 #define AT91_SAMA7G5_TEMP_CHAN_CNT 1 741 .nr_channels = AT91_SAMA7G5_SINGLE_CHAN_CNT + 742 AT91_SAMA7G5_DIFF_CHAN_CNT + 743 AT91_SAMA7G5_TEMP_CHAN_CNT, 744 #define AT91_SAMA7G5_MAX_CHAN_IDX (AT91_SAMA7G5_SINGLE_CHAN_CNT + \ 745 AT91_SAMA7G5_DIFF_CHAN_CNT + \ 746 AT91_SAMA7G5_TEMP_CHAN_CNT) 747 .max_channels = ARRAY_SIZE(at91_sama7g5_adc_channels), 748 .max_index = AT91_SAMA7G5_MAX_CHAN_IDX, 749 #define AT91_SAMA7G5_HW_TRIG_CNT 3 750 .hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT, 751 .osr_mask = GENMASK(18, 16), 752 .oversampling_avail = { 1, 4, 16, 64, 256, }, 753 .oversampling_avail_no = 5, 754 .chan_realbits = 16, 755 .temp_sensor = true, 756 .temp_chan = AT91_SAMA7G5_ADC_TEMP_CHANNEL, 757 }; 758 759 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) 760 { 761 int i; 762 763 for (i = 0; i < indio_dev->num_channels; i++) { 764 if (indio_dev->channels[i].scan_index == chan) 765 return i; 766 } 767 return -EINVAL; 768 } 769 770 static inline struct iio_chan_spec const * 771 at91_adc_chan_get(struct iio_dev *indio_dev, int chan) 772 { 773 int index = at91_adc_chan_xlate(indio_dev, chan); 774 775 if (index < 0) 776 return NULL; 777 return indio_dev->channels + index; 778 } 779 780 static inline int at91_adc_fwnode_xlate(struct iio_dev *indio_dev, 781 const struct fwnode_reference_args *iiospec) 782 { 783 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]); 784 } 785 786 static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) 787 { 788 u32 mask = 0; 789 u8 bit; 790 struct at91_adc_state *st = iio_priv(indio_dev); 791 792 for_each_set_bit(bit, indio_dev->active_scan_mask, 793 indio_dev->num_channels) { 794 struct iio_chan_spec const *chan = 795 at91_adc_chan_get(indio_dev, bit); 796 mask |= BIT(chan->channel); 797 } 798 799 return mask & GENMASK(st->soc_info.platform->nr_channels, 0); 800 } 801 802 static void at91_adc_cor(struct at91_adc_state *st, 803 struct iio_chan_spec const *chan) 804 { 805 u32 cor, cur_cor; 806 807 cor = BIT(chan->channel) | BIT(chan->channel2); 808 809 cur_cor = at91_adc_readl(st, COR); 810 cor <<= st->soc_info.platform->layout->COR_diff_offset; 811 if (chan->differential) 812 at91_adc_writel(st, COR, cur_cor | cor); 813 else 814 at91_adc_writel(st, COR, cur_cor & ~cor); 815 } 816 817 static void at91_adc_irq_status(struct at91_adc_state *st, u32 *status, 818 u32 *eoc) 819 { 820 *status = at91_adc_readl(st, ISR); 821 if (st->soc_info.platform->layout->EOC_ISR) 822 *eoc = at91_adc_readl(st, EOC_ISR); 823 else 824 *eoc = *status; 825 } 826 827 static void at91_adc_irq_mask(struct at91_adc_state *st, u32 *status, u32 *eoc) 828 { 829 *status = at91_adc_readl(st, IMR); 830 if (st->soc_info.platform->layout->EOC_IMR) 831 *eoc = at91_adc_readl(st, EOC_IMR); 832 else 833 *eoc = *status; 834 } 835 836 static void at91_adc_eoc_dis(struct at91_adc_state *st, unsigned int channel) 837 { 838 /* 839 * On some products having the EOC bits in a separate register, 840 * errata recommends not writing this register (EOC_IDR). 841 * On products having the EOC bits in the IDR register, it's fine to write it. 842 */ 843 if (!st->soc_info.platform->layout->EOC_IDR) 844 at91_adc_writel(st, IDR, BIT(channel)); 845 } 846 847 static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel) 848 { 849 if (!st->soc_info.platform->layout->EOC_IDR) 850 at91_adc_writel(st, IER, BIT(channel)); 851 else 852 at91_adc_writel(st, EOC_IER, BIT(channel)); 853 } 854 855 static int at91_adc_config_emr(struct at91_adc_state *st, 856 u32 oversampling_ratio, u32 trackx) 857 { 858 /* configure the extended mode register */ 859 unsigned int emr, osr; 860 unsigned int osr_mask = st->soc_info.platform->osr_mask; 861 int i, ret; 862 863 /* Check against supported oversampling values. */ 864 for (i = 0; i < st->soc_info.platform->oversampling_avail_no; i++) { 865 if (oversampling_ratio == st->soc_info.platform->oversampling_avail[i]) 866 break; 867 } 868 if (i == st->soc_info.platform->oversampling_avail_no) 869 return -EINVAL; 870 871 /* select oversampling ratio from configuration */ 872 switch (oversampling_ratio) { 873 case 1: 874 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES, 875 osr_mask); 876 break; 877 case 4: 878 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES, 879 osr_mask); 880 break; 881 case 16: 882 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES, 883 osr_mask); 884 break; 885 case 64: 886 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_64SAMPLES, 887 osr_mask); 888 break; 889 case 256: 890 osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_256SAMPLES, 891 osr_mask); 892 break; 893 } 894 895 ret = pm_runtime_resume_and_get(st->dev); 896 if (ret < 0) 897 return ret; 898 899 emr = at91_adc_readl(st, EMR); 900 /* select oversampling per single trigger event */ 901 emr |= AT91_SAMA5D2_EMR_ASTE(1); 902 /* delete leftover content if it's the case */ 903 emr &= ~(osr_mask | AT91_SAMA5D2_TRACKX_MASK); 904 /* Update osr and trackx. */ 905 emr |= osr | AT91_SAMA5D2_TRACKX(trackx); 906 at91_adc_writel(st, EMR, emr); 907 908 pm_runtime_mark_last_busy(st->dev); 909 pm_runtime_put_autosuspend(st->dev); 910 911 st->oversampling_ratio = oversampling_ratio; 912 913 return 0; 914 } 915 916 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) 917 { 918 int nbits, diff; 919 920 if (st->oversampling_ratio == 1) 921 nbits = 12; 922 else if (st->oversampling_ratio == 4) 923 nbits = 13; 924 else if (st->oversampling_ratio == 16) 925 nbits = 14; 926 else if (st->oversampling_ratio == 64) 927 nbits = 15; 928 else if (st->oversampling_ratio == 256) 929 nbits = 16; 930 else 931 /* Should not happen. */ 932 return -EINVAL; 933 934 /* 935 * We have nbits of real data and channel is registered as 936 * st->soc_info.platform->chan_realbits, so shift left diff bits. 937 */ 938 diff = st->soc_info.platform->chan_realbits - nbits; 939 *val <<= diff; 940 941 return IIO_VAL_INT; 942 } 943 944 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf, 945 int len) 946 { 947 int i = 0, val; 948 u16 *buf_u16 = (u16 *) buf; 949 950 /* 951 * We are converting each two bytes (each sample). 952 * First convert the byte based array to u16, and convert each sample 953 * separately. 954 * Each value is two bytes in an array of chars, so to not shift 955 * more than we need, save the value separately. 956 * len is in bytes, so divide by two to get number of samples. 957 */ 958 while (i < len / 2) { 959 val = buf_u16[i]; 960 at91_adc_adjust_val_osr(st, &val); 961 buf_u16[i] = val; 962 i++; 963 } 964 } 965 966 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state) 967 { 968 u32 clk_khz = st->current_sample_rate / 1000; 969 int i = 0, ret; 970 u16 pendbc; 971 u32 tsmr, acr; 972 973 if (state) { 974 ret = pm_runtime_resume_and_get(st->dev); 975 if (ret < 0) 976 return ret; 977 } else { 978 /* disabling touch IRQs and setting mode to no touch enabled */ 979 at91_adc_writel(st, IDR, 980 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN); 981 at91_adc_writel(st, TSMR, 0); 982 983 pm_runtime_mark_last_busy(st->dev); 984 pm_runtime_put_autosuspend(st->dev); 985 return 0; 986 } 987 /* 988 * debounce time is in microseconds, we need it in milliseconds to 989 * multiply with kilohertz, so, divide by 1000, but after the multiply. 990 * round up to make sure pendbc is at least 1 991 */ 992 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US * 993 clk_khz / 1000, 1); 994 995 /* get the required exponent */ 996 while (pendbc >> i++) 997 ; 998 999 pendbc = i; 1000 1001 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS; 1002 1003 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK; 1004 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) & 1005 AT91_SAMA5D2_TSMR_PENDBC_MASK; 1006 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA; 1007 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA; 1008 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK; 1009 1010 at91_adc_writel(st, TSMR, tsmr); 1011 1012 acr = at91_adc_readl(st, ACR); 1013 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK; 1014 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK; 1015 at91_adc_writel(st, ACR, acr); 1016 1017 /* Sample Period Time = (TRGPER + 1) / ADCClock */ 1018 st->touch_st.sample_period_val = 1019 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US * 1020 clk_khz / 1000) - 1, 1); 1021 /* enable pen detect IRQ */ 1022 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN); 1023 1024 return 0; 1025 } 1026 1027 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg) 1028 { 1029 u32 val = 0; 1030 u32 scale, result, pos; 1031 1032 /* 1033 * to obtain the actual position we must divide by scale 1034 * and multiply with max, where 1035 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1 1036 */ 1037 /* first half of register is the x or y, second half is the scale */ 1038 if (reg == st->soc_info.platform->layout->XPOSR) 1039 val = at91_adc_readl(st, XPOSR); 1040 else if (reg == st->soc_info.platform->layout->YPOSR) 1041 val = at91_adc_readl(st, YPOSR); 1042 1043 if (!val) 1044 dev_dbg(&st->indio_dev->dev, "pos is 0\n"); 1045 1046 pos = val & AT91_SAMA5D2_XYZ_MASK; 1047 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos; 1048 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 1049 if (scale == 0) { 1050 dev_err(&st->indio_dev->dev, "scale is 0\n"); 1051 return 0; 1052 } 1053 result /= scale; 1054 1055 return result; 1056 } 1057 1058 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st) 1059 { 1060 st->touch_st.x_pos = at91_adc_touch_pos(st, st->soc_info.platform->layout->XPOSR); 1061 return st->touch_st.x_pos; 1062 } 1063 1064 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st) 1065 { 1066 return at91_adc_touch_pos(st, st->soc_info.platform->layout->YPOSR); 1067 } 1068 1069 static u16 at91_adc_touch_pressure(struct at91_adc_state *st) 1070 { 1071 u32 val; 1072 u32 z1, z2; 1073 u32 pres; 1074 u32 rxp = 1; 1075 u32 factor = 1000; 1076 1077 /* calculate the pressure */ 1078 val = at91_adc_readl(st, PRESSR); 1079 z1 = val & AT91_SAMA5D2_XYZ_MASK; 1080 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 1081 1082 if (z1 != 0) 1083 pres = rxp * (st->touch_st.x_pos * factor / 1024) * 1084 (z2 * factor / z1 - factor) / 1085 factor; 1086 else 1087 pres = 0xFFFF; /* no pen contact */ 1088 1089 /* 1090 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0. 1091 * We compute it this way, but let's return it in the expected way, 1092 * growing from 0 to 0xFFFF. 1093 */ 1094 return 0xFFFF - pres; 1095 } 1096 1097 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val) 1098 { 1099 *val = 0; 1100 if (!st->touch_st.touching) 1101 return -ENODATA; 1102 if (chan == st->soc_info.platform->touch_chan_x) 1103 *val = at91_adc_touch_x_pos(st); 1104 else if (chan == st->soc_info.platform->touch_chan_y) 1105 *val = at91_adc_touch_y_pos(st); 1106 else 1107 return -ENODATA; 1108 1109 return IIO_VAL_INT; 1110 } 1111 1112 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val) 1113 { 1114 *val = 0; 1115 if (!st->touch_st.touching) 1116 return -ENODATA; 1117 if (chan == st->soc_info.platform->touch_chan_p) 1118 *val = at91_adc_touch_pressure(st); 1119 else 1120 return -ENODATA; 1121 1122 return IIO_VAL_INT; 1123 } 1124 1125 static void at91_adc_configure_trigger_registers(struct at91_adc_state *st, 1126 bool state) 1127 { 1128 u32 status = at91_adc_readl(st, TRGR); 1129 1130 /* clear TRGMOD */ 1131 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK; 1132 1133 if (state) 1134 status |= st->selected_trig->trgmod_value; 1135 1136 /* set/unset hw trigger */ 1137 at91_adc_writel(st, TRGR, status); 1138 } 1139 1140 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) 1141 { 1142 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 1143 struct at91_adc_state *st = iio_priv(indio); 1144 int ret; 1145 1146 if (state) { 1147 ret = pm_runtime_resume_and_get(st->dev); 1148 if (ret < 0) 1149 return ret; 1150 } 1151 1152 at91_adc_configure_trigger_registers(st, state); 1153 1154 if (!state) { 1155 pm_runtime_mark_last_busy(st->dev); 1156 pm_runtime_put_autosuspend(st->dev); 1157 } 1158 1159 return 0; 1160 } 1161 1162 static void at91_adc_reenable_trigger(struct iio_trigger *trig) 1163 { 1164 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 1165 struct at91_adc_state *st = iio_priv(indio); 1166 1167 /* if we are using DMA, we must not reenable irq after each trigger */ 1168 if (st->dma_st.dma_chan) 1169 return; 1170 1171 enable_irq(st->irq); 1172 1173 /* Needed to ACK the DRDY interruption */ 1174 at91_adc_readl(st, LCDR); 1175 } 1176 1177 static const struct iio_trigger_ops at91_adc_trigger_ops = { 1178 .set_trigger_state = &at91_adc_configure_trigger, 1179 .reenable = &at91_adc_reenable_trigger, 1180 .validate_device = iio_trigger_validate_own_device, 1181 }; 1182 1183 static int at91_adc_dma_size_done(struct at91_adc_state *st) 1184 { 1185 struct dma_tx_state state; 1186 enum dma_status status; 1187 int i, size; 1188 1189 status = dmaengine_tx_status(st->dma_st.dma_chan, 1190 st->dma_st.dma_chan->cookie, 1191 &state); 1192 if (status != DMA_IN_PROGRESS) 1193 return 0; 1194 1195 /* Transferred length is size in bytes from end of buffer */ 1196 i = st->dma_st.rx_buf_sz - state.residue; 1197 1198 /* Return available bytes */ 1199 if (i >= st->dma_st.buf_idx) 1200 size = i - st->dma_st.buf_idx; 1201 else 1202 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx; 1203 return size; 1204 } 1205 1206 static void at91_dma_buffer_done(void *data) 1207 { 1208 struct iio_dev *indio_dev = data; 1209 1210 iio_trigger_poll_nested(indio_dev->trig); 1211 } 1212 1213 static int at91_adc_dma_start(struct iio_dev *indio_dev) 1214 { 1215 struct at91_adc_state *st = iio_priv(indio_dev); 1216 struct dma_async_tx_descriptor *desc; 1217 dma_cookie_t cookie; 1218 int ret; 1219 u8 bit; 1220 1221 if (!st->dma_st.dma_chan) 1222 return 0; 1223 1224 /* we start a new DMA, so set buffer index to start */ 1225 st->dma_st.buf_idx = 0; 1226 1227 /* 1228 * compute buffer size w.r.t. watermark and enabled channels. 1229 * scan_bytes is aligned so we need an exact size for DMA 1230 */ 1231 st->dma_st.rx_buf_sz = 0; 1232 1233 for_each_set_bit(bit, indio_dev->active_scan_mask, 1234 indio_dev->num_channels) { 1235 struct iio_chan_spec const *chan = 1236 at91_adc_chan_get(indio_dev, bit); 1237 1238 if (!chan) 1239 continue; 1240 1241 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8; 1242 } 1243 st->dma_st.rx_buf_sz *= st->dma_st.watermark; 1244 1245 /* Prepare a DMA cyclic transaction */ 1246 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan, 1247 st->dma_st.rx_dma_buf, 1248 st->dma_st.rx_buf_sz, 1249 st->dma_st.rx_buf_sz / 2, 1250 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1251 1252 if (!desc) { 1253 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n"); 1254 return -EBUSY; 1255 } 1256 1257 desc->callback = at91_dma_buffer_done; 1258 desc->callback_param = indio_dev; 1259 1260 cookie = dmaengine_submit(desc); 1261 ret = dma_submit_error(cookie); 1262 if (ret) { 1263 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n"); 1264 dmaengine_terminate_async(st->dma_st.dma_chan); 1265 return ret; 1266 } 1267 1268 /* enable general overrun error signaling */ 1269 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_GOVRE); 1270 /* Issue pending DMA requests */ 1271 dma_async_issue_pending(st->dma_st.dma_chan); 1272 1273 /* consider current time as DMA start time for timestamps */ 1274 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 1275 1276 dev_dbg(&indio_dev->dev, "DMA cyclic started\n"); 1277 1278 return 0; 1279 } 1280 1281 static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio, 1282 struct at91_adc_state *st) 1283 { 1284 /* if using DMA, we do not use our own IRQ (we use DMA-controller) */ 1285 if (st->dma_st.dma_chan) 1286 return false; 1287 /* if the trigger is not ours, then it has its own IRQ */ 1288 if (iio_trigger_validate_own_device(indio->trig, indio)) 1289 return false; 1290 return true; 1291 } 1292 1293 static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev) 1294 { 1295 struct at91_adc_state *st = iio_priv(indio_dev); 1296 1297 return !!bitmap_subset(indio_dev->active_scan_mask, 1298 &st->touch_st.channels_bitmask, 1299 st->soc_info.platform->max_index + 1); 1300 } 1301 1302 static int at91_adc_buffer_prepare(struct iio_dev *indio_dev) 1303 { 1304 int ret; 1305 u8 bit; 1306 struct at91_adc_state *st = iio_priv(indio_dev); 1307 1308 /* check if we are enabling triggered buffer or the touchscreen */ 1309 if (at91_adc_current_chan_is_touch(indio_dev)) 1310 return at91_adc_configure_touch(st, true); 1311 1312 /* if we are not in triggered mode, we cannot enable the buffer. */ 1313 if (!(iio_device_get_current_mode(indio_dev) & INDIO_ALL_TRIGGERED_MODES)) 1314 return -EINVAL; 1315 1316 ret = pm_runtime_resume_and_get(st->dev); 1317 if (ret < 0) 1318 return ret; 1319 1320 /* we continue with the triggered buffer */ 1321 ret = at91_adc_dma_start(indio_dev); 1322 if (ret) { 1323 dev_err(&indio_dev->dev, "buffer prepare failed\n"); 1324 goto pm_runtime_put; 1325 } 1326 1327 for_each_set_bit(bit, indio_dev->active_scan_mask, 1328 indio_dev->num_channels) { 1329 struct iio_chan_spec const *chan = 1330 at91_adc_chan_get(indio_dev, bit); 1331 if (!chan) 1332 continue; 1333 /* these channel types cannot be handled by this trigger */ 1334 if (chan->type == IIO_POSITIONRELATIVE || 1335 chan->type == IIO_PRESSURE || 1336 chan->type == IIO_TEMP) 1337 continue; 1338 1339 at91_adc_cor(st, chan); 1340 1341 at91_adc_writel(st, CHER, BIT(chan->channel)); 1342 } 1343 1344 if (at91_adc_buffer_check_use_irq(indio_dev, st)) 1345 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_DRDY); 1346 1347 pm_runtime_put: 1348 pm_runtime_mark_last_busy(st->dev); 1349 pm_runtime_put_autosuspend(st->dev); 1350 return ret; 1351 } 1352 1353 static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev) 1354 { 1355 struct at91_adc_state *st = iio_priv(indio_dev); 1356 int ret; 1357 u8 bit; 1358 1359 /* check if we are disabling triggered buffer or the touchscreen */ 1360 if (at91_adc_current_chan_is_touch(indio_dev)) 1361 return at91_adc_configure_touch(st, false); 1362 1363 /* if we are not in triggered mode, nothing to do here */ 1364 if (!(iio_device_get_current_mode(indio_dev) & INDIO_ALL_TRIGGERED_MODES)) 1365 return -EINVAL; 1366 1367 ret = pm_runtime_resume_and_get(st->dev); 1368 if (ret < 0) 1369 return ret; 1370 1371 /* 1372 * For each enable channel we must disable it in hardware. 1373 * In the case of DMA, we must read the last converted value 1374 * to clear EOC status and not get a possible interrupt later. 1375 * This value is being read by DMA from LCDR anyway, so it's not lost. 1376 */ 1377 for_each_set_bit(bit, indio_dev->active_scan_mask, 1378 indio_dev->num_channels) { 1379 struct iio_chan_spec const *chan = 1380 at91_adc_chan_get(indio_dev, bit); 1381 1382 if (!chan) 1383 continue; 1384 /* these channel types are virtual, no need to do anything */ 1385 if (chan->type == IIO_POSITIONRELATIVE || 1386 chan->type == IIO_PRESSURE || 1387 chan->type == IIO_TEMP) 1388 continue; 1389 1390 at91_adc_writel(st, CHDR, BIT(chan->channel)); 1391 1392 if (st->dma_st.dma_chan) 1393 at91_adc_read_chan(st, chan->address); 1394 } 1395 1396 if (at91_adc_buffer_check_use_irq(indio_dev, st)) 1397 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_DRDY); 1398 1399 /* read overflow register to clear possible overflow status */ 1400 at91_adc_readl(st, OVER); 1401 1402 /* if we are using DMA we must clear registers and end DMA */ 1403 if (st->dma_st.dma_chan) 1404 dmaengine_terminate_sync(st->dma_st.dma_chan); 1405 1406 pm_runtime_mark_last_busy(st->dev); 1407 pm_runtime_put_autosuspend(st->dev); 1408 1409 return 0; 1410 } 1411 1412 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = { 1413 .postdisable = &at91_adc_buffer_postdisable, 1414 }; 1415 1416 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio, 1417 char *trigger_name) 1418 { 1419 struct iio_trigger *trig; 1420 int ret; 1421 1422 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name, 1423 iio_device_id(indio), trigger_name); 1424 if (!trig) 1425 return ERR_PTR(-ENOMEM); 1426 1427 trig->dev.parent = indio->dev.parent; 1428 iio_trigger_set_drvdata(trig, indio); 1429 trig->ops = &at91_adc_trigger_ops; 1430 1431 ret = devm_iio_trigger_register(&indio->dev, trig); 1432 if (ret) 1433 return ERR_PTR(ret); 1434 1435 return trig; 1436 } 1437 1438 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, 1439 struct iio_poll_func *pf) 1440 { 1441 struct at91_adc_state *st = iio_priv(indio_dev); 1442 int i = 0; 1443 int val; 1444 u8 bit; 1445 u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); 1446 unsigned int timeout = 50; 1447 u32 status, imr, eoc = 0, eoc_imr; 1448 1449 /* 1450 * Check if the conversion is ready. If not, wait a little bit, and 1451 * in case of timeout exit with an error. 1452 */ 1453 while (((eoc & mask) != mask) && timeout) { 1454 at91_adc_irq_status(st, &status, &eoc); 1455 at91_adc_irq_mask(st, &imr, &eoc_imr); 1456 usleep_range(50, 100); 1457 timeout--; 1458 } 1459 1460 /* Cannot read data, not ready. Continue without reporting data */ 1461 if (!timeout) 1462 return; 1463 1464 for_each_set_bit(bit, indio_dev->active_scan_mask, 1465 indio_dev->num_channels) { 1466 struct iio_chan_spec const *chan = 1467 at91_adc_chan_get(indio_dev, bit); 1468 1469 if (!chan) 1470 continue; 1471 /* 1472 * Our external trigger only supports the voltage channels. 1473 * In case someone requested a different type of channel 1474 * just put zeroes to buffer. 1475 * This should not happen because we check the scan mode 1476 * and scan mask when we enable the buffer, and we don't allow 1477 * the buffer to start with a mixed mask (voltage and something 1478 * else). 1479 * Thus, emit a warning. 1480 */ 1481 if (chan->type == IIO_VOLTAGE) { 1482 val = at91_adc_read_chan(st, chan->address); 1483 at91_adc_adjust_val_osr(st, &val); 1484 st->buffer[i] = val; 1485 } else { 1486 st->buffer[i] = 0; 1487 WARN(true, "This trigger cannot handle this type of channel"); 1488 } 1489 i++; 1490 } 1491 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer, 1492 pf->timestamp); 1493 } 1494 1495 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev) 1496 { 1497 struct at91_adc_state *st = iio_priv(indio_dev); 1498 int transferred_len = at91_adc_dma_size_done(st); 1499 s64 ns = iio_get_time_ns(indio_dev); 1500 s64 interval; 1501 int sample_index = 0, sample_count, sample_size; 1502 1503 u32 status = at91_adc_readl(st, ISR); 1504 /* if we reached this point, we cannot sample faster */ 1505 if (status & AT91_SAMA5D2_IER_GOVRE) 1506 pr_info_ratelimited("%s: conversion overrun detected\n", 1507 indio_dev->name); 1508 1509 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark); 1510 1511 sample_count = div_s64(transferred_len, sample_size); 1512 1513 /* 1514 * interval between samples is total time since last transfer handling 1515 * divided by the number of samples (total size divided by sample size) 1516 */ 1517 interval = div_s64((ns - st->dma_st.dma_ts), sample_count); 1518 1519 while (transferred_len >= sample_size) { 1520 /* 1521 * for all the values in the current sample, 1522 * adjust the values inside the buffer for oversampling 1523 */ 1524 at91_adc_adjust_val_osr_array(st, 1525 &st->dma_st.rx_buf[st->dma_st.buf_idx], 1526 sample_size); 1527 1528 iio_push_to_buffers_with_timestamp(indio_dev, 1529 (st->dma_st.rx_buf + st->dma_st.buf_idx), 1530 (st->dma_st.dma_ts + interval * sample_index)); 1531 /* adjust remaining length */ 1532 transferred_len -= sample_size; 1533 /* adjust buffer index */ 1534 st->dma_st.buf_idx += sample_size; 1535 /* in case of reaching end of buffer, reset index */ 1536 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz) 1537 st->dma_st.buf_idx = 0; 1538 sample_index++; 1539 } 1540 /* adjust saved time for next transfer handling */ 1541 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 1542 } 1543 1544 static irqreturn_t at91_adc_trigger_handler(int irq, void *p) 1545 { 1546 struct iio_poll_func *pf = p; 1547 struct iio_dev *indio_dev = pf->indio_dev; 1548 struct at91_adc_state *st = iio_priv(indio_dev); 1549 1550 /* 1551 * If it's not our trigger, start a conversion now, as we are 1552 * actually polling the trigger now. 1553 */ 1554 if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev)) 1555 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START); 1556 1557 if (st->dma_st.dma_chan) 1558 at91_adc_trigger_handler_dma(indio_dev); 1559 else 1560 at91_adc_trigger_handler_nodma(indio_dev, pf); 1561 1562 iio_trigger_notify_done(indio_dev->trig); 1563 1564 return IRQ_HANDLED; 1565 } 1566 1567 static unsigned at91_adc_startup_time(unsigned startup_time_min, 1568 unsigned adc_clk_khz) 1569 { 1570 static const unsigned int startup_lookup[] = { 1571 0, 8, 16, 24, 1572 64, 80, 96, 112, 1573 512, 576, 640, 704, 1574 768, 832, 896, 960 1575 }; 1576 unsigned ticks_min, i; 1577 1578 /* 1579 * Since the adc frequency is checked before, there is no reason 1580 * to not meet the startup time constraint. 1581 */ 1582 1583 ticks_min = startup_time_min * adc_clk_khz / 1000; 1584 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++) 1585 if (startup_lookup[i] > ticks_min) 1586 break; 1587 1588 return i; 1589 } 1590 1591 static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq, 1592 unsigned int startup_time, 1593 unsigned int tracktim) 1594 { 1595 struct at91_adc_state *st = iio_priv(indio_dev); 1596 unsigned f_per, prescal, startup, mr; 1597 int ret; 1598 1599 f_per = clk_get_rate(st->per_clk); 1600 prescal = (f_per / (2 * freq)) - 1; 1601 1602 startup = at91_adc_startup_time(startup_time, freq / 1000); 1603 1604 ret = pm_runtime_resume_and_get(st->dev); 1605 if (ret < 0) 1606 return; 1607 1608 mr = at91_adc_readl(st, MR); 1609 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK); 1610 mr |= AT91_SAMA5D2_MR_STARTUP(startup); 1611 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal); 1612 mr |= AT91_SAMA5D2_MR_TRACKTIM(tracktim); 1613 at91_adc_writel(st, MR, mr); 1614 1615 pm_runtime_mark_last_busy(st->dev); 1616 pm_runtime_put_autosuspend(st->dev); 1617 1618 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u, tracktim=%u\n", 1619 freq, startup, prescal, tracktim); 1620 st->current_sample_rate = freq; 1621 } 1622 1623 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st) 1624 { 1625 return st->current_sample_rate; 1626 } 1627 1628 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev) 1629 { 1630 struct at91_adc_state *st = iio_priv(indio_dev); 1631 u8 bit; 1632 u16 val; 1633 int i = 0; 1634 1635 for_each_set_bit(bit, indio_dev->active_scan_mask, 1636 st->soc_info.platform->max_index + 1) { 1637 struct iio_chan_spec const *chan = 1638 at91_adc_chan_get(indio_dev, bit); 1639 1640 if (chan->type == IIO_POSITIONRELATIVE) 1641 at91_adc_read_position(st, chan->channel, &val); 1642 else if (chan->type == IIO_PRESSURE) 1643 at91_adc_read_pressure(st, chan->channel, &val); 1644 else 1645 continue; 1646 st->buffer[i] = val; 1647 i++; 1648 } 1649 /* 1650 * Schedule work to push to buffers. 1651 * This is intended to push to the callback buffer that another driver 1652 * registered. We are still in a handler from our IRQ. If we push 1653 * directly, it means the other driver has it's callback called 1654 * from our IRQ context. Which is something we better avoid. 1655 * Let's schedule it after our IRQ is completed. 1656 */ 1657 schedule_work(&st->touch_st.workq); 1658 } 1659 1660 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st) 1661 { 1662 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN); 1663 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_NOPEN | 1664 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1665 AT91_SAMA5D2_IER_PRDY); 1666 at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC | 1667 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val)); 1668 st->touch_st.touching = true; 1669 } 1670 1671 static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev) 1672 { 1673 struct at91_adc_state *st = iio_priv(indio_dev); 1674 1675 at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER); 1676 at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_NOPEN | 1677 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1678 AT91_SAMA5D2_IER_PRDY); 1679 st->touch_st.touching = false; 1680 1681 at91_adc_touch_data_handler(indio_dev); 1682 1683 at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN); 1684 } 1685 1686 static void at91_adc_workq_handler(struct work_struct *workq) 1687 { 1688 struct at91_adc_touch *touch_st = container_of(workq, 1689 struct at91_adc_touch, workq); 1690 struct at91_adc_state *st = container_of(touch_st, 1691 struct at91_adc_state, touch_st); 1692 struct iio_dev *indio_dev = st->indio_dev; 1693 1694 iio_push_to_buffers(indio_dev, st->buffer); 1695 } 1696 1697 static irqreturn_t at91_adc_interrupt(int irq, void *private) 1698 { 1699 struct iio_dev *indio = private; 1700 struct at91_adc_state *st = iio_priv(indio); 1701 u32 status, eoc, imr, eoc_imr; 1702 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1703 AT91_SAMA5D2_IER_PRDY; 1704 1705 at91_adc_irq_status(st, &status, &eoc); 1706 at91_adc_irq_mask(st, &imr, &eoc_imr); 1707 1708 if (!(status & imr) && !(eoc & eoc_imr)) 1709 return IRQ_NONE; 1710 if (status & AT91_SAMA5D2_IER_PEN) { 1711 /* pen detected IRQ */ 1712 at91_adc_pen_detect_interrupt(st); 1713 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) { 1714 /* nopen detected IRQ */ 1715 at91_adc_no_pen_detect_interrupt(indio); 1716 } else if ((status & AT91_SAMA5D2_ISR_PENS) && 1717 ((status & rdy_mask) == rdy_mask)) { 1718 /* periodic trigger IRQ - during pen sense */ 1719 at91_adc_touch_data_handler(indio); 1720 } else if (status & AT91_SAMA5D2_ISR_PENS) { 1721 /* 1722 * touching, but the measurements are not ready yet. 1723 * read and ignore. 1724 */ 1725 status = at91_adc_readl(st, XPOSR); 1726 status = at91_adc_readl(st, YPOSR); 1727 status = at91_adc_readl(st, PRESSR); 1728 } else if (iio_buffer_enabled(indio) && 1729 (status & AT91_SAMA5D2_IER_DRDY)) { 1730 /* triggered buffer without DMA */ 1731 disable_irq_nosync(irq); 1732 iio_trigger_poll(indio->trig); 1733 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) { 1734 /* triggered buffer with DMA - should not happen */ 1735 disable_irq_nosync(irq); 1736 WARN(true, "Unexpected irq occurred\n"); 1737 } else if (!iio_buffer_enabled(indio)) { 1738 /* software requested conversion */ 1739 st->conversion_value = at91_adc_read_chan(st, st->chan->address); 1740 st->conversion_done = true; 1741 wake_up_interruptible(&st->wq_data_available); 1742 } 1743 return IRQ_HANDLED; 1744 } 1745 1746 /* This needs to be called with direct mode claimed and st->lock locked. */ 1747 static int at91_adc_read_info_raw(struct iio_dev *indio_dev, 1748 struct iio_chan_spec const *chan, int *val) 1749 { 1750 struct at91_adc_state *st = iio_priv(indio_dev); 1751 u16 tmp_val; 1752 int ret; 1753 1754 ret = pm_runtime_resume_and_get(st->dev); 1755 if (ret < 0) 1756 return ret; 1757 1758 /* 1759 * Keep in mind that we cannot use software trigger or touchscreen 1760 * if external trigger is enabled 1761 */ 1762 if (chan->type == IIO_POSITIONRELATIVE) { 1763 ret = at91_adc_read_position(st, chan->channel, 1764 &tmp_val); 1765 *val = tmp_val; 1766 if (ret > 0) 1767 ret = at91_adc_adjust_val_osr(st, val); 1768 1769 goto pm_runtime_put; 1770 } 1771 if (chan->type == IIO_PRESSURE) { 1772 ret = at91_adc_read_pressure(st, chan->channel, 1773 &tmp_val); 1774 *val = tmp_val; 1775 if (ret > 0) 1776 ret = at91_adc_adjust_val_osr(st, val); 1777 1778 goto pm_runtime_put; 1779 } 1780 1781 /* in this case we have a voltage or temperature channel */ 1782 1783 st->chan = chan; 1784 1785 at91_adc_cor(st, chan); 1786 at91_adc_writel(st, CHER, BIT(chan->channel)); 1787 /* 1788 * TEMPMR.TEMPON needs to update after CHER otherwise if none 1789 * of the channels are enabled and TEMPMR.TEMPON = 1 will 1790 * trigger DRDY interruption while preparing for temperature read. 1791 */ 1792 if (chan->type == IIO_TEMP) 1793 at91_adc_writel(st, TEMPMR, AT91_SAMA5D2_TEMPMR_TEMPON); 1794 at91_adc_eoc_ena(st, chan->channel); 1795 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START); 1796 1797 ret = wait_event_interruptible_timeout(st->wq_data_available, 1798 st->conversion_done, 1799 msecs_to_jiffies(1000)); 1800 if (ret == 0) 1801 ret = -ETIMEDOUT; 1802 1803 if (ret > 0) { 1804 *val = st->conversion_value; 1805 ret = at91_adc_adjust_val_osr(st, val); 1806 if (chan->scan_type.sign == 's') 1807 *val = sign_extend32(*val, 1808 chan->scan_type.realbits - 1); 1809 st->conversion_done = false; 1810 } 1811 1812 at91_adc_eoc_dis(st, st->chan->channel); 1813 if (chan->type == IIO_TEMP) 1814 at91_adc_writel(st, TEMPMR, 0U); 1815 at91_adc_writel(st, CHDR, BIT(chan->channel)); 1816 1817 /* Needed to ACK the DRDY interruption */ 1818 at91_adc_readl(st, LCDR); 1819 1820 pm_runtime_put: 1821 pm_runtime_mark_last_busy(st->dev); 1822 pm_runtime_put_autosuspend(st->dev); 1823 return ret; 1824 } 1825 1826 static int at91_adc_read_info_locked(struct iio_dev *indio_dev, 1827 struct iio_chan_spec const *chan, int *val) 1828 { 1829 struct at91_adc_state *st = iio_priv(indio_dev); 1830 1831 guard(mutex)(&st->lock); 1832 1833 return at91_adc_read_info_raw(indio_dev, chan, val); 1834 } 1835 1836 static void at91_adc_temp_sensor_configure(struct at91_adc_state *st, 1837 bool start) 1838 { 1839 u32 sample_rate, oversampling_ratio; 1840 u32 startup_time, tracktim, trackx; 1841 1842 if (start) { 1843 /* 1844 * Configure the sensor for best accuracy: 10MHz frequency, 1845 * oversampling rate of 256, tracktim=0xf and trackx=1. 1846 */ 1847 sample_rate = 10 * MEGA; 1848 oversampling_ratio = 256; 1849 startup_time = AT91_SAMA5D2_MR_STARTUP_TS_MIN; 1850 tracktim = AT91_SAMA5D2_MR_TRACKTIM_TS; 1851 trackx = AT91_SAMA5D2_TRACKX_TS; 1852 1853 st->temp_st.saved_sample_rate = st->current_sample_rate; 1854 st->temp_st.saved_oversampling = st->oversampling_ratio; 1855 } else { 1856 /* Go back to previous settings. */ 1857 sample_rate = st->temp_st.saved_sample_rate; 1858 oversampling_ratio = st->temp_st.saved_oversampling; 1859 startup_time = st->soc_info.startup_time; 1860 tracktim = 0; 1861 trackx = 0; 1862 } 1863 1864 at91_adc_setup_samp_freq(st->indio_dev, sample_rate, startup_time, 1865 tracktim); 1866 at91_adc_config_emr(st, oversampling_ratio, trackx); 1867 } 1868 1869 static int at91_adc_read_temp(struct iio_dev *indio_dev, 1870 struct iio_chan_spec const *chan, int *val) 1871 { 1872 struct at91_adc_state *st = iio_priv(indio_dev); 1873 struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb; 1874 u64 div1, div2; 1875 u32 tmp; 1876 int ret, vbg, vtemp; 1877 1878 guard(mutex)(&st->lock); 1879 1880 ret = pm_runtime_resume_and_get(st->dev); 1881 if (ret < 0) 1882 return ret; 1883 1884 at91_adc_temp_sensor_configure(st, true); 1885 1886 /* Read VBG. */ 1887 tmp = at91_adc_readl(st, ACR); 1888 tmp |= AT91_SAMA5D2_ACR_SRCLCH; 1889 at91_adc_writel(st, ACR, tmp); 1890 ret = at91_adc_read_info_raw(indio_dev, chan, &vbg); 1891 if (ret < 0) 1892 goto restore_config; 1893 1894 /* Read VTEMP. */ 1895 tmp &= ~AT91_SAMA5D2_ACR_SRCLCH; 1896 at91_adc_writel(st, ACR, tmp); 1897 ret = at91_adc_read_info_raw(indio_dev, chan, &vtemp); 1898 1899 restore_config: 1900 /* Revert previous settings. */ 1901 at91_adc_temp_sensor_configure(st, false); 1902 pm_runtime_mark_last_busy(st->dev); 1903 pm_runtime_put_autosuspend(st->dev); 1904 if (ret < 0) 1905 return ret; 1906 1907 /* 1908 * Temp[milli] = p1[milli] + (vtemp * clb->p6 - clb->p4 * vbg)/ 1909 * (vbg * AT91_ADC_TS_VTEMP_DT) 1910 */ 1911 div1 = DIV_ROUND_CLOSEST_ULL(((u64)vtemp * clb->p6), vbg); 1912 div1 = DIV_ROUND_CLOSEST_ULL((div1 * 1000), AT91_ADC_TS_VTEMP_DT); 1913 div2 = DIV_ROUND_CLOSEST_ULL((u64)clb->p4, AT91_ADC_TS_VTEMP_DT); 1914 div2 *= 1000; 1915 *val = clb->p1 + (int)div1 - (int)div2; 1916 1917 return ret; 1918 } 1919 1920 static int at91_adc_read_raw(struct iio_dev *indio_dev, 1921 struct iio_chan_spec const *chan, 1922 int *val, int *val2, long mask) 1923 { 1924 struct at91_adc_state *st = iio_priv(indio_dev); 1925 int ret; 1926 1927 switch (mask) { 1928 case IIO_CHAN_INFO_RAW: 1929 if (!iio_device_claim_direct(indio_dev)) 1930 return -EBUSY; 1931 1932 ret = at91_adc_read_info_locked(indio_dev, chan, val); 1933 iio_device_release_direct(indio_dev); 1934 return ret; 1935 1936 case IIO_CHAN_INFO_SCALE: 1937 *val = st->vref_uv / 1000; 1938 if (chan->differential) 1939 *val *= 2; 1940 *val2 = chan->scan_type.realbits; 1941 return IIO_VAL_FRACTIONAL_LOG2; 1942 1943 case IIO_CHAN_INFO_PROCESSED: 1944 if (chan->type != IIO_TEMP) 1945 return -EINVAL; 1946 if (!iio_device_claim_direct(indio_dev)) 1947 return -EBUSY; 1948 1949 ret = at91_adc_read_temp(indio_dev, chan, val); 1950 iio_device_release_direct(indio_dev); 1951 1952 return ret; 1953 1954 case IIO_CHAN_INFO_SAMP_FREQ: 1955 *val = at91_adc_get_sample_freq(st); 1956 return IIO_VAL_INT; 1957 1958 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1959 *val = st->oversampling_ratio; 1960 return IIO_VAL_INT; 1961 1962 default: 1963 return -EINVAL; 1964 } 1965 } 1966 1967 static int at91_adc_write_raw(struct iio_dev *indio_dev, 1968 struct iio_chan_spec const *chan, 1969 int val, int val2, long mask) 1970 { 1971 struct at91_adc_state *st = iio_priv(indio_dev); 1972 int ret; 1973 1974 switch (mask) { 1975 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1976 /* if no change, optimize out */ 1977 if (val == st->oversampling_ratio) 1978 return 0; 1979 1980 if (!iio_device_claim_direct(indio_dev)) 1981 return -EBUSY; 1982 mutex_lock(&st->lock); 1983 /* update ratio */ 1984 ret = at91_adc_config_emr(st, val, 0); 1985 mutex_unlock(&st->lock); 1986 iio_device_release_direct(indio_dev); 1987 return ret; 1988 case IIO_CHAN_INFO_SAMP_FREQ: 1989 if (val < st->soc_info.min_sample_rate || 1990 val > st->soc_info.max_sample_rate) 1991 return -EINVAL; 1992 1993 if (!iio_device_claim_direct(indio_dev)) 1994 return -EBUSY; 1995 mutex_lock(&st->lock); 1996 at91_adc_setup_samp_freq(indio_dev, val, 1997 st->soc_info.startup_time, 0); 1998 mutex_unlock(&st->lock); 1999 iio_device_release_direct(indio_dev); 2000 return 0; 2001 default: 2002 return -EINVAL; 2003 } 2004 } 2005 2006 static int at91_adc_read_avail(struct iio_dev *indio_dev, 2007 struct iio_chan_spec const *chan, 2008 const int **vals, int *type, int *length, 2009 long mask) 2010 { 2011 struct at91_adc_state *st = iio_priv(indio_dev); 2012 2013 switch (mask) { 2014 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 2015 *vals = (int *)st->soc_info.platform->oversampling_avail; 2016 *type = IIO_VAL_INT; 2017 *length = st->soc_info.platform->oversampling_avail_no; 2018 return IIO_AVAIL_LIST; 2019 default: 2020 return -EINVAL; 2021 } 2022 } 2023 2024 static void at91_adc_dma_init(struct at91_adc_state *st) 2025 { 2026 struct device *dev = &st->indio_dev->dev; 2027 struct dma_slave_config config = {0}; 2028 /* we have 2 bytes for each channel */ 2029 unsigned int sample_size = st->soc_info.platform->nr_channels * 2; 2030 /* 2031 * We make the buffer double the size of the fifo, 2032 * such that DMA uses one half of the buffer (full fifo size) 2033 * and the software uses the other half to read/write. 2034 */ 2035 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 2036 sample_size * 2, PAGE_SIZE); 2037 2038 if (st->dma_st.dma_chan) 2039 return; 2040 2041 st->dma_st.dma_chan = dma_request_chan(dev, "rx"); 2042 if (IS_ERR(st->dma_st.dma_chan)) { 2043 dev_info(dev, "can't get DMA channel\n"); 2044 st->dma_st.dma_chan = NULL; 2045 goto dma_exit; 2046 } 2047 2048 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev, 2049 pages * PAGE_SIZE, 2050 &st->dma_st.rx_dma_buf, 2051 GFP_KERNEL); 2052 if (!st->dma_st.rx_buf) { 2053 dev_info(dev, "can't allocate coherent DMA area\n"); 2054 goto dma_chan_disable; 2055 } 2056 2057 /* Configure DMA channel to read data register */ 2058 config.direction = DMA_DEV_TO_MEM; 2059 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr 2060 + st->soc_info.platform->layout->LCDR); 2061 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 2062 config.src_maxburst = 1; 2063 config.dst_maxburst = 1; 2064 2065 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) { 2066 dev_info(dev, "can't configure DMA slave\n"); 2067 goto dma_free_area; 2068 } 2069 2070 dev_info(dev, "using %s for rx DMA transfers\n", 2071 dma_chan_name(st->dma_st.dma_chan)); 2072 2073 return; 2074 2075 dma_free_area: 2076 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 2077 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 2078 dma_chan_disable: 2079 dma_release_channel(st->dma_st.dma_chan); 2080 st->dma_st.dma_chan = NULL; 2081 dma_exit: 2082 dev_info(dev, "continuing without DMA support\n"); 2083 } 2084 2085 static void at91_adc_dma_disable(struct at91_adc_state *st) 2086 { 2087 struct device *dev = &st->indio_dev->dev; 2088 /* we have 2 bytes for each channel */ 2089 unsigned int sample_size = st->soc_info.platform->nr_channels * 2; 2090 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 2091 sample_size * 2, PAGE_SIZE); 2092 2093 /* if we are not using DMA, just return */ 2094 if (!st->dma_st.dma_chan) 2095 return; 2096 2097 /* wait for all transactions to be terminated first*/ 2098 dmaengine_terminate_sync(st->dma_st.dma_chan); 2099 2100 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 2101 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 2102 dma_release_channel(st->dma_st.dma_chan); 2103 st->dma_st.dma_chan = NULL; 2104 2105 dev_info(dev, "continuing without DMA support\n"); 2106 } 2107 2108 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 2109 { 2110 struct at91_adc_state *st = iio_priv(indio_dev); 2111 int ret; 2112 2113 if (val > AT91_HWFIFO_MAX_SIZE) 2114 val = AT91_HWFIFO_MAX_SIZE; 2115 2116 if (!st->selected_trig->hw_trig) { 2117 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n"); 2118 return 0; 2119 } 2120 2121 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val); 2122 st->dma_st.watermark = val; 2123 2124 /* 2125 * The logic here is: if we have watermark 1, it means we do 2126 * each conversion with it's own IRQ, thus we don't need DMA. 2127 * If the watermark is higher, we do DMA to do all the transfers in bulk 2128 */ 2129 2130 if (val == 1) 2131 at91_adc_dma_disable(st); 2132 else if (val > 1) 2133 at91_adc_dma_init(st); 2134 2135 /* 2136 * We can start the DMA only after setting the watermark and 2137 * having the DMA initialization completed 2138 */ 2139 ret = at91_adc_buffer_prepare(indio_dev); 2140 if (ret) 2141 at91_adc_dma_disable(st); 2142 2143 return ret; 2144 } 2145 2146 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev, 2147 const unsigned long *scan_mask) 2148 { 2149 struct at91_adc_state *st = iio_priv(indio_dev); 2150 2151 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask, 2152 st->soc_info.platform->max_index + 1)) 2153 return 0; 2154 /* 2155 * if the new bitmap is a combination of touchscreen and regular 2156 * channels, then we are not fine 2157 */ 2158 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask, 2159 st->soc_info.platform->max_index + 1)) 2160 return -EINVAL; 2161 return 0; 2162 } 2163 2164 static void at91_adc_hw_init(struct iio_dev *indio_dev) 2165 { 2166 struct at91_adc_state *st = iio_priv(indio_dev); 2167 2168 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST); 2169 if (st->soc_info.platform->layout->EOC_IDR) 2170 at91_adc_writel(st, EOC_IDR, 0xffffffff); 2171 at91_adc_writel(st, IDR, 0xffffffff); 2172 /* 2173 * Transfer field must be set to 2 according to the datasheet and 2174 * allows different analog settings for each channel. 2175 */ 2176 at91_adc_writel(st, MR, 2177 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH); 2178 2179 at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate, 2180 st->soc_info.startup_time, 0); 2181 2182 /* configure extended mode register */ 2183 at91_adc_config_emr(st, st->oversampling_ratio, 0); 2184 } 2185 2186 static ssize_t at91_adc_get_fifo_state(struct device *dev, 2187 struct device_attribute *attr, char *buf) 2188 { 2189 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 2190 struct at91_adc_state *st = iio_priv(indio_dev); 2191 2192 return sysfs_emit(buf, "%d\n", !!st->dma_st.dma_chan); 2193 } 2194 2195 static ssize_t at91_adc_get_watermark(struct device *dev, 2196 struct device_attribute *attr, char *buf) 2197 { 2198 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 2199 struct at91_adc_state *st = iio_priv(indio_dev); 2200 2201 return sysfs_emit(buf, "%d\n", st->dma_st.watermark); 2202 } 2203 2204 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 2205 at91_adc_get_fifo_state, NULL, 0); 2206 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 2207 at91_adc_get_watermark, NULL, 0); 2208 2209 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "2"); 2210 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR); 2211 2212 static const struct iio_dev_attr *at91_adc_fifo_attributes[] = { 2213 &iio_dev_attr_hwfifo_watermark_min, 2214 &iio_dev_attr_hwfifo_watermark_max, 2215 &iio_dev_attr_hwfifo_watermark, 2216 &iio_dev_attr_hwfifo_enabled, 2217 NULL, 2218 }; 2219 2220 static const struct iio_info at91_adc_info = { 2221 .read_avail = &at91_adc_read_avail, 2222 .read_raw = &at91_adc_read_raw, 2223 .write_raw = &at91_adc_write_raw, 2224 .update_scan_mode = &at91_adc_update_scan_mode, 2225 .fwnode_xlate = &at91_adc_fwnode_xlate, 2226 .hwfifo_set_watermark = &at91_adc_set_watermark, 2227 }; 2228 2229 static int at91_adc_buffer_and_trigger_init(struct device *dev, 2230 struct iio_dev *indio) 2231 { 2232 struct at91_adc_state *st = iio_priv(indio); 2233 const struct iio_dev_attr **fifo_attrs; 2234 int ret; 2235 2236 if (st->selected_trig->hw_trig) 2237 fifo_attrs = at91_adc_fifo_attributes; 2238 else 2239 fifo_attrs = NULL; 2240 2241 ret = devm_iio_triggered_buffer_setup_ext(&indio->dev, indio, 2242 &iio_pollfunc_store_time, &at91_adc_trigger_handler, 2243 IIO_BUFFER_DIRECTION_IN, &at91_buffer_setup_ops, fifo_attrs); 2244 if (ret < 0) { 2245 dev_err(dev, "couldn't initialize the buffer.\n"); 2246 return ret; 2247 } 2248 2249 if (!st->selected_trig->hw_trig) 2250 return 0; 2251 2252 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name); 2253 if (IS_ERR(st->trig)) { 2254 dev_err(dev, "could not allocate trigger\n"); 2255 return PTR_ERR(st->trig); 2256 } 2257 2258 /* 2259 * Initially the iio buffer has a length of 2 and 2260 * a watermark of 1 2261 */ 2262 st->dma_st.watermark = 1; 2263 2264 return 0; 2265 } 2266 2267 static int at91_adc_temp_sensor_init(struct at91_adc_state *st, 2268 struct device *dev) 2269 { 2270 struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb; 2271 struct nvmem_cell *temp_calib; 2272 u32 *buf; 2273 size_t len; 2274 int ret = 0; 2275 2276 if (!st->soc_info.platform->temp_sensor) 2277 return 0; 2278 2279 /* Get the calibration data from NVMEM. */ 2280 temp_calib = devm_nvmem_cell_get(dev, "temperature_calib"); 2281 if (IS_ERR(temp_calib)) { 2282 ret = PTR_ERR(temp_calib); 2283 if (ret != -ENOENT) 2284 dev_err(dev, "Failed to get temperature_calib cell!\n"); 2285 return ret; 2286 } 2287 2288 buf = nvmem_cell_read(temp_calib, &len); 2289 if (IS_ERR(buf)) { 2290 dev_err(dev, "Failed to read calibration data!\n"); 2291 return PTR_ERR(buf); 2292 } 2293 if (len < AT91_ADC_TS_CLB_IDX_MAX * 4) { 2294 dev_err(dev, "Invalid calibration data!\n"); 2295 ret = -EINVAL; 2296 goto free_buf; 2297 } 2298 2299 /* Store calibration data for later use. */ 2300 clb->p1 = buf[AT91_ADC_TS_CLB_IDX_P1]; 2301 clb->p4 = buf[AT91_ADC_TS_CLB_IDX_P4]; 2302 clb->p6 = buf[AT91_ADC_TS_CLB_IDX_P6]; 2303 2304 /* 2305 * We prepare here the conversion to milli to avoid doing it on hotpath. 2306 */ 2307 clb->p1 = clb->p1 * 1000; 2308 2309 free_buf: 2310 kfree(buf); 2311 return ret; 2312 } 2313 2314 static int at91_adc_probe(struct platform_device *pdev) 2315 { 2316 struct device *dev = &pdev->dev; 2317 struct iio_dev *indio_dev; 2318 struct at91_adc_state *st; 2319 struct resource *res; 2320 int ret, i, num_channels; 2321 u32 edge_type = IRQ_TYPE_NONE; 2322 2323 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 2324 if (!indio_dev) 2325 return -ENOMEM; 2326 2327 st = iio_priv(indio_dev); 2328 st->indio_dev = indio_dev; 2329 2330 st->soc_info.platform = device_get_match_data(dev); 2331 2332 ret = at91_adc_temp_sensor_init(st, &pdev->dev); 2333 /* Don't register temperature channel if initialization failed. */ 2334 if (ret) 2335 num_channels = st->soc_info.platform->max_channels - 1; 2336 else 2337 num_channels = st->soc_info.platform->max_channels; 2338 2339 indio_dev->name = dev_name(&pdev->dev); 2340 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 2341 indio_dev->info = &at91_adc_info; 2342 indio_dev->channels = *st->soc_info.platform->adc_channels; 2343 indio_dev->num_channels = num_channels; 2344 2345 bitmap_set(&st->touch_st.channels_bitmask, 2346 st->soc_info.platform->touch_chan_x, 1); 2347 bitmap_set(&st->touch_st.channels_bitmask, 2348 st->soc_info.platform->touch_chan_y, 1); 2349 bitmap_set(&st->touch_st.channels_bitmask, 2350 st->soc_info.platform->touch_chan_p, 1); 2351 2352 st->oversampling_ratio = 1; 2353 2354 ret = device_property_read_u32(dev, "atmel,min-sample-rate-hz", 2355 &st->soc_info.min_sample_rate); 2356 if (ret) { 2357 dev_err(&pdev->dev, 2358 "invalid or missing value for atmel,min-sample-rate-hz\n"); 2359 return ret; 2360 } 2361 2362 ret = device_property_read_u32(dev, "atmel,max-sample-rate-hz", 2363 &st->soc_info.max_sample_rate); 2364 if (ret) { 2365 dev_err(&pdev->dev, 2366 "invalid or missing value for atmel,max-sample-rate-hz\n"); 2367 return ret; 2368 } 2369 2370 ret = device_property_read_u32(dev, "atmel,startup-time-ms", 2371 &st->soc_info.startup_time); 2372 if (ret) { 2373 dev_err(&pdev->dev, 2374 "invalid or missing value for atmel,startup-time-ms\n"); 2375 return ret; 2376 } 2377 2378 ret = device_property_read_u32(dev, "atmel,trigger-edge-type", 2379 &edge_type); 2380 if (ret) { 2381 dev_dbg(&pdev->dev, 2382 "atmel,trigger-edge-type not specified, only software trigger available\n"); 2383 } 2384 2385 st->selected_trig = NULL; 2386 2387 /* find the right trigger, or no trigger at all */ 2388 for (i = 0; i < st->soc_info.platform->hw_trig_cnt + 1; i++) 2389 if (at91_adc_trigger_list[i].edge_type == edge_type) { 2390 st->selected_trig = &at91_adc_trigger_list[i]; 2391 break; 2392 } 2393 2394 if (!st->selected_trig) { 2395 dev_err(&pdev->dev, "invalid external trigger edge value\n"); 2396 return -EINVAL; 2397 } 2398 2399 init_waitqueue_head(&st->wq_data_available); 2400 mutex_init(&st->lock); 2401 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler); 2402 2403 st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2404 if (IS_ERR(st->base)) 2405 return PTR_ERR(st->base); 2406 2407 /* if we plan to use DMA, we need the physical address of the regs */ 2408 st->dma_st.phys_addr = res->start; 2409 2410 st->irq = platform_get_irq(pdev, 0); 2411 if (st->irq < 0) 2412 return st->irq; 2413 2414 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk"); 2415 if (IS_ERR(st->per_clk)) 2416 return PTR_ERR(st->per_clk); 2417 2418 st->reg = devm_regulator_get(&pdev->dev, "vddana"); 2419 if (IS_ERR(st->reg)) 2420 return PTR_ERR(st->reg); 2421 2422 st->vref = devm_regulator_get(&pdev->dev, "vref"); 2423 if (IS_ERR(st->vref)) 2424 return PTR_ERR(st->vref); 2425 2426 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0, 2427 pdev->dev.driver->name, indio_dev); 2428 if (ret) 2429 return ret; 2430 2431 ret = regulator_enable(st->reg); 2432 if (ret) 2433 return ret; 2434 2435 ret = regulator_enable(st->vref); 2436 if (ret) 2437 goto reg_disable; 2438 2439 st->vref_uv = regulator_get_voltage(st->vref); 2440 if (st->vref_uv <= 0) { 2441 ret = -EINVAL; 2442 goto vref_disable; 2443 } 2444 2445 ret = clk_prepare_enable(st->per_clk); 2446 if (ret) 2447 goto vref_disable; 2448 2449 platform_set_drvdata(pdev, indio_dev); 2450 st->dev = &pdev->dev; 2451 pm_runtime_set_autosuspend_delay(st->dev, 500); 2452 pm_runtime_use_autosuspend(st->dev); 2453 pm_runtime_set_active(st->dev); 2454 pm_runtime_enable(st->dev); 2455 pm_runtime_get_noresume(st->dev); 2456 2457 at91_adc_hw_init(indio_dev); 2458 2459 ret = at91_adc_buffer_and_trigger_init(&pdev->dev, indio_dev); 2460 if (ret < 0) 2461 goto err_pm_disable; 2462 2463 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32))) 2464 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n"); 2465 2466 ret = iio_device_register(indio_dev); 2467 if (ret < 0) 2468 goto dma_disable; 2469 2470 if (st->selected_trig->hw_trig) 2471 dev_info(&pdev->dev, "setting up trigger as %s\n", 2472 st->selected_trig->name); 2473 2474 dev_info(&pdev->dev, "version: %x\n", 2475 readl_relaxed(st->base + st->soc_info.platform->layout->VERSION)); 2476 2477 pm_runtime_mark_last_busy(st->dev); 2478 pm_runtime_put_autosuspend(st->dev); 2479 2480 return 0; 2481 2482 dma_disable: 2483 at91_adc_dma_disable(st); 2484 err_pm_disable: 2485 pm_runtime_put_noidle(st->dev); 2486 pm_runtime_disable(st->dev); 2487 pm_runtime_set_suspended(st->dev); 2488 pm_runtime_dont_use_autosuspend(st->dev); 2489 clk_disable_unprepare(st->per_clk); 2490 vref_disable: 2491 regulator_disable(st->vref); 2492 reg_disable: 2493 regulator_disable(st->reg); 2494 return ret; 2495 } 2496 2497 static void at91_adc_remove(struct platform_device *pdev) 2498 { 2499 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 2500 struct at91_adc_state *st = iio_priv(indio_dev); 2501 2502 iio_device_unregister(indio_dev); 2503 2504 at91_adc_dma_disable(st); 2505 2506 pm_runtime_disable(st->dev); 2507 pm_runtime_set_suspended(st->dev); 2508 clk_disable_unprepare(st->per_clk); 2509 2510 regulator_disable(st->vref); 2511 regulator_disable(st->reg); 2512 } 2513 2514 static int at91_adc_suspend(struct device *dev) 2515 { 2516 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2517 struct at91_adc_state *st = iio_priv(indio_dev); 2518 int ret; 2519 2520 ret = pm_runtime_resume_and_get(st->dev); 2521 if (ret < 0) 2522 return ret; 2523 2524 if (iio_buffer_enabled(indio_dev)) 2525 at91_adc_buffer_postdisable(indio_dev); 2526 2527 /* 2528 * Do a sofware reset of the ADC before we go to suspend. 2529 * this will ensure that all pins are free from being muxed by the ADC 2530 * and can be used by for other devices. 2531 * Otherwise, ADC will hog them and we can't go to suspend mode. 2532 */ 2533 at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST); 2534 2535 pm_runtime_mark_last_busy(st->dev); 2536 pm_runtime_put_noidle(st->dev); 2537 clk_disable_unprepare(st->per_clk); 2538 regulator_disable(st->vref); 2539 regulator_disable(st->reg); 2540 2541 return pinctrl_pm_select_sleep_state(dev); 2542 } 2543 2544 static int at91_adc_resume(struct device *dev) 2545 { 2546 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2547 struct at91_adc_state *st = iio_priv(indio_dev); 2548 int ret; 2549 2550 ret = pinctrl_pm_select_default_state(dev); 2551 if (ret) 2552 goto resume_failed; 2553 2554 ret = regulator_enable(st->reg); 2555 if (ret) 2556 goto resume_failed; 2557 2558 ret = regulator_enable(st->vref); 2559 if (ret) 2560 goto reg_disable_resume; 2561 2562 ret = clk_prepare_enable(st->per_clk); 2563 if (ret) 2564 goto vref_disable_resume; 2565 2566 pm_runtime_get_noresume(st->dev); 2567 2568 at91_adc_hw_init(indio_dev); 2569 2570 /* reconfiguring trigger hardware state */ 2571 if (iio_buffer_enabled(indio_dev)) { 2572 ret = at91_adc_buffer_prepare(indio_dev); 2573 if (ret) 2574 goto pm_runtime_put; 2575 2576 at91_adc_configure_trigger_registers(st, true); 2577 } 2578 2579 pm_runtime_mark_last_busy(st->dev); 2580 pm_runtime_put_autosuspend(st->dev); 2581 2582 return 0; 2583 2584 pm_runtime_put: 2585 pm_runtime_mark_last_busy(st->dev); 2586 pm_runtime_put_noidle(st->dev); 2587 clk_disable_unprepare(st->per_clk); 2588 vref_disable_resume: 2589 regulator_disable(st->vref); 2590 reg_disable_resume: 2591 regulator_disable(st->reg); 2592 resume_failed: 2593 dev_err(&indio_dev->dev, "failed to resume\n"); 2594 return ret; 2595 } 2596 2597 static int at91_adc_runtime_suspend(struct device *dev) 2598 { 2599 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2600 struct at91_adc_state *st = iio_priv(indio_dev); 2601 2602 clk_disable(st->per_clk); 2603 2604 return 0; 2605 } 2606 2607 static int at91_adc_runtime_resume(struct device *dev) 2608 { 2609 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2610 struct at91_adc_state *st = iio_priv(indio_dev); 2611 2612 return clk_enable(st->per_clk); 2613 } 2614 2615 static const struct dev_pm_ops at91_adc_pm_ops = { 2616 SYSTEM_SLEEP_PM_OPS(at91_adc_suspend, at91_adc_resume) 2617 RUNTIME_PM_OPS(at91_adc_runtime_suspend, at91_adc_runtime_resume, 2618 NULL) 2619 }; 2620 2621 static const struct of_device_id at91_adc_dt_match[] = { 2622 { 2623 .compatible = "atmel,sama5d2-adc", 2624 .data = (const void *)&sama5d2_platform, 2625 }, { 2626 .compatible = "microchip,sama7g5-adc", 2627 .data = (const void *)&sama7g5_platform, 2628 }, { 2629 /* sentinel */ 2630 } 2631 }; 2632 MODULE_DEVICE_TABLE(of, at91_adc_dt_match); 2633 2634 static struct platform_driver at91_adc_driver = { 2635 .probe = at91_adc_probe, 2636 .remove = at91_adc_remove, 2637 .driver = { 2638 .name = "at91-sama5d2_adc", 2639 .of_match_table = at91_adc_dt_match, 2640 .pm = pm_ptr(&at91_adc_pm_ops), 2641 }, 2642 }; 2643 module_platform_driver(at91_adc_driver) 2644 2645 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@microchip.com>"); 2646 MODULE_AUTHOR("Eugen Hristev <eugen.hristev@microchip.com"); 2647 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC"); 2648 MODULE_LICENSE("GPL v2"); 2649