1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Aspeed AST2400/2500/2600 ADC 4 * 5 * Copyright (C) 2017 Google, Inc. 6 * Copyright (C) 2021 Aspeed Technology Inc. 7 * 8 * ADC clock formula: 9 * Ast2400/Ast2500: 10 * clock period = period of PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0] + 1) 11 * Ast2600: 12 * clock period = period of PCLK * 2 * (ADC0C[15:0] + 1) 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/err.h> 18 #include <linux/errno.h> 19 #include <linux/io.h> 20 #include <linux/module.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/reset.h> 25 #include <linux/spinlock.h> 26 #include <linux/types.h> 27 #include <linux/bitfield.h> 28 #include <linux/regmap.h> 29 #include <linux/mfd/syscon.h> 30 31 #include <linux/iio/iio.h> 32 #include <linux/iio/driver.h> 33 #include <linux/iopoll.h> 34 35 #define ASPEED_RESOLUTION_BITS 10 36 #define ASPEED_CLOCKS_PER_SAMPLE 12 37 38 #define ASPEED_REG_ENGINE_CONTROL 0x00 39 #define ASPEED_REG_INTERRUPT_CONTROL 0x04 40 #define ASPEED_REG_VGA_DETECT_CONTROL 0x08 41 #define ASPEED_REG_CLOCK_CONTROL 0x0C 42 #define ASPEED_REG_COMPENSATION_TRIM 0xC4 43 /* 44 * The register offset between 0xC8~0xCC can be read and won't affect the 45 * hardware logic in each version of ADC. 46 */ 47 #define ASPEED_REG_MAX 0xD0 48 49 #define ASPEED_ADC_ENGINE_ENABLE BIT(0) 50 #define ASPEED_ADC_OP_MODE GENMASK(3, 1) 51 #define ASPEED_ADC_OP_MODE_PWR_DOWN 0 52 #define ASPEED_ADC_OP_MODE_STANDBY 1 53 #define ASPEED_ADC_OP_MODE_NORMAL 7 54 #define ASPEED_ADC_CTRL_COMPENSATION BIT(4) 55 #define ASPEED_ADC_AUTO_COMPENSATION BIT(5) 56 /* 57 * Bit 6 determines not only the reference voltage range but also the dividing 58 * circuit for battery sensing. 59 */ 60 #define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6) 61 #define ASPEED_ADC_REF_VOLTAGE_2500mV 0 62 #define ASPEED_ADC_REF_VOLTAGE_1200mV 1 63 #define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH 2 64 #define ASPEED_ADC_REF_VOLTAGE_EXT_LOW 3 65 #define ASPEED_ADC_BAT_SENSING_DIV BIT(6) 66 #define ASPEED_ADC_BAT_SENSING_DIV_2_3 0 67 #define ASPEED_ADC_BAT_SENSING_DIV_1_3 1 68 #define ASPEED_ADC_CTRL_INIT_RDY BIT(8) 69 #define ASPEED_ADC_CH7_MODE BIT(12) 70 #define ASPEED_ADC_CH7_NORMAL 0 71 #define ASPEED_ADC_CH7_BAT 1 72 #define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13) 73 #define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) 74 #define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch)) 75 76 #define ASPEED_ADC_INIT_POLLING_TIME 500 77 #define ASPEED_ADC_INIT_TIMEOUT 500000 78 /* Battery sensing is typically on the last channel */ 79 #define ASPEED_ADC_BATTERY_CHANNEL 7 80 /* 81 * When the sampling rate is too high, the ADC may not have enough charging 82 * time, resulting in a low voltage value. Thus, the default uses a slow 83 * sampling rate for most use cases. 84 */ 85 #define ASPEED_ADC_DEF_SAMPLING_RATE 65000 86 87 struct aspeed_adc_trim_locate { 88 const unsigned int offset; 89 const unsigned int field; 90 }; 91 92 struct aspeed_adc_model_data { 93 const char *model_name; 94 unsigned int min_sampling_rate; // Hz 95 unsigned int max_sampling_rate; // Hz 96 unsigned int vref_fixed_mv; 97 bool wait_init_sequence; 98 bool need_prescaler; 99 bool bat_sense_sup; 100 u8 scaler_bit_width; 101 unsigned int num_channels; 102 const struct aspeed_adc_trim_locate *trim_locate; 103 }; 104 105 struct adc_gain { 106 u8 mult; 107 u8 div; 108 }; 109 110 struct aspeed_adc_data { 111 struct device *dev; 112 const struct aspeed_adc_model_data *model_data; 113 void __iomem *base; 114 spinlock_t clk_lock; 115 struct clk_hw *fixed_div_clk; 116 struct clk_hw *clk_prescaler; 117 struct clk_hw *clk_scaler; 118 struct reset_control *rst; 119 int vref_mv; 120 u32 sample_period_ns; 121 int cv; 122 bool battery_sensing; 123 struct adc_gain battery_mode_gain; 124 }; 125 126 /* 127 * Enable multiple consecutive channels starting from channel 0. 128 * This creates a bitmask for channels 0 to (num_channels - 1). 129 * For example: num_channels=3 creates mask 0x0007 (channels 0,1,2) 130 */ 131 static inline u32 aspeed_adc_channels_mask(unsigned int num_channels) 132 { 133 if (num_channels > 16) 134 return GENMASK(15, 0); 135 136 return BIT(num_channels) - 1; 137 } 138 139 static inline unsigned int aspeed_adc_get_active_channels(const struct aspeed_adc_data *data) 140 { 141 /* 142 * For controllers with battery sensing capability, the last channel 143 * is reserved for battery sensing and should not be included in 144 * normal channel operations. 145 */ 146 if (data->model_data->bat_sense_sup) 147 return data->model_data->num_channels - 1; 148 return data->model_data->num_channels; 149 } 150 151 #define ASPEED_CHAN(_idx, _data_reg_addr) { \ 152 .type = IIO_VOLTAGE, \ 153 .indexed = 1, \ 154 .channel = (_idx), \ 155 .address = (_data_reg_addr), \ 156 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 157 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 158 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 159 BIT(IIO_CHAN_INFO_OFFSET), \ 160 } 161 162 static const struct iio_chan_spec aspeed_adc_iio_channels[] = { 163 ASPEED_CHAN(0, 0x10), 164 ASPEED_CHAN(1, 0x12), 165 ASPEED_CHAN(2, 0x14), 166 ASPEED_CHAN(3, 0x16), 167 ASPEED_CHAN(4, 0x18), 168 ASPEED_CHAN(5, 0x1A), 169 ASPEED_CHAN(6, 0x1C), 170 ASPEED_CHAN(7, 0x1E), 171 ASPEED_CHAN(8, 0x20), 172 ASPEED_CHAN(9, 0x22), 173 ASPEED_CHAN(10, 0x24), 174 ASPEED_CHAN(11, 0x26), 175 ASPEED_CHAN(12, 0x28), 176 ASPEED_CHAN(13, 0x2A), 177 ASPEED_CHAN(14, 0x2C), 178 ASPEED_CHAN(15, 0x2E), 179 }; 180 181 #define ASPEED_BAT_CHAN(_idx, _data_reg_addr) { \ 182 .type = IIO_VOLTAGE, \ 183 .indexed = 1, \ 184 .channel = (_idx), \ 185 .address = (_data_reg_addr), \ 186 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 187 BIT(IIO_CHAN_INFO_OFFSET), \ 188 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 189 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 190 } 191 static const struct iio_chan_spec aspeed_adc_iio_bat_channels[] = { 192 ASPEED_CHAN(0, 0x10), 193 ASPEED_CHAN(1, 0x12), 194 ASPEED_CHAN(2, 0x14), 195 ASPEED_CHAN(3, 0x16), 196 ASPEED_CHAN(4, 0x18), 197 ASPEED_CHAN(5, 0x1A), 198 ASPEED_CHAN(6, 0x1C), 199 ASPEED_BAT_CHAN(7, 0x1E), 200 }; 201 202 static int aspeed_adc_set_trim_data(struct iio_dev *indio_dev) 203 { 204 struct device_node *syscon; 205 struct regmap *scu; 206 u32 scu_otp, trimming_val; 207 struct aspeed_adc_data *data = iio_priv(indio_dev); 208 209 syscon = of_find_node_by_name(NULL, "syscon"); 210 if (syscon == NULL) { 211 dev_warn(data->dev, "Couldn't find syscon node\n"); 212 return -EOPNOTSUPP; 213 } 214 scu = syscon_node_to_regmap(syscon); 215 of_node_put(syscon); 216 if (IS_ERR(scu)) { 217 dev_warn(data->dev, "Failed to get syscon regmap\n"); 218 return -EOPNOTSUPP; 219 } 220 if (data->model_data->trim_locate) { 221 if (regmap_read(scu, data->model_data->trim_locate->offset, 222 &scu_otp)) { 223 dev_warn(data->dev, 224 "Failed to get adc trimming data\n"); 225 trimming_val = 0x8; 226 } else { 227 trimming_val = 228 ((scu_otp) & 229 (data->model_data->trim_locate->field)) >> 230 __ffs(data->model_data->trim_locate->field); 231 if (!trimming_val) 232 trimming_val = 0x8; 233 } 234 dev_dbg(data->dev, 235 "trimming val = %d, offset = %08x, fields = %08x\n", 236 trimming_val, data->model_data->trim_locate->offset, 237 data->model_data->trim_locate->field); 238 writel(trimming_val, data->base + ASPEED_REG_COMPENSATION_TRIM); 239 } 240 return 0; 241 } 242 243 static int aspeed_adc_compensation(struct iio_dev *indio_dev) 244 { 245 struct aspeed_adc_data *data = iio_priv(indio_dev); 246 u32 index, adc_raw = 0; 247 u32 adc_engine_control_reg_val; 248 249 adc_engine_control_reg_val = 250 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 251 adc_engine_control_reg_val &= ~ASPEED_ADC_OP_MODE; 252 adc_engine_control_reg_val |= 253 (FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | 254 ASPEED_ADC_ENGINE_ENABLE); 255 /* 256 * Enable compensating sensing: 257 * After that, the input voltage of ADC will force to half of the reference 258 * voltage. So the expected reading raw data will become half of the max 259 * value. We can get compensating value = 0x200 - ADC read raw value. 260 * It is recommended to average at least 10 samples to get a final CV. 261 */ 262 writel(adc_engine_control_reg_val | ASPEED_ADC_CTRL_COMPENSATION | 263 ASPEED_ADC_CTRL_CHANNEL_ENABLE(0), 264 data->base + ASPEED_REG_ENGINE_CONTROL); 265 /* 266 * After enable compensating sensing mode need to wait some time for the 267 * ADC stablize. Experiment result is 1ms. 268 */ 269 fsleep(1000); 270 271 for (index = 0; index < 16; index++) { 272 /* 273 * Waiting for the sampling period ensures that the value acquired 274 * is fresh each time. 275 */ 276 ndelay(data->sample_period_ns); 277 adc_raw += readw(data->base + aspeed_adc_iio_channels[0].address); 278 } 279 adc_raw >>= 4; 280 data->cv = BIT(ASPEED_RESOLUTION_BITS - 1) - adc_raw; 281 writel(adc_engine_control_reg_val, 282 data->base + ASPEED_REG_ENGINE_CONTROL); 283 dev_dbg(data->dev, "Compensating value = %d\n", data->cv); 284 285 return 0; 286 } 287 288 static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate) 289 { 290 struct aspeed_adc_data *data = iio_priv(indio_dev); 291 292 if (rate < data->model_data->min_sampling_rate || 293 rate > data->model_data->max_sampling_rate) 294 return -EINVAL; 295 /* Each sampling needs 12 clocks to convert.*/ 296 clk_set_rate(data->clk_scaler->clk, rate * ASPEED_CLOCKS_PER_SAMPLE); 297 rate = clk_get_rate(data->clk_scaler->clk); 298 data->sample_period_ns = DIV_ROUND_UP_ULL( 299 (u64)NSEC_PER_SEC * ASPEED_CLOCKS_PER_SAMPLE, rate); 300 dev_dbg(data->dev, "Adc clock = %d sample period = %d ns", rate, 301 data->sample_period_ns); 302 303 return 0; 304 } 305 306 static int aspeed_adc_read_raw(struct iio_dev *indio_dev, 307 struct iio_chan_spec const *chan, 308 int *val, int *val2, long mask) 309 { 310 struct aspeed_adc_data *data = iio_priv(indio_dev); 311 u32 adc_engine_control_reg_val; 312 313 switch (mask) { 314 case IIO_CHAN_INFO_RAW: 315 adc_engine_control_reg_val = readl(data->base + ASPEED_REG_ENGINE_CONTROL); 316 /* 317 * For battery sensing capable controllers, we need to enable 318 * the specific channel before reading. This is required because 319 * the battery channel may not be enabled by default. 320 */ 321 if (data->model_data->bat_sense_sup && 322 chan->channel == ASPEED_ADC_BATTERY_CHANNEL) { 323 u32 ctrl_reg = adc_engine_control_reg_val & ~ASPEED_ADC_CTRL_CHANNEL; 324 325 ctrl_reg |= ASPEED_ADC_CTRL_CHANNEL_ENABLE(chan->channel); 326 writel(ctrl_reg, data->base + ASPEED_REG_ENGINE_CONTROL); 327 /* 328 * After enable a new channel need to wait some time for ADC stable 329 * Experiment result is 1ms. 330 */ 331 fsleep(1000); 332 } 333 334 if (data->battery_sensing && chan->channel == ASPEED_ADC_BATTERY_CHANNEL) { 335 writel(adc_engine_control_reg_val | 336 FIELD_PREP(ASPEED_ADC_CH7_MODE, 337 ASPEED_ADC_CH7_BAT) | 338 ASPEED_ADC_BAT_SENSING_ENABLE, 339 data->base + ASPEED_REG_ENGINE_CONTROL); 340 /* 341 * After enable battery sensing mode need to wait some time for ADC stable 342 * Experiment result is 1ms. 343 */ 344 fsleep(1000); 345 *val = readw(data->base + chan->address); 346 *val = (*val * data->battery_mode_gain.mult) / 347 data->battery_mode_gain.div; 348 } else 349 *val = readw(data->base + chan->address); 350 /* Restore control register value */ 351 writel(adc_engine_control_reg_val, 352 data->base + ASPEED_REG_ENGINE_CONTROL); 353 return IIO_VAL_INT; 354 355 case IIO_CHAN_INFO_OFFSET: 356 if (data->battery_sensing && chan->channel == ASPEED_ADC_BATTERY_CHANNEL) 357 *val = (data->cv * data->battery_mode_gain.mult) / 358 data->battery_mode_gain.div; 359 else 360 *val = data->cv; 361 return IIO_VAL_INT; 362 363 case IIO_CHAN_INFO_SCALE: 364 *val = data->vref_mv; 365 *val2 = ASPEED_RESOLUTION_BITS; 366 return IIO_VAL_FRACTIONAL_LOG2; 367 368 case IIO_CHAN_INFO_SAMP_FREQ: 369 *val = clk_get_rate(data->clk_scaler->clk) / 370 ASPEED_CLOCKS_PER_SAMPLE; 371 return IIO_VAL_INT; 372 373 default: 374 return -EINVAL; 375 } 376 } 377 378 static int aspeed_adc_write_raw(struct iio_dev *indio_dev, 379 struct iio_chan_spec const *chan, 380 int val, int val2, long mask) 381 { 382 switch (mask) { 383 case IIO_CHAN_INFO_SAMP_FREQ: 384 return aspeed_adc_set_sampling_rate(indio_dev, val); 385 386 case IIO_CHAN_INFO_SCALE: 387 case IIO_CHAN_INFO_RAW: 388 /* 389 * Technically, these could be written but the only reasons 390 * for doing so seem better handled in userspace. EPERM is 391 * returned to signal this is a policy choice rather than a 392 * hardware limitation. 393 */ 394 return -EPERM; 395 396 default: 397 return -EINVAL; 398 } 399 } 400 401 static int aspeed_adc_reg_access(struct iio_dev *indio_dev, 402 unsigned int reg, unsigned int writeval, 403 unsigned int *readval) 404 { 405 struct aspeed_adc_data *data = iio_priv(indio_dev); 406 407 if (!readval || reg % 4 || reg > ASPEED_REG_MAX) 408 return -EINVAL; 409 410 *readval = readl(data->base + reg); 411 412 return 0; 413 } 414 415 static const struct iio_info aspeed_adc_iio_info = { 416 .read_raw = aspeed_adc_read_raw, 417 .write_raw = aspeed_adc_write_raw, 418 .debugfs_reg_access = aspeed_adc_reg_access, 419 }; 420 421 static void aspeed_adc_unregister_fixed_divider(void *data) 422 { 423 struct clk_hw *clk = data; 424 425 clk_hw_unregister_fixed_factor(clk); 426 } 427 428 static void aspeed_adc_reset_assert(void *data) 429 { 430 struct reset_control *rst = data; 431 432 reset_control_assert(rst); 433 } 434 435 static void aspeed_adc_clk_disable_unprepare(void *data) 436 { 437 struct clk *clk = data; 438 439 clk_disable_unprepare(clk); 440 } 441 442 static void aspeed_adc_power_down(void *data) 443 { 444 struct aspeed_adc_data *priv_data = data; 445 446 writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), 447 priv_data->base + ASPEED_REG_ENGINE_CONTROL); 448 } 449 450 static int aspeed_adc_vref_config(struct iio_dev *indio_dev) 451 { 452 struct aspeed_adc_data *data = iio_priv(indio_dev); 453 int ret; 454 u32 adc_engine_control_reg_val; 455 456 if (data->model_data->vref_fixed_mv) { 457 data->vref_mv = data->model_data->vref_fixed_mv; 458 return 0; 459 } 460 adc_engine_control_reg_val = 461 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 462 adc_engine_control_reg_val &= ~ASPEED_ADC_REF_VOLTAGE; 463 464 ret = devm_regulator_get_enable_read_voltage(data->dev, "vref"); 465 if (ret < 0 && ret != -ENODEV) 466 return ret; 467 468 if (ret != -ENODEV) { 469 data->vref_mv = ret / 1000; 470 471 if ((data->vref_mv >= 1550) && (data->vref_mv <= 2700)) 472 writel(adc_engine_control_reg_val | 473 FIELD_PREP( 474 ASPEED_ADC_REF_VOLTAGE, 475 ASPEED_ADC_REF_VOLTAGE_EXT_HIGH), 476 data->base + ASPEED_REG_ENGINE_CONTROL); 477 else if ((data->vref_mv >= 900) && (data->vref_mv <= 1650)) 478 writel(adc_engine_control_reg_val | 479 FIELD_PREP( 480 ASPEED_ADC_REF_VOLTAGE, 481 ASPEED_ADC_REF_VOLTAGE_EXT_LOW), 482 data->base + ASPEED_REG_ENGINE_CONTROL); 483 else { 484 dev_err(data->dev, "Regulator voltage %d not support", 485 data->vref_mv); 486 return -EOPNOTSUPP; 487 } 488 } else { 489 data->vref_mv = 2500000; 490 of_property_read_u32(data->dev->of_node, 491 "aspeed,int-vref-microvolt", 492 &data->vref_mv); 493 /* Conversion from uV to mV */ 494 data->vref_mv /= 1000; 495 if (data->vref_mv == 2500) 496 writel(adc_engine_control_reg_val | 497 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE, 498 ASPEED_ADC_REF_VOLTAGE_2500mV), 499 data->base + ASPEED_REG_ENGINE_CONTROL); 500 else if (data->vref_mv == 1200) 501 writel(adc_engine_control_reg_val | 502 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE, 503 ASPEED_ADC_REF_VOLTAGE_1200mV), 504 data->base + ASPEED_REG_ENGINE_CONTROL); 505 else { 506 dev_err(data->dev, "Voltage %d not support", data->vref_mv); 507 return -EOPNOTSUPP; 508 } 509 } 510 511 return 0; 512 } 513 514 static int aspeed_adc_probe(struct platform_device *pdev) 515 { 516 struct iio_dev *indio_dev; 517 struct aspeed_adc_data *data; 518 int ret; 519 u32 adc_engine_control_reg_val; 520 struct device *dev = &pdev->dev; 521 struct device_node *np = dev_of_node(dev); 522 unsigned long scaler_flags = 0; 523 char clk_name[32], clk_parent_name[32]; 524 525 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 526 if (!indio_dev) 527 return -ENOMEM; 528 529 data = iio_priv(indio_dev); 530 data->dev = dev; 531 data->model_data = of_device_get_match_data(dev); 532 platform_set_drvdata(pdev, indio_dev); 533 534 data->base = devm_platform_ioremap_resource(pdev, 0); 535 if (IS_ERR(data->base)) 536 return PTR_ERR(data->base); 537 538 /* Register ADC clock prescaler with source specified by device tree. */ 539 spin_lock_init(&data->clk_lock); 540 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), "%s", 541 of_clk_get_parent_name(np, 0)); 542 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-fixed-div", 543 data->model_data->model_name); 544 data->fixed_div_clk = clk_hw_register_fixed_factor(dev, clk_name, 545 clk_parent_name, 0, 1, 2); 546 if (IS_ERR(data->fixed_div_clk)) 547 return PTR_ERR(data->fixed_div_clk); 548 549 ret = devm_add_action_or_reset(dev, aspeed_adc_unregister_fixed_divider, 550 data->fixed_div_clk); 551 if (ret) 552 return ret; 553 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), clk_name); 554 555 if (data->model_data->need_prescaler) { 556 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-prescaler", 557 data->model_data->model_name); 558 data->clk_prescaler = devm_clk_hw_register_divider( 559 dev, clk_name, clk_parent_name, 0, 560 data->base + ASPEED_REG_CLOCK_CONTROL, 17, 15, 0, 561 &data->clk_lock); 562 if (IS_ERR(data->clk_prescaler)) 563 return PTR_ERR(data->clk_prescaler); 564 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), 565 clk_name); 566 scaler_flags = CLK_SET_RATE_PARENT; 567 } 568 /* 569 * Register ADC clock scaler downstream from the prescaler. Allow rate 570 * setting to adjust the prescaler as well. 571 */ 572 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-scaler", 573 data->model_data->model_name); 574 data->clk_scaler = devm_clk_hw_register_divider( 575 dev, clk_name, clk_parent_name, scaler_flags, 576 data->base + ASPEED_REG_CLOCK_CONTROL, 0, 577 data->model_data->scaler_bit_width, 578 data->model_data->need_prescaler ? CLK_DIVIDER_ONE_BASED : 0, 579 &data->clk_lock); 580 if (IS_ERR(data->clk_scaler)) 581 return PTR_ERR(data->clk_scaler); 582 583 data->rst = devm_reset_control_get_shared(dev, NULL); 584 if (IS_ERR(data->rst)) 585 return dev_err_probe(dev, PTR_ERR(data->rst), 586 "invalid or missing reset controller device tree entry"); 587 588 reset_control_deassert(data->rst); 589 590 ret = devm_add_action_or_reset(dev, aspeed_adc_reset_assert, data->rst); 591 if (ret) 592 return ret; 593 594 ret = aspeed_adc_vref_config(indio_dev); 595 if (ret) 596 return ret; 597 598 ret = aspeed_adc_set_trim_data(indio_dev); 599 if (ret) 600 return ret; 601 602 if (of_property_present(np, "aspeed,battery-sensing")) { 603 if (data->model_data->bat_sense_sup) { 604 data->battery_sensing = 1; 605 if (readl(data->base + ASPEED_REG_ENGINE_CONTROL) & 606 ASPEED_ADC_BAT_SENSING_DIV) { 607 data->battery_mode_gain.mult = 3; 608 data->battery_mode_gain.div = 1; 609 } else { 610 data->battery_mode_gain.mult = 3; 611 data->battery_mode_gain.div = 2; 612 } 613 } else 614 dev_warn(dev, "Failed to enable battery-sensing mode\n"); 615 } 616 617 ret = clk_prepare_enable(data->clk_scaler->clk); 618 if (ret) 619 return ret; 620 ret = devm_add_action_or_reset(dev, aspeed_adc_clk_disable_unprepare, 621 data->clk_scaler->clk); 622 if (ret) 623 return ret; 624 ret = aspeed_adc_set_sampling_rate(indio_dev, 625 ASPEED_ADC_DEF_SAMPLING_RATE); 626 if (ret) 627 return ret; 628 629 adc_engine_control_reg_val = 630 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 631 adc_engine_control_reg_val |= 632 FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | 633 ASPEED_ADC_ENGINE_ENABLE; 634 /* Enable engine in normal mode. */ 635 writel(adc_engine_control_reg_val, 636 data->base + ASPEED_REG_ENGINE_CONTROL); 637 638 ret = devm_add_action_or_reset(dev, aspeed_adc_power_down, data); 639 if (ret) 640 return ret; 641 642 if (data->model_data->wait_init_sequence) { 643 /* Wait for initial sequence complete. */ 644 ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL, 645 adc_engine_control_reg_val, 646 adc_engine_control_reg_val & 647 ASPEED_ADC_CTRL_INIT_RDY, 648 ASPEED_ADC_INIT_POLLING_TIME, 649 ASPEED_ADC_INIT_TIMEOUT); 650 if (ret) 651 return ret; 652 } 653 654 aspeed_adc_compensation(indio_dev); 655 /* Start all channels in normal mode. */ 656 adc_engine_control_reg_val = 657 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 658 FIELD_MODIFY(ASPEED_ADC_CTRL_CHANNEL, &adc_engine_control_reg_val, 659 aspeed_adc_channels_mask(aspeed_adc_get_active_channels(data))); 660 661 writel(adc_engine_control_reg_val, 662 data->base + ASPEED_REG_ENGINE_CONTROL); 663 664 indio_dev->name = data->model_data->model_name; 665 indio_dev->info = &aspeed_adc_iio_info; 666 indio_dev->modes = INDIO_DIRECT_MODE; 667 indio_dev->channels = data->battery_sensing ? 668 aspeed_adc_iio_bat_channels : 669 aspeed_adc_iio_channels; 670 indio_dev->num_channels = data->model_data->num_channels; 671 672 return devm_iio_device_register(dev, indio_dev); 673 } 674 675 static const struct aspeed_adc_trim_locate ast2500_adc_trim = { 676 .offset = 0x154, 677 .field = GENMASK(31, 28), 678 }; 679 680 static const struct aspeed_adc_trim_locate ast2600_adc0_trim = { 681 .offset = 0x5d0, 682 .field = GENMASK(3, 0), 683 }; 684 685 static const struct aspeed_adc_trim_locate ast2600_adc1_trim = { 686 .offset = 0x5d0, 687 .field = GENMASK(7, 4), 688 }; 689 690 static const struct aspeed_adc_trim_locate ast2700_adc0_trim = { 691 .offset = 0x820, 692 .field = GENMASK(3, 0), 693 }; 694 695 static const struct aspeed_adc_trim_locate ast2700_adc1_trim = { 696 .offset = 0x820, 697 .field = GENMASK(7, 4), 698 }; 699 700 static const struct aspeed_adc_model_data ast2400_model_data = { 701 .model_name = "ast2400-adc", 702 .vref_fixed_mv = 2500, 703 .min_sampling_rate = 10000, 704 .max_sampling_rate = 500000, 705 .need_prescaler = true, 706 .scaler_bit_width = 10, 707 .num_channels = 16, 708 }; 709 710 static const struct aspeed_adc_model_data ast2500_model_data = { 711 .model_name = "ast2500-adc", 712 .vref_fixed_mv = 1800, 713 .min_sampling_rate = 1, 714 .max_sampling_rate = 1000000, 715 .wait_init_sequence = true, 716 .need_prescaler = true, 717 .scaler_bit_width = 10, 718 .num_channels = 16, 719 .trim_locate = &ast2500_adc_trim, 720 }; 721 722 static const struct aspeed_adc_model_data ast2600_adc0_model_data = { 723 .model_name = "ast2600-adc0", 724 .min_sampling_rate = 10000, 725 .max_sampling_rate = 500000, 726 .wait_init_sequence = true, 727 .bat_sense_sup = true, 728 .scaler_bit_width = 16, 729 .num_channels = 8, 730 .trim_locate = &ast2600_adc0_trim, 731 }; 732 733 static const struct aspeed_adc_model_data ast2600_adc1_model_data = { 734 .model_name = "ast2600-adc1", 735 .min_sampling_rate = 10000, 736 .max_sampling_rate = 500000, 737 .wait_init_sequence = true, 738 .bat_sense_sup = true, 739 .scaler_bit_width = 16, 740 .num_channels = 8, 741 .trim_locate = &ast2600_adc1_trim, 742 }; 743 744 static const struct aspeed_adc_model_data ast2700_adc0_model_data = { 745 .model_name = "ast2700-adc0", 746 .min_sampling_rate = 10000, 747 .max_sampling_rate = 500000, 748 .wait_init_sequence = true, 749 .bat_sense_sup = true, 750 .scaler_bit_width = 16, 751 .num_channels = 8, 752 .trim_locate = &ast2700_adc0_trim, 753 }; 754 755 static const struct aspeed_adc_model_data ast2700_adc1_model_data = { 756 .model_name = "ast2700-adc1", 757 .min_sampling_rate = 10000, 758 .max_sampling_rate = 500000, 759 .wait_init_sequence = true, 760 .bat_sense_sup = true, 761 .scaler_bit_width = 16, 762 .num_channels = 8, 763 .trim_locate = &ast2700_adc1_trim, 764 }; 765 766 static const struct of_device_id aspeed_adc_matches[] = { 767 { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data }, 768 { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data }, 769 { .compatible = "aspeed,ast2600-adc0", .data = &ast2600_adc0_model_data }, 770 { .compatible = "aspeed,ast2600-adc1", .data = &ast2600_adc1_model_data }, 771 { .compatible = "aspeed,ast2700-adc0", .data = &ast2700_adc0_model_data }, 772 { .compatible = "aspeed,ast2700-adc1", .data = &ast2700_adc1_model_data }, 773 { } 774 }; 775 MODULE_DEVICE_TABLE(of, aspeed_adc_matches); 776 777 static struct platform_driver aspeed_adc_driver = { 778 .probe = aspeed_adc_probe, 779 .driver = { 780 .name = KBUILD_MODNAME, 781 .of_match_table = aspeed_adc_matches, 782 } 783 }; 784 785 module_platform_driver(aspeed_adc_driver); 786 787 MODULE_AUTHOR("Rick Altherr <raltherr@google.com>"); 788 MODULE_DESCRIPTION("Aspeed AST2400/2500/2600 ADC Driver"); 789 MODULE_LICENSE("GPL"); 790