1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices Generic AXI ADC IP core 4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 5 * 6 * Copyright 2012-2020 Analog Devices Inc. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/delay.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 23 #include <linux/fpga/adi-axi-common.h> 24 25 #include <linux/iio/backend.h> 26 #include <linux/iio/buffer-dmaengine.h> 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/iio.h> 29 30 #include "ad7606_bus_iface.h" 31 /* 32 * Register definitions: 33 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map 34 */ 35 36 /* ADC controls */ 37 38 #define ADI_AXI_REG_RSTN 0x0040 39 #define ADI_AXI_REG_RSTN_CE_N BIT(2) 40 #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1) 41 #define ADI_AXI_REG_RSTN_RSTN BIT(0) 42 43 #define ADI_AXI_ADC_REG_CONFIG 0x000c 44 #define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) 45 46 #define ADI_AXI_ADC_REG_CTRL 0x0044 47 #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) 48 49 #define ADI_AXI_ADC_REG_CNTRL_3 0x004c 50 #define AXI_AD485X_CNTRL_3_OS_EN_MSK BIT(2) 51 #define AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK GENMASK(1, 0) 52 #define AXI_AD485X_PACKET_FORMAT_20BIT 0x0 53 #define AXI_AD485X_PACKET_FORMAT_24BIT 0x1 54 #define AXI_AD485X_PACKET_FORMAT_32BIT 0x2 55 56 #define ADI_AXI_ADC_REG_DRP_STATUS 0x0074 57 #define ADI_AXI_ADC_DRP_LOCKED BIT(17) 58 59 /* ADC Channel controls */ 60 61 #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40) 62 #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11) 63 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10) 64 #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9) 65 #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8) 66 #define ADI_AXI_REG_CHAN_CTRL_FMT_MASK GENMASK(6, 4) 67 #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6) 68 #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5) 69 #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4) 70 #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1) 71 #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0) 72 73 #define ADI_AXI_ADC_REG_CHAN_STATUS(c) (0x0404 + (c) * 0x40) 74 #define ADI_AXI_ADC_CHAN_STAT_PN_MASK GENMASK(2, 1) 75 /* out of sync */ 76 #define ADI_AXI_ADC_CHAN_STAT_PN_OOS BIT(1) 77 /* spurious out of sync */ 78 #define ADI_AXI_ADC_CHAN_STAT_PN_ERR BIT(2) 79 80 #define ADI_AXI_ADC_REG_CHAN_CTRL_3(c) (0x0418 + (c) * 0x40) 81 #define ADI_AXI_ADC_CHAN_PN_SEL_MASK GENMASK(19, 16) 82 83 /* IO Delays */ 84 #define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4) 85 #define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0) 86 87 #define ADI_AXI_REG_CONFIG_WR 0x0080 88 #define ADI_AXI_REG_CONFIG_RD 0x0084 89 #define ADI_AXI_REG_CONFIG_CTRL 0x008c 90 #define ADI_AXI_REG_CONFIG_CTRL_READ 0x03 91 #define ADI_AXI_REG_CONFIG_CTRL_WRITE 0x01 92 93 #define ADI_AXI_ADC_MAX_IO_NUM_LANES 15 94 95 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \ 96 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \ 97 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ 98 ADI_AXI_REG_CHAN_CTRL_ENABLE) 99 100 #define ADI_AXI_REG_READ_BIT 0x8000 101 #define ADI_AXI_REG_ADDRESS_MASK 0xff00 102 #define ADI_AXI_REG_VALUE_MASK 0x00ff 103 104 struct axi_adc_info { 105 unsigned int version; 106 const struct iio_backend_info *backend_info; 107 bool has_child_nodes; 108 const void *pdata; 109 unsigned int pdata_sz; 110 }; 111 112 struct adi_axi_adc_state { 113 const struct axi_adc_info *info; 114 struct regmap *regmap; 115 struct device *dev; 116 /* lock to protect multiple accesses to the device registers */ 117 struct mutex lock; 118 }; 119 120 static int axi_adc_enable(struct iio_backend *back) 121 { 122 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 123 unsigned int __val; 124 int ret; 125 126 guard(mutex)(&st->lock); 127 ret = regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, 128 ADI_AXI_REG_RSTN_MMCM_RSTN); 129 if (ret) 130 return ret; 131 132 /* 133 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all 134 * designs really use it but if they don't we still get the lock bit 135 * set. So let's do it all the time so the code is generic. 136 */ 137 ret = regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_DRP_STATUS, 138 __val, __val & ADI_AXI_ADC_DRP_LOCKED, 139 100, 1000); 140 if (ret) 141 return ret; 142 143 return regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, 144 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN); 145 } 146 147 static void axi_adc_disable(struct iio_backend *back) 148 { 149 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 150 151 guard(mutex)(&st->lock); 152 regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0); 153 } 154 155 static int axi_adc_data_format_set(struct iio_backend *back, unsigned int chan, 156 const struct iio_backend_data_fmt *data) 157 { 158 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 159 u32 val; 160 161 if (!data->enable) 162 return regmap_clear_bits(st->regmap, 163 ADI_AXI_REG_CHAN_CTRL(chan), 164 ADI_AXI_REG_CHAN_CTRL_FMT_EN); 165 166 val = FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_EN, true); 167 if (data->sign_extend) 168 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT, true); 169 if (data->type == IIO_BACKEND_OFFSET_BINARY) 170 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_TYPE, true); 171 172 return regmap_update_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 173 ADI_AXI_REG_CHAN_CTRL_FMT_MASK, val); 174 } 175 176 static int axi_adc_data_sample_trigger(struct iio_backend *back, 177 enum iio_backend_sample_trigger trigger) 178 { 179 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 180 181 switch (trigger) { 182 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING: 183 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 184 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK); 185 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING: 186 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 187 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK); 188 default: 189 return -EINVAL; 190 } 191 } 192 193 static int axi_adc_iodelays_set(struct iio_backend *back, unsigned int lane, 194 unsigned int tap) 195 { 196 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 197 int ret; 198 u32 val; 199 200 if (tap > FIELD_MAX(AXI_ADC_DELAY_CTRL_MASK)) 201 return -EINVAL; 202 if (lane > ADI_AXI_ADC_MAX_IO_NUM_LANES) 203 return -EINVAL; 204 205 guard(mutex)(&st->lock); 206 ret = regmap_write(st->regmap, ADI_AXI_ADC_REG_DELAY(lane), tap); 207 if (ret) 208 return ret; 209 /* 210 * If readback is ~0, that means there are issues with the 211 * delay_clk. 212 */ 213 ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_DELAY(lane), &val); 214 if (ret) 215 return ret; 216 if (val == U32_MAX) 217 return -EIO; 218 219 return 0; 220 } 221 222 static int axi_adc_test_pattern_set(struct iio_backend *back, 223 unsigned int chan, 224 enum iio_backend_test_pattern pattern) 225 { 226 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 227 228 switch (pattern) { 229 case IIO_BACKEND_NO_TEST_PATTERN: 230 /* nothing to do */ 231 return 0; 232 case IIO_BACKEND_ADI_PRBS_9A: 233 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CHAN_CTRL_3(chan), 234 ADI_AXI_ADC_CHAN_PN_SEL_MASK, 235 FIELD_PREP(ADI_AXI_ADC_CHAN_PN_SEL_MASK, 0)); 236 case IIO_BACKEND_ADI_PRBS_23A: 237 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CHAN_CTRL_3(chan), 238 ADI_AXI_ADC_CHAN_PN_SEL_MASK, 239 FIELD_PREP(ADI_AXI_ADC_CHAN_PN_SEL_MASK, 1)); 240 default: 241 return -EINVAL; 242 } 243 } 244 245 static int axi_adc_read_chan_status(struct adi_axi_adc_state *st, unsigned int chan, 246 unsigned int *status) 247 { 248 int ret; 249 250 guard(mutex)(&st->lock); 251 /* reset test bits by setting them */ 252 ret = regmap_write(st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan), 253 ADI_AXI_ADC_CHAN_STAT_PN_MASK); 254 if (ret) 255 return ret; 256 257 /* let's give enough time to validate or erroring the incoming pattern */ 258 fsleep(1000); 259 260 return regmap_read(st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan), 261 status); 262 } 263 264 static int axi_adc_chan_status(struct iio_backend *back, unsigned int chan, 265 bool *error) 266 { 267 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 268 u32 val; 269 int ret; 270 271 ret = axi_adc_read_chan_status(st, chan, &val); 272 if (ret) 273 return ret; 274 275 if (ADI_AXI_ADC_CHAN_STAT_PN_MASK & val) 276 *error = true; 277 else 278 *error = false; 279 280 return 0; 281 } 282 283 static int axi_adc_debugfs_print_chan_status(struct iio_backend *back, 284 unsigned int chan, char *buf, 285 size_t len) 286 { 287 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 288 u32 val; 289 int ret; 290 291 ret = axi_adc_read_chan_status(st, chan, &val); 292 if (ret) 293 return ret; 294 295 /* 296 * PN_ERR is cleared in case out of sync is set. Hence, no point in 297 * checking both bits. 298 */ 299 if (val & ADI_AXI_ADC_CHAN_STAT_PN_OOS) 300 return scnprintf(buf, len, "CH%u: Out of Sync.\n", chan); 301 if (val & ADI_AXI_ADC_CHAN_STAT_PN_ERR) 302 return scnprintf(buf, len, "CH%u: Spurious Out of Sync.\n", chan); 303 304 return scnprintf(buf, len, "CH%u: OK.\n", chan); 305 } 306 307 static int axi_adc_chan_enable(struct iio_backend *back, unsigned int chan) 308 { 309 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 310 311 return regmap_set_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 312 ADI_AXI_REG_CHAN_CTRL_ENABLE); 313 } 314 315 static int axi_adc_chan_disable(struct iio_backend *back, unsigned int chan) 316 { 317 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 318 319 return regmap_clear_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 320 ADI_AXI_REG_CHAN_CTRL_ENABLE); 321 } 322 323 static int axi_adc_interface_type_get(struct iio_backend *back, 324 enum iio_backend_interface_type *type) 325 { 326 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 327 unsigned int val; 328 int ret; 329 330 ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_CONFIG, &val); 331 if (ret) 332 return ret; 333 334 if (val & ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N) 335 *type = IIO_BACKEND_INTERFACE_SERIAL_CMOS; 336 else 337 *type = IIO_BACKEND_INTERFACE_SERIAL_LVDS; 338 339 return 0; 340 } 341 342 static int axi_adc_ad485x_data_size_set(struct iio_backend *back, 343 unsigned int size) 344 { 345 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 346 unsigned int val; 347 348 switch (size) { 349 /* 350 * There are two different variants of the AXI AXI_AD485X IP block, a 351 * 16-bit and a 20-bit variant. 352 * The 0x0 value (AXI_AD485X_PACKET_FORMAT_20BIT) is corresponding also 353 * to the 16-bit variant of the IP block. 354 */ 355 case 16: 356 case 20: 357 val = AXI_AD485X_PACKET_FORMAT_20BIT; 358 break; 359 case 24: 360 val = AXI_AD485X_PACKET_FORMAT_24BIT; 361 break; 362 /* 363 * The 0x2 (AXI_AD485X_PACKET_FORMAT_32BIT) corresponds only to the 364 * 20-bit variant of the IP block. Setting this value properly is 365 * ensured by the upper layers of the drivers calling the axi-adc 366 * functions. 367 * Also, for 16-bit IP block, the 0x2 (AXI_AD485X_PACKET_FORMAT_32BIT) 368 * value is handled as maximum size available which is 24-bit for this 369 * configuration. 370 */ 371 case 32: 372 val = AXI_AD485X_PACKET_FORMAT_32BIT; 373 break; 374 default: 375 return -EINVAL; 376 } 377 378 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 379 AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK, 380 FIELD_PREP(AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK, val)); 381 } 382 383 static int axi_adc_ad485x_oversampling_ratio_set(struct iio_backend *back, 384 unsigned int ratio) 385 { 386 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 387 388 /* The current state of the function enables or disables the 389 * oversampling in REG_CNTRL_3 register. A ratio equal to 1 implies no 390 * oversampling, while a value greater than 1 implies oversampling being 391 * enabled. 392 */ 393 switch (ratio) { 394 case 0: 395 return -EINVAL; 396 case 1: 397 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 398 AXI_AD485X_CNTRL_3_OS_EN_MSK); 399 default: 400 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 401 AXI_AD485X_CNTRL_3_OS_EN_MSK); 402 } 403 } 404 405 static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, 406 struct iio_dev *indio_dev) 407 { 408 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 409 const char *dma_name; 410 411 if (device_property_read_string(st->dev, "dma-names", &dma_name)) 412 dma_name = "rx"; 413 414 return iio_dmaengine_buffer_setup(st->dev, indio_dev, dma_name); 415 } 416 417 static int axi_adc_raw_write(struct iio_backend *back, u32 val) 418 { 419 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 420 421 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_WR, val); 422 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 423 ADI_AXI_REG_CONFIG_CTRL_WRITE); 424 fsleep(100); 425 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); 426 fsleep(100); 427 428 return 0; 429 } 430 431 static int axi_adc_raw_read(struct iio_backend *back, u32 *val) 432 { 433 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 434 435 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 436 ADI_AXI_REG_CONFIG_CTRL_READ); 437 fsleep(100); 438 regmap_read(st->regmap, ADI_AXI_REG_CONFIG_RD, val); 439 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); 440 fsleep(100); 441 442 return 0; 443 } 444 445 static int ad7606_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val) 446 { 447 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 448 u32 addr, reg_val; 449 450 guard(mutex)(&st->lock); 451 452 /* 453 * The address is written on the highest weight byte, and the MSB set 454 * at 1 indicates a read operation. 455 */ 456 addr = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | ADI_AXI_REG_READ_BIT; 457 axi_adc_raw_write(back, addr); 458 axi_adc_raw_read(back, ®_val); 459 460 *val = FIELD_GET(ADI_AXI_REG_VALUE_MASK, reg_val); 461 462 /* Write 0x0 on the bus to get back to ADC mode */ 463 axi_adc_raw_write(back, 0); 464 465 return 0; 466 } 467 468 static int ad7606_bus_reg_write(struct iio_backend *back, u32 reg, u32 val) 469 { 470 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 471 u32 buf; 472 473 guard(mutex)(&st->lock); 474 475 /* Write any register to switch to register mode */ 476 axi_adc_raw_write(back, 0xaf00); 477 478 buf = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | 479 FIELD_PREP(ADI_AXI_REG_VALUE_MASK, val); 480 axi_adc_raw_write(back, buf); 481 482 /* Write 0x0 on the bus to get back to ADC mode */ 483 axi_adc_raw_write(back, 0); 484 485 return 0; 486 } 487 488 static void axi_adc_free_buffer(struct iio_backend *back, 489 struct iio_buffer *buffer) 490 { 491 iio_dmaengine_buffer_teardown(buffer); 492 } 493 494 static int axi_adc_reg_access(struct iio_backend *back, unsigned int reg, 495 unsigned int writeval, unsigned int *readval) 496 { 497 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 498 499 if (readval) 500 return regmap_read(st->regmap, reg, readval); 501 502 return regmap_write(st->regmap, reg, writeval); 503 } 504 505 static const struct regmap_config axi_adc_regmap_config = { 506 .val_bits = 32, 507 .reg_bits = 32, 508 .reg_stride = 4, 509 }; 510 511 static void axi_adc_child_remove(void *data) 512 { 513 platform_device_unregister(data); 514 } 515 516 static int axi_adc_create_platform_device(struct adi_axi_adc_state *st, 517 struct fwnode_handle *child) 518 { 519 struct platform_device_info pi = { 520 .parent = st->dev, 521 .name = fwnode_get_name(child), 522 .id = PLATFORM_DEVID_AUTO, 523 .fwnode = child, 524 .data = st->info->pdata, 525 .size_data = st->info->pdata_sz, 526 }; 527 struct platform_device *pdev; 528 int ret; 529 530 pdev = platform_device_register_full(&pi); 531 if (IS_ERR(pdev)) 532 return PTR_ERR(pdev); 533 534 ret = devm_add_action_or_reset(st->dev, axi_adc_child_remove, pdev); 535 if (ret) 536 return ret; 537 538 return 0; 539 } 540 541 static const struct iio_backend_ops adi_axi_adc_ops = { 542 .enable = axi_adc_enable, 543 .disable = axi_adc_disable, 544 .data_format_set = axi_adc_data_format_set, 545 .chan_enable = axi_adc_chan_enable, 546 .chan_disable = axi_adc_chan_disable, 547 .request_buffer = axi_adc_request_buffer, 548 .free_buffer = axi_adc_free_buffer, 549 .data_sample_trigger = axi_adc_data_sample_trigger, 550 .iodelay_set = axi_adc_iodelays_set, 551 .test_pattern_set = axi_adc_test_pattern_set, 552 .chan_status = axi_adc_chan_status, 553 .interface_type_get = axi_adc_interface_type_get, 554 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access), 555 .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), 556 }; 557 558 static const struct iio_backend_info adi_axi_adc_generic = { 559 .name = "axi-adc", 560 .ops = &adi_axi_adc_ops, 561 }; 562 563 static const struct iio_backend_ops adi_ad485x_ops = { 564 .enable = axi_adc_enable, 565 .disable = axi_adc_disable, 566 .data_format_set = axi_adc_data_format_set, 567 .chan_enable = axi_adc_chan_enable, 568 .chan_disable = axi_adc_chan_disable, 569 .request_buffer = axi_adc_request_buffer, 570 .free_buffer = axi_adc_free_buffer, 571 .data_sample_trigger = axi_adc_data_sample_trigger, 572 .iodelay_set = axi_adc_iodelays_set, 573 .chan_status = axi_adc_chan_status, 574 .interface_type_get = axi_adc_interface_type_get, 575 .data_size_set = axi_adc_ad485x_data_size_set, 576 .oversampling_ratio_set = axi_adc_ad485x_oversampling_ratio_set, 577 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access), 578 .debugfs_print_chan_status = 579 iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), 580 }; 581 582 static const struct iio_backend_info axi_ad485x = { 583 .name = "axi-ad485x", 584 .ops = &adi_ad485x_ops, 585 }; 586 587 static int adi_axi_adc_probe(struct platform_device *pdev) 588 { 589 struct adi_axi_adc_state *st; 590 void __iomem *base; 591 unsigned int ver; 592 struct clk *clk; 593 int ret; 594 595 st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL); 596 if (!st) 597 return -ENOMEM; 598 599 base = devm_platform_ioremap_resource(pdev, 0); 600 if (IS_ERR(base)) 601 return PTR_ERR(base); 602 603 st->dev = &pdev->dev; 604 st->regmap = devm_regmap_init_mmio(&pdev->dev, base, 605 &axi_adc_regmap_config); 606 if (IS_ERR(st->regmap)) 607 return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap), 608 "failed to init register map\n"); 609 610 st->info = device_get_match_data(&pdev->dev); 611 if (!st->info) 612 return -ENODEV; 613 614 clk = devm_clk_get_enabled(&pdev->dev, NULL); 615 if (IS_ERR(clk)) 616 return dev_err_probe(&pdev->dev, PTR_ERR(clk), 617 "failed to get clock\n"); 618 619 /* 620 * Force disable the core. Up to the frontend to enable us. And we can 621 * still read/write registers... 622 */ 623 ret = regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0); 624 if (ret) 625 return ret; 626 627 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); 628 if (ret) 629 return ret; 630 631 if (ADI_AXI_PCORE_VER_MAJOR(ver) != 632 ADI_AXI_PCORE_VER_MAJOR(st->info->version)) { 633 dev_err(&pdev->dev, 634 "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", 635 ADI_AXI_PCORE_VER_MAJOR(st->info->version), 636 ADI_AXI_PCORE_VER_MINOR(st->info->version), 637 ADI_AXI_PCORE_VER_PATCH(st->info->version), 638 ADI_AXI_PCORE_VER_MAJOR(ver), 639 ADI_AXI_PCORE_VER_MINOR(ver), 640 ADI_AXI_PCORE_VER_PATCH(ver)); 641 return -ENODEV; 642 } 643 644 ret = devm_iio_backend_register(&pdev->dev, st->info->backend_info, st); 645 if (ret) 646 return dev_err_probe(&pdev->dev, ret, 647 "failed to register iio backend\n"); 648 649 device_for_each_child_node_scoped(&pdev->dev, child) { 650 int val; 651 652 if (!st->info->has_child_nodes) 653 return dev_err_probe(&pdev->dev, -EINVAL, 654 "invalid fdt axi-dac compatible."); 655 656 /* Processing only reg 0 node */ 657 ret = fwnode_property_read_u32(child, "reg", &val); 658 if (ret) 659 return dev_err_probe(&pdev->dev, ret, 660 "invalid reg property."); 661 if (val != 0) 662 return dev_err_probe(&pdev->dev, -EINVAL, 663 "invalid node address."); 664 665 ret = axi_adc_create_platform_device(st, child); 666 if (ret) 667 return dev_err_probe(&pdev->dev, -EINVAL, 668 "cannot create device."); 669 } 670 671 dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n", 672 ADI_AXI_PCORE_VER_MAJOR(ver), 673 ADI_AXI_PCORE_VER_MINOR(ver), 674 ADI_AXI_PCORE_VER_PATCH(ver)); 675 676 return 0; 677 } 678 679 static const struct axi_adc_info adc_generic = { 680 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 681 .backend_info = &adi_axi_adc_generic, 682 }; 683 684 static const struct axi_adc_info adi_axi_ad485x = { 685 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 686 .backend_info = &axi_ad485x, 687 }; 688 689 static const struct ad7606_platform_data ad7606_pdata = { 690 .bus_reg_read = ad7606_bus_reg_read, 691 .bus_reg_write = ad7606_bus_reg_write, 692 }; 693 694 static const struct axi_adc_info adc_ad7606 = { 695 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 696 .backend_info = &adi_axi_adc_generic, 697 .pdata = &ad7606_pdata, 698 .pdata_sz = sizeof(ad7606_pdata), 699 .has_child_nodes = true, 700 }; 701 702 /* Match table for of_platform binding */ 703 static const struct of_device_id adi_axi_adc_of_match[] = { 704 { .compatible = "adi,axi-adc-10.0.a", .data = &adc_generic }, 705 { .compatible = "adi,axi-ad485x", .data = &adi_axi_ad485x }, 706 { .compatible = "adi,axi-ad7606x", .data = &adc_ad7606 }, 707 { } 708 }; 709 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match); 710 711 static struct platform_driver adi_axi_adc_driver = { 712 .driver = { 713 .name = KBUILD_MODNAME, 714 .of_match_table = adi_axi_adc_of_match, 715 }, 716 .probe = adi_axi_adc_probe, 717 }; 718 module_platform_driver(adi_axi_adc_driver); 719 720 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 721 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver"); 722 MODULE_LICENSE("GPL v2"); 723 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 724 MODULE_IMPORT_NS("IIO_BACKEND"); 725