1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices Generic AXI ADC IP core 4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 5 * 6 * Copyright 2012-2020 Analog Devices Inc. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 20 #include <linux/iio/iio.h> 21 #include <linux/iio/sysfs.h> 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/buffer-dmaengine.h> 24 25 #include <linux/fpga/adi-axi-common.h> 26 #include <linux/iio/adc/adi-axi-adc.h> 27 28 /* 29 * Register definitions: 30 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map 31 */ 32 33 /* ADC controls */ 34 35 #define ADI_AXI_REG_RSTN 0x0040 36 #define ADI_AXI_REG_RSTN_CE_N BIT(2) 37 #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1) 38 #define ADI_AXI_REG_RSTN_RSTN BIT(0) 39 40 /* ADC Channel controls */ 41 42 #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40) 43 #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11) 44 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10) 45 #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9) 46 #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8) 47 #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6) 48 #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5) 49 #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4) 50 #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1) 51 #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0) 52 53 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \ 54 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \ 55 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ 56 ADI_AXI_REG_CHAN_CTRL_ENABLE) 57 58 struct adi_axi_adc_core_info { 59 unsigned int version; 60 }; 61 62 struct adi_axi_adc_state { 63 struct mutex lock; 64 65 struct adi_axi_adc_client *client; 66 struct regmap *regmap; 67 }; 68 69 struct adi_axi_adc_client { 70 struct list_head entry; 71 struct adi_axi_adc_conv conv; 72 struct adi_axi_adc_state *state; 73 struct device *dev; 74 const struct adi_axi_adc_core_info *info; 75 }; 76 77 static LIST_HEAD(registered_clients); 78 static DEFINE_MUTEX(registered_clients_lock); 79 80 static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv) 81 { 82 return container_of(conv, struct adi_axi_adc_client, conv); 83 } 84 85 void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv) 86 { 87 struct adi_axi_adc_client *cl = conv_to_client(conv); 88 89 return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), 90 IIO_DMA_MINALIGN); 91 } 92 EXPORT_SYMBOL_NS_GPL(adi_axi_adc_conv_priv, IIO_ADI_AXI); 93 94 static int adi_axi_adc_config_dma_buffer(struct device *dev, 95 struct iio_dev *indio_dev) 96 { 97 const char *dma_name; 98 99 if (!device_property_present(dev, "dmas")) 100 return 0; 101 102 if (device_property_read_string(dev, "dma-names", &dma_name)) 103 dma_name = "rx"; 104 105 return devm_iio_dmaengine_buffer_setup(indio_dev->dev.parent, 106 indio_dev, dma_name); 107 } 108 109 static int adi_axi_adc_read_raw(struct iio_dev *indio_dev, 110 struct iio_chan_spec const *chan, 111 int *val, int *val2, long mask) 112 { 113 struct adi_axi_adc_state *st = iio_priv(indio_dev); 114 struct adi_axi_adc_conv *conv = &st->client->conv; 115 116 if (!conv->read_raw) 117 return -EOPNOTSUPP; 118 119 return conv->read_raw(conv, chan, val, val2, mask); 120 } 121 122 static int adi_axi_adc_write_raw(struct iio_dev *indio_dev, 123 struct iio_chan_spec const *chan, 124 int val, int val2, long mask) 125 { 126 struct adi_axi_adc_state *st = iio_priv(indio_dev); 127 struct adi_axi_adc_conv *conv = &st->client->conv; 128 129 if (!conv->write_raw) 130 return -EOPNOTSUPP; 131 132 return conv->write_raw(conv, chan, val, val2, mask); 133 } 134 135 static int adi_axi_adc_read_avail(struct iio_dev *indio_dev, 136 struct iio_chan_spec const *chan, 137 const int **vals, int *type, int *length, 138 long mask) 139 { 140 struct adi_axi_adc_state *st = iio_priv(indio_dev); 141 struct adi_axi_adc_conv *conv = &st->client->conv; 142 143 if (!conv->read_avail) 144 return -EOPNOTSUPP; 145 146 return conv->read_avail(conv, chan, vals, type, length, mask); 147 } 148 149 static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev, 150 const unsigned long *scan_mask) 151 { 152 struct adi_axi_adc_state *st = iio_priv(indio_dev); 153 struct adi_axi_adc_conv *conv = &st->client->conv; 154 unsigned int i; 155 int ret; 156 157 for (i = 0; i < conv->chip_info->num_channels; i++) { 158 if (test_bit(i, scan_mask)) 159 ret = regmap_set_bits(st->regmap, 160 ADI_AXI_REG_CHAN_CTRL(i), 161 ADI_AXI_REG_CHAN_CTRL_ENABLE); 162 else 163 ret = regmap_clear_bits(st->regmap, 164 ADI_AXI_REG_CHAN_CTRL(i), 165 ADI_AXI_REG_CHAN_CTRL_ENABLE); 166 if (ret) 167 return ret; 168 } 169 170 return 0; 171 } 172 173 static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev, 174 size_t sizeof_priv) 175 { 176 struct adi_axi_adc_client *cl; 177 size_t alloc_size; 178 179 alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_DMA_MINALIGN); 180 if (sizeof_priv) 181 alloc_size += ALIGN(sizeof_priv, IIO_DMA_MINALIGN); 182 183 cl = kzalloc(alloc_size, GFP_KERNEL); 184 if (!cl) 185 return ERR_PTR(-ENOMEM); 186 187 mutex_lock(®istered_clients_lock); 188 189 cl->dev = get_device(dev); 190 191 list_add_tail(&cl->entry, ®istered_clients); 192 193 mutex_unlock(®istered_clients_lock); 194 195 return &cl->conv; 196 } 197 198 static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv) 199 { 200 struct adi_axi_adc_client *cl = conv_to_client(conv); 201 202 mutex_lock(®istered_clients_lock); 203 204 list_del(&cl->entry); 205 put_device(cl->dev); 206 207 mutex_unlock(®istered_clients_lock); 208 209 kfree(cl); 210 } 211 212 static void devm_adi_axi_adc_conv_release(void *conv) 213 { 214 adi_axi_adc_conv_unregister(conv); 215 } 216 217 struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev, 218 size_t sizeof_priv) 219 { 220 struct adi_axi_adc_conv *conv; 221 int ret; 222 223 conv = adi_axi_adc_conv_register(dev, sizeof_priv); 224 if (IS_ERR(conv)) 225 return conv; 226 227 ret = devm_add_action_or_reset(dev, devm_adi_axi_adc_conv_release, 228 conv); 229 if (ret) 230 return ERR_PTR(ret); 231 232 return conv; 233 } 234 EXPORT_SYMBOL_NS_GPL(devm_adi_axi_adc_conv_register, IIO_ADI_AXI); 235 236 static const struct iio_info adi_axi_adc_info = { 237 .read_raw = &adi_axi_adc_read_raw, 238 .write_raw = &adi_axi_adc_write_raw, 239 .update_scan_mode = &adi_axi_adc_update_scan_mode, 240 .read_avail = &adi_axi_adc_read_avail, 241 }; 242 243 static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = { 244 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 245 }; 246 247 static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev) 248 { 249 const struct adi_axi_adc_core_info *info; 250 struct adi_axi_adc_client *cl; 251 struct device_node *cln; 252 253 info = of_device_get_match_data(dev); 254 if (!info) 255 return ERR_PTR(-ENODEV); 256 257 cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0); 258 if (!cln) { 259 dev_err(dev, "No 'adi,adc-dev' node defined\n"); 260 return ERR_PTR(-ENODEV); 261 } 262 263 mutex_lock(®istered_clients_lock); 264 265 list_for_each_entry(cl, ®istered_clients, entry) { 266 if (!cl->dev) 267 continue; 268 269 if (cl->dev->of_node != cln) 270 continue; 271 272 if (!try_module_get(cl->dev->driver->owner)) { 273 mutex_unlock(®istered_clients_lock); 274 of_node_put(cln); 275 return ERR_PTR(-ENODEV); 276 } 277 278 get_device(cl->dev); 279 cl->info = info; 280 mutex_unlock(®istered_clients_lock); 281 of_node_put(cln); 282 return cl; 283 } 284 285 mutex_unlock(®istered_clients_lock); 286 of_node_put(cln); 287 288 return ERR_PTR(-EPROBE_DEFER); 289 } 290 291 static int adi_axi_adc_setup_channels(struct device *dev, 292 struct adi_axi_adc_state *st) 293 { 294 struct adi_axi_adc_conv *conv = &st->client->conv; 295 int i, ret; 296 297 if (conv->preenable_setup) { 298 ret = conv->preenable_setup(conv); 299 if (ret) 300 return ret; 301 } 302 303 for (i = 0; i < conv->chip_info->num_channels; i++) { 304 ret = regmap_write(st->regmap, ADI_AXI_REG_CHAN_CTRL(i), 305 ADI_AXI_REG_CHAN_CTRL_DEFAULTS); 306 if (ret) 307 return ret; 308 } 309 310 return 0; 311 } 312 313 static int axi_adc_reset(struct adi_axi_adc_state *st) 314 { 315 int ret; 316 317 ret = regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0); 318 if (ret) 319 return ret; 320 321 mdelay(10); 322 ret = regmap_write(st->regmap, ADI_AXI_REG_RSTN, 323 ADI_AXI_REG_RSTN_MMCM_RSTN); 324 if (ret) 325 return ret; 326 327 mdelay(10); 328 return regmap_write(st->regmap, ADI_AXI_REG_RSTN, 329 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN); 330 } 331 332 static void adi_axi_adc_cleanup(void *data) 333 { 334 struct adi_axi_adc_client *cl = data; 335 336 put_device(cl->dev); 337 module_put(cl->dev->driver->owner); 338 } 339 340 static const struct regmap_config axi_adc_regmap_config = { 341 .val_bits = 32, 342 .reg_bits = 32, 343 .reg_stride = 4, 344 .max_register = 0x0800, 345 }; 346 347 static int adi_axi_adc_probe(struct platform_device *pdev) 348 { 349 struct adi_axi_adc_conv *conv; 350 struct iio_dev *indio_dev; 351 struct adi_axi_adc_client *cl; 352 struct adi_axi_adc_state *st; 353 void __iomem *base; 354 unsigned int ver; 355 int ret; 356 357 cl = adi_axi_adc_attach_client(&pdev->dev); 358 if (IS_ERR(cl)) 359 return PTR_ERR(cl); 360 361 ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl); 362 if (ret) 363 return ret; 364 365 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 366 if (indio_dev == NULL) 367 return -ENOMEM; 368 369 st = iio_priv(indio_dev); 370 st->client = cl; 371 cl->state = st; 372 mutex_init(&st->lock); 373 374 base = devm_platform_ioremap_resource(pdev, 0); 375 if (IS_ERR(base)) 376 return PTR_ERR(base); 377 378 st->regmap = devm_regmap_init_mmio(&pdev->dev, base, 379 &axi_adc_regmap_config); 380 if (IS_ERR(st->regmap)) 381 return PTR_ERR(st->regmap); 382 383 conv = &st->client->conv; 384 385 ret = axi_adc_reset(st); 386 if (ret) 387 return ret; 388 389 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); 390 if (ret) 391 return ret; 392 393 if (cl->info->version > ver) { 394 dev_err(&pdev->dev, 395 "IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", 396 ADI_AXI_PCORE_VER_MAJOR(cl->info->version), 397 ADI_AXI_PCORE_VER_MINOR(cl->info->version), 398 ADI_AXI_PCORE_VER_PATCH(cl->info->version), 399 ADI_AXI_PCORE_VER_MAJOR(ver), 400 ADI_AXI_PCORE_VER_MINOR(ver), 401 ADI_AXI_PCORE_VER_PATCH(ver)); 402 return -ENODEV; 403 } 404 405 indio_dev->info = &adi_axi_adc_info; 406 indio_dev->name = "adi-axi-adc"; 407 indio_dev->modes = INDIO_DIRECT_MODE; 408 indio_dev->num_channels = conv->chip_info->num_channels; 409 indio_dev->channels = conv->chip_info->channels; 410 411 ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev); 412 if (ret) 413 return ret; 414 415 ret = adi_axi_adc_setup_channels(&pdev->dev, st); 416 if (ret) 417 return ret; 418 419 ret = devm_iio_device_register(&pdev->dev, indio_dev); 420 if (ret) 421 return ret; 422 423 dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n", 424 ADI_AXI_PCORE_VER_MAJOR(ver), 425 ADI_AXI_PCORE_VER_MINOR(ver), 426 ADI_AXI_PCORE_VER_PATCH(ver)); 427 428 return 0; 429 } 430 431 /* Match table for of_platform binding */ 432 static const struct of_device_id adi_axi_adc_of_match[] = { 433 { .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info }, 434 { /* end of list */ } 435 }; 436 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match); 437 438 static struct platform_driver adi_axi_adc_driver = { 439 .driver = { 440 .name = KBUILD_MODNAME, 441 .of_match_table = adi_axi_adc_of_match, 442 }, 443 .probe = adi_axi_adc_probe, 444 }; 445 module_platform_driver(adi_axi_adc_driver); 446 447 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 448 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver"); 449 MODULE_LICENSE("GPL v2"); 450