1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices Generic AXI ADC IP core 4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 5 * 6 * Copyright 2012-2020 Analog Devices Inc. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 23 #include <linux/fpga/adi-axi-common.h> 24 25 #include <linux/iio/backend.h> 26 #include <linux/iio/buffer-dmaengine.h> 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/iio.h> 29 30 /* 31 * Register definitions: 32 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map 33 */ 34 35 /* ADC controls */ 36 37 #define ADI_AXI_REG_RSTN 0x0040 38 #define ADI_AXI_REG_RSTN_CE_N BIT(2) 39 #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1) 40 #define ADI_AXI_REG_RSTN_RSTN BIT(0) 41 42 #define ADI_AXI_ADC_REG_CTRL 0x0044 43 #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) 44 45 /* ADC Channel controls */ 46 47 #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40) 48 #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11) 49 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10) 50 #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9) 51 #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8) 52 #define ADI_AXI_REG_CHAN_CTRL_FMT_MASK GENMASK(6, 4) 53 #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6) 54 #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5) 55 #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4) 56 #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1) 57 #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0) 58 59 #define ADI_AXI_ADC_REG_CHAN_STATUS(c) (0x0404 + (c) * 0x40) 60 #define ADI_AXI_ADC_CHAN_STAT_PN_MASK GENMASK(2, 1) 61 62 #define ADI_AXI_ADC_REG_CHAN_CTRL_3(c) (0x0418 + (c) * 0x40) 63 #define ADI_AXI_ADC_CHAN_PN_SEL_MASK GENMASK(19, 16) 64 65 /* IO Delays */ 66 #define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4) 67 #define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0) 68 69 #define ADI_AXI_ADC_MAX_IO_NUM_LANES 15 70 71 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \ 72 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \ 73 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ 74 ADI_AXI_REG_CHAN_CTRL_ENABLE) 75 76 struct adi_axi_adc_state { 77 struct regmap *regmap; 78 struct device *dev; 79 /* lock to protect multiple accesses to the device registers */ 80 struct mutex lock; 81 }; 82 83 static int axi_adc_enable(struct iio_backend *back) 84 { 85 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 86 int ret; 87 88 ret = regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, 89 ADI_AXI_REG_RSTN_MMCM_RSTN); 90 if (ret) 91 return ret; 92 93 fsleep(10000); 94 return regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, 95 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN); 96 } 97 98 static void axi_adc_disable(struct iio_backend *back) 99 { 100 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 101 102 regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0); 103 } 104 105 static int axi_adc_data_format_set(struct iio_backend *back, unsigned int chan, 106 const struct iio_backend_data_fmt *data) 107 { 108 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 109 u32 val; 110 111 if (!data->enable) 112 return regmap_clear_bits(st->regmap, 113 ADI_AXI_REG_CHAN_CTRL(chan), 114 ADI_AXI_REG_CHAN_CTRL_FMT_EN); 115 116 val = FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_EN, true); 117 if (data->sign_extend) 118 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT, true); 119 if (data->type == IIO_BACKEND_OFFSET_BINARY) 120 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_TYPE, true); 121 122 return regmap_update_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 123 ADI_AXI_REG_CHAN_CTRL_FMT_MASK, val); 124 } 125 126 static int axi_adc_data_sample_trigger(struct iio_backend *back, 127 enum iio_backend_sample_trigger trigger) 128 { 129 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 130 131 switch (trigger) { 132 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING: 133 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 134 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK); 135 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING: 136 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 137 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK); 138 default: 139 return -EINVAL; 140 } 141 } 142 143 static int axi_adc_iodelays_set(struct iio_backend *back, unsigned int lane, 144 unsigned int tap) 145 { 146 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 147 int ret; 148 u32 val; 149 150 if (tap > FIELD_MAX(AXI_ADC_DELAY_CTRL_MASK)) 151 return -EINVAL; 152 if (lane > ADI_AXI_ADC_MAX_IO_NUM_LANES) 153 return -EINVAL; 154 155 guard(mutex)(&st->lock); 156 ret = regmap_write(st->regmap, ADI_AXI_ADC_REG_DELAY(lane), tap); 157 if (ret) 158 return ret; 159 /* 160 * If readback is ~0, that means there are issues with the 161 * delay_clk. 162 */ 163 ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_DELAY(lane), &val); 164 if (ret) 165 return ret; 166 if (val == U32_MAX) 167 return -EIO; 168 169 return 0; 170 } 171 172 static int axi_adc_test_pattern_set(struct iio_backend *back, 173 unsigned int chan, 174 enum iio_backend_test_pattern pattern) 175 { 176 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 177 178 switch (pattern) { 179 case IIO_BACKEND_NO_TEST_PATTERN: 180 /* nothing to do */ 181 return 0; 182 case IIO_BACKEND_ADI_PRBS_9A: 183 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CHAN_CTRL_3(chan), 184 ADI_AXI_ADC_CHAN_PN_SEL_MASK, 185 FIELD_PREP(ADI_AXI_ADC_CHAN_PN_SEL_MASK, 0)); 186 default: 187 return -EINVAL; 188 } 189 } 190 191 static int axi_adc_chan_status(struct iio_backend *back, unsigned int chan, 192 bool *error) 193 { 194 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 195 int ret; 196 u32 val; 197 198 guard(mutex)(&st->lock); 199 /* reset test bits by setting them */ 200 ret = regmap_write(st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan), 201 ADI_AXI_ADC_CHAN_STAT_PN_MASK); 202 if (ret) 203 return ret; 204 205 /* let's give enough time to validate or erroring the incoming pattern */ 206 fsleep(1000); 207 208 ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan), &val); 209 if (ret) 210 return ret; 211 212 if (ADI_AXI_ADC_CHAN_STAT_PN_MASK & val) 213 *error = true; 214 else 215 *error = false; 216 217 return 0; 218 } 219 220 static int axi_adc_chan_enable(struct iio_backend *back, unsigned int chan) 221 { 222 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 223 224 return regmap_set_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 225 ADI_AXI_REG_CHAN_CTRL_ENABLE); 226 } 227 228 static int axi_adc_chan_disable(struct iio_backend *back, unsigned int chan) 229 { 230 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 231 232 return regmap_clear_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 233 ADI_AXI_REG_CHAN_CTRL_ENABLE); 234 } 235 236 static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, 237 struct iio_dev *indio_dev) 238 { 239 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 240 const char *dma_name; 241 242 if (device_property_read_string(st->dev, "dma-names", &dma_name)) 243 dma_name = "rx"; 244 245 return iio_dmaengine_buffer_setup(st->dev, indio_dev, dma_name); 246 } 247 248 static void axi_adc_free_buffer(struct iio_backend *back, 249 struct iio_buffer *buffer) 250 { 251 iio_dmaengine_buffer_free(buffer); 252 } 253 254 static const struct regmap_config axi_adc_regmap_config = { 255 .val_bits = 32, 256 .reg_bits = 32, 257 .reg_stride = 4, 258 }; 259 260 static const struct iio_backend_ops adi_axi_adc_generic = { 261 .enable = axi_adc_enable, 262 .disable = axi_adc_disable, 263 .data_format_set = axi_adc_data_format_set, 264 .chan_enable = axi_adc_chan_enable, 265 .chan_disable = axi_adc_chan_disable, 266 .request_buffer = axi_adc_request_buffer, 267 .free_buffer = axi_adc_free_buffer, 268 .data_sample_trigger = axi_adc_data_sample_trigger, 269 .iodelay_set = axi_adc_iodelays_set, 270 .test_pattern_set = axi_adc_test_pattern_set, 271 .chan_status = axi_adc_chan_status, 272 }; 273 274 static int adi_axi_adc_probe(struct platform_device *pdev) 275 { 276 const unsigned int *expected_ver; 277 struct adi_axi_adc_state *st; 278 void __iomem *base; 279 unsigned int ver; 280 struct clk *clk; 281 int ret; 282 283 st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL); 284 if (!st) 285 return -ENOMEM; 286 287 base = devm_platform_ioremap_resource(pdev, 0); 288 if (IS_ERR(base)) 289 return PTR_ERR(base); 290 291 st->dev = &pdev->dev; 292 st->regmap = devm_regmap_init_mmio(&pdev->dev, base, 293 &axi_adc_regmap_config); 294 if (IS_ERR(st->regmap)) 295 return PTR_ERR(st->regmap); 296 297 expected_ver = device_get_match_data(&pdev->dev); 298 if (!expected_ver) 299 return -ENODEV; 300 301 clk = devm_clk_get_enabled(&pdev->dev, NULL); 302 if (IS_ERR(clk)) 303 return PTR_ERR(clk); 304 305 /* 306 * Force disable the core. Up to the frontend to enable us. And we can 307 * still read/write registers... 308 */ 309 ret = regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0); 310 if (ret) 311 return ret; 312 313 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); 314 if (ret) 315 return ret; 316 317 if (ADI_AXI_PCORE_VER_MAJOR(ver) != ADI_AXI_PCORE_VER_MAJOR(*expected_ver)) { 318 dev_err(&pdev->dev, 319 "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", 320 ADI_AXI_PCORE_VER_MAJOR(*expected_ver), 321 ADI_AXI_PCORE_VER_MINOR(*expected_ver), 322 ADI_AXI_PCORE_VER_PATCH(*expected_ver), 323 ADI_AXI_PCORE_VER_MAJOR(ver), 324 ADI_AXI_PCORE_VER_MINOR(ver), 325 ADI_AXI_PCORE_VER_PATCH(ver)); 326 return -ENODEV; 327 } 328 329 ret = devm_iio_backend_register(&pdev->dev, &adi_axi_adc_generic, st); 330 if (ret) 331 return ret; 332 333 dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n", 334 ADI_AXI_PCORE_VER_MAJOR(ver), 335 ADI_AXI_PCORE_VER_MINOR(ver), 336 ADI_AXI_PCORE_VER_PATCH(ver)); 337 338 return 0; 339 } 340 341 static unsigned int adi_axi_adc_10_0_a_info = ADI_AXI_PCORE_VER(10, 0, 'a'); 342 343 /* Match table for of_platform binding */ 344 static const struct of_device_id adi_axi_adc_of_match[] = { 345 { .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info }, 346 { /* end of list */ } 347 }; 348 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match); 349 350 static struct platform_driver adi_axi_adc_driver = { 351 .driver = { 352 .name = KBUILD_MODNAME, 353 .of_match_table = adi_axi_adc_of_match, 354 }, 355 .probe = adi_axi_adc_probe, 356 }; 357 module_platform_driver(adi_axi_adc_driver); 358 359 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 360 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver"); 361 MODULE_LICENSE("GPL v2"); 362 MODULE_IMPORT_NS(IIO_DMAENGINE_BUFFER); 363 MODULE_IMPORT_NS(IIO_BACKEND); 364