1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices Generic AXI ADC IP core 4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 5 * 6 * Copyright 2012-2020 Analog Devices Inc. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/delay.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 23 #include <linux/fpga/adi-axi-common.h> 24 25 #include <linux/iio/backend.h> 26 #include <linux/iio/buffer-dmaengine.h> 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/iio.h> 29 30 #include "ad7606_bus_iface.h" 31 /* 32 * Register definitions: 33 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map 34 */ 35 36 /* ADC controls */ 37 38 #define ADI_AXI_REG_RSTN 0x0040 39 #define ADI_AXI_REG_RSTN_CE_N BIT(2) 40 #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1) 41 #define ADI_AXI_REG_RSTN_RSTN BIT(0) 42 43 #define ADI_AXI_ADC_REG_CONFIG 0x000c 44 #define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) 45 46 #define ADI_AXI_ADC_REG_CTRL 0x0044 47 #define ADI_AXI_ADC_CTRL_NUM_LANES_MSK GENMASK(12, 8) 48 #define ADI_AXI_ADC_CTRL_SYNC_MSK BIT(3) 49 #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) 50 51 #define ADI_AXI_ADC_REG_CNTRL_3 0x004c 52 #define AXI_AD485X_CNTRL_3_OS_EN_MSK BIT(2) 53 #define AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK GENMASK(1, 0) 54 #define AXI_AD485X_PACKET_FORMAT_20BIT 0x0 55 #define AXI_AD485X_PACKET_FORMAT_24BIT 0x1 56 #define AXI_AD485X_PACKET_FORMAT_32BIT 0x2 57 #define AXI_AD408X_CNTRL_3_FILTER_EN_MSK BIT(0) 58 59 #define ADI_AXI_ADC_REG_SYNC_STATUS 0x0068 60 #define ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK BIT(0) 61 62 #define ADI_AXI_ADC_REG_DRP_STATUS 0x0074 63 #define ADI_AXI_ADC_DRP_LOCKED BIT(17) 64 65 /* ADC Channel controls */ 66 67 #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40) 68 #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11) 69 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10) 70 #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9) 71 #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8) 72 #define ADI_AXI_REG_CHAN_CTRL_FMT_MASK GENMASK(6, 4) 73 #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6) 74 #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5) 75 #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4) 76 #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1) 77 #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0) 78 79 #define ADI_AXI_ADC_REG_CHAN_STATUS(c) (0x0404 + (c) * 0x40) 80 #define ADI_AXI_ADC_CHAN_STAT_PN_MASK GENMASK(2, 1) 81 /* out of sync */ 82 #define ADI_AXI_ADC_CHAN_STAT_PN_OOS BIT(1) 83 /* spurious out of sync */ 84 #define ADI_AXI_ADC_CHAN_STAT_PN_ERR BIT(2) 85 86 #define ADI_AXI_ADC_REG_CHAN_CTRL_3(c) (0x0418 + (c) * 0x40) 87 #define ADI_AXI_ADC_CHAN_PN_SEL_MASK GENMASK(19, 16) 88 89 #define ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(c) (0x0424 + (c) * 0x40) 90 #define ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK GENMASK(15, 0) 91 92 /* IO Delays */ 93 #define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4) 94 #define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0) 95 96 #define ADI_AXI_REG_CONFIG_WR 0x0080 97 #define ADI_AXI_REG_CONFIG_RD 0x0084 98 #define ADI_AXI_REG_CONFIG_CTRL 0x008c 99 #define ADI_AXI_REG_CONFIG_CTRL_READ 0x03 100 #define ADI_AXI_REG_CONFIG_CTRL_WRITE 0x01 101 102 #define ADI_AXI_ADC_MAX_IO_NUM_LANES 15 103 104 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \ 105 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \ 106 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ 107 ADI_AXI_REG_CHAN_CTRL_ENABLE) 108 109 #define ADI_AXI_REG_READ_BIT 0x8000 110 #define ADI_AXI_REG_ADDRESS_MASK 0xff00 111 #define ADI_AXI_REG_VALUE_MASK 0x00ff 112 113 struct axi_adc_info { 114 unsigned int version; 115 const struct iio_backend_info *backend_info; 116 bool has_child_nodes; 117 const void *pdata; 118 unsigned int pdata_sz; 119 }; 120 121 struct adi_axi_adc_state { 122 const struct axi_adc_info *info; 123 struct regmap *regmap; 124 struct device *dev; 125 /* lock to protect multiple accesses to the device registers */ 126 struct mutex lock; 127 }; 128 129 static int axi_adc_enable(struct iio_backend *back) 130 { 131 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 132 unsigned int __val; 133 int ret; 134 135 guard(mutex)(&st->lock); 136 ret = regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, 137 ADI_AXI_REG_RSTN_MMCM_RSTN); 138 if (ret) 139 return ret; 140 141 /* 142 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all 143 * designs really use it but if they don't we still get the lock bit 144 * set. So let's do it all the time so the code is generic. 145 */ 146 ret = regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_DRP_STATUS, 147 __val, __val & ADI_AXI_ADC_DRP_LOCKED, 148 100, 1000); 149 if (ret) 150 return ret; 151 152 return regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, 153 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN); 154 } 155 156 static void axi_adc_disable(struct iio_backend *back) 157 { 158 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 159 160 guard(mutex)(&st->lock); 161 regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0); 162 } 163 164 static int axi_adc_data_format_set(struct iio_backend *back, unsigned int chan, 165 const struct iio_backend_data_fmt *data) 166 { 167 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 168 u32 val; 169 170 if (!data->enable) 171 return regmap_clear_bits(st->regmap, 172 ADI_AXI_REG_CHAN_CTRL(chan), 173 ADI_AXI_REG_CHAN_CTRL_FMT_EN); 174 175 val = FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_EN, true); 176 if (data->sign_extend) 177 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT, true); 178 if (data->type == IIO_BACKEND_OFFSET_BINARY) 179 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_TYPE, true); 180 181 return regmap_update_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 182 ADI_AXI_REG_CHAN_CTRL_FMT_MASK, val); 183 } 184 185 static int axi_adc_data_sample_trigger(struct iio_backend *back, 186 enum iio_backend_sample_trigger trigger) 187 { 188 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 189 190 switch (trigger) { 191 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING: 192 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 193 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK); 194 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING: 195 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 196 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK); 197 default: 198 return -EINVAL; 199 } 200 } 201 202 static int axi_adc_iodelays_set(struct iio_backend *back, unsigned int lane, 203 unsigned int tap) 204 { 205 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 206 int ret; 207 u32 val; 208 209 if (tap > FIELD_MAX(AXI_ADC_DELAY_CTRL_MASK)) 210 return -EINVAL; 211 if (lane > ADI_AXI_ADC_MAX_IO_NUM_LANES) 212 return -EINVAL; 213 214 guard(mutex)(&st->lock); 215 ret = regmap_write(st->regmap, ADI_AXI_ADC_REG_DELAY(lane), tap); 216 if (ret) 217 return ret; 218 /* 219 * If readback is ~0, that means there are issues with the 220 * delay_clk. 221 */ 222 ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_DELAY(lane), &val); 223 if (ret) 224 return ret; 225 if (val == U32_MAX) 226 return -EIO; 227 228 return 0; 229 } 230 231 static int axi_adc_test_pattern_set(struct iio_backend *back, 232 unsigned int chan, 233 enum iio_backend_test_pattern pattern) 234 { 235 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 236 237 switch (pattern) { 238 case IIO_BACKEND_NO_TEST_PATTERN: 239 /* nothing to do */ 240 return 0; 241 case IIO_BACKEND_ADI_PRBS_9A: 242 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CHAN_CTRL_3(chan), 243 ADI_AXI_ADC_CHAN_PN_SEL_MASK, 244 FIELD_PREP(ADI_AXI_ADC_CHAN_PN_SEL_MASK, 0)); 245 case IIO_BACKEND_ADI_PRBS_23A: 246 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CHAN_CTRL_3(chan), 247 ADI_AXI_ADC_CHAN_PN_SEL_MASK, 248 FIELD_PREP(ADI_AXI_ADC_CHAN_PN_SEL_MASK, 1)); 249 default: 250 return -EINVAL; 251 } 252 } 253 254 static int axi_adc_oversampling_ratio_set(struct iio_backend *back, 255 unsigned int chan, 256 unsigned int rate) 257 { 258 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 259 260 return regmap_update_bits(st->regmap, 261 ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(chan), 262 ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK, 263 FIELD_PREP(ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK, 264 rate)); 265 } 266 267 static int axi_adc_read_chan_status(struct adi_axi_adc_state *st, unsigned int chan, 268 unsigned int *status) 269 { 270 int ret; 271 272 guard(mutex)(&st->lock); 273 /* reset test bits by setting them */ 274 ret = regmap_write(st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan), 275 ADI_AXI_ADC_CHAN_STAT_PN_MASK); 276 if (ret) 277 return ret; 278 279 /* let's give enough time to validate or erroring the incoming pattern */ 280 fsleep(1000); 281 282 return regmap_read(st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan), 283 status); 284 } 285 286 static int axi_adc_chan_status(struct iio_backend *back, unsigned int chan, 287 bool *error) 288 { 289 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 290 u32 val; 291 int ret; 292 293 ret = axi_adc_read_chan_status(st, chan, &val); 294 if (ret) 295 return ret; 296 297 if (ADI_AXI_ADC_CHAN_STAT_PN_MASK & val) 298 *error = true; 299 else 300 *error = false; 301 302 return 0; 303 } 304 305 static int axi_adc_debugfs_print_chan_status(struct iio_backend *back, 306 unsigned int chan, char *buf, 307 size_t len) 308 { 309 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 310 u32 val; 311 int ret; 312 313 ret = axi_adc_read_chan_status(st, chan, &val); 314 if (ret) 315 return ret; 316 317 /* 318 * PN_ERR is cleared in case out of sync is set. Hence, no point in 319 * checking both bits. 320 */ 321 if (val & ADI_AXI_ADC_CHAN_STAT_PN_OOS) 322 return scnprintf(buf, len, "CH%u: Out of Sync.\n", chan); 323 if (val & ADI_AXI_ADC_CHAN_STAT_PN_ERR) 324 return scnprintf(buf, len, "CH%u: Spurious Out of Sync.\n", chan); 325 326 return scnprintf(buf, len, "CH%u: OK.\n", chan); 327 } 328 329 static int axi_adc_chan_enable(struct iio_backend *back, unsigned int chan) 330 { 331 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 332 333 return regmap_set_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 334 ADI_AXI_REG_CHAN_CTRL_ENABLE); 335 } 336 337 static int axi_adc_chan_disable(struct iio_backend *back, unsigned int chan) 338 { 339 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 340 341 return regmap_clear_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 342 ADI_AXI_REG_CHAN_CTRL_ENABLE); 343 } 344 345 static int axi_adc_interface_type_get(struct iio_backend *back, 346 enum iio_backend_interface_type *type) 347 { 348 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 349 unsigned int val; 350 int ret; 351 352 ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_CONFIG, &val); 353 if (ret) 354 return ret; 355 356 if (val & ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N) 357 *type = IIO_BACKEND_INTERFACE_SERIAL_CMOS; 358 else 359 *type = IIO_BACKEND_INTERFACE_SERIAL_LVDS; 360 361 return 0; 362 } 363 364 static int axi_adc_ad485x_data_size_set(struct iio_backend *back, 365 unsigned int size) 366 { 367 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 368 unsigned int val; 369 370 switch (size) { 371 /* 372 * There are two different variants of the AXI AXI_AD485X IP block, a 373 * 16-bit and a 20-bit variant. 374 * The 0x0 value (AXI_AD485X_PACKET_FORMAT_20BIT) is corresponding also 375 * to the 16-bit variant of the IP block. 376 */ 377 case 16: 378 case 20: 379 val = AXI_AD485X_PACKET_FORMAT_20BIT; 380 break; 381 case 24: 382 val = AXI_AD485X_PACKET_FORMAT_24BIT; 383 break; 384 /* 385 * The 0x2 (AXI_AD485X_PACKET_FORMAT_32BIT) corresponds only to the 386 * 20-bit variant of the IP block. Setting this value properly is 387 * ensured by the upper layers of the drivers calling the axi-adc 388 * functions. 389 * Also, for 16-bit IP block, the 0x2 (AXI_AD485X_PACKET_FORMAT_32BIT) 390 * value is handled as maximum size available which is 24-bit for this 391 * configuration. 392 */ 393 case 32: 394 val = AXI_AD485X_PACKET_FORMAT_32BIT; 395 break; 396 default: 397 return -EINVAL; 398 } 399 400 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 401 AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK, 402 FIELD_PREP(AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK, val)); 403 } 404 405 static int axi_adc_ad485x_oversampling_ratio_set(struct iio_backend *back, 406 unsigned int chan, 407 unsigned int ratio) 408 { 409 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 410 411 /* The current state of the function enables or disables the 412 * oversampling in REG_CNTRL_3 register. A ratio equal to 1 implies no 413 * oversampling, while a value greater than 1 implies oversampling being 414 * enabled. 415 */ 416 switch (ratio) { 417 case 0: 418 return -EINVAL; 419 case 1: 420 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 421 AXI_AD485X_CNTRL_3_OS_EN_MSK); 422 default: 423 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 424 AXI_AD485X_CNTRL_3_OS_EN_MSK); 425 } 426 } 427 428 static int axi_adc_ad408x_filter_type_set(struct iio_backend *back, 429 enum iio_backend_filter_type type) 430 { 431 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 432 433 if (type) 434 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 435 AXI_AD408X_CNTRL_3_FILTER_EN_MSK); 436 437 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 438 AXI_AD408X_CNTRL_3_FILTER_EN_MSK); 439 } 440 441 static int axi_adc_ad408x_interface_data_align(struct iio_backend *back, 442 u32 timeout_us) 443 { 444 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 445 u32 val; 446 int ret; 447 448 ret = regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 449 ADI_AXI_ADC_CTRL_SYNC_MSK); 450 if (ret) 451 return ret; 452 453 return regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_SYNC_STATUS, 454 val, 455 FIELD_GET(ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK, val), 456 1, timeout_us); 457 } 458 459 static int axi_adc_num_lanes_set(struct iio_backend *back, 460 unsigned int num_lanes) 461 { 462 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 463 464 if (!num_lanes) 465 return -EINVAL; 466 467 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 468 ADI_AXI_ADC_CTRL_NUM_LANES_MSK, 469 FIELD_PREP(ADI_AXI_ADC_CTRL_NUM_LANES_MSK, num_lanes)); 470 } 471 472 static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, 473 struct iio_dev *indio_dev) 474 { 475 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 476 const char *dma_name; 477 478 if (device_property_read_string(st->dev, "dma-names", &dma_name)) 479 dma_name = "rx"; 480 481 return iio_dmaengine_buffer_setup(st->dev, indio_dev, dma_name); 482 } 483 484 static int axi_adc_raw_write(struct iio_backend *back, u32 val) 485 { 486 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 487 488 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_WR, val); 489 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 490 ADI_AXI_REG_CONFIG_CTRL_WRITE); 491 fsleep(100); 492 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); 493 fsleep(100); 494 495 return 0; 496 } 497 498 static int axi_adc_raw_read(struct iio_backend *back, u32 *val) 499 { 500 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 501 502 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 503 ADI_AXI_REG_CONFIG_CTRL_READ); 504 fsleep(100); 505 regmap_read(st->regmap, ADI_AXI_REG_CONFIG_RD, val); 506 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); 507 fsleep(100); 508 509 return 0; 510 } 511 512 static int ad7606_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val) 513 { 514 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 515 u32 addr, reg_val; 516 517 guard(mutex)(&st->lock); 518 519 /* 520 * The address is written on the highest weight byte, and the MSB set 521 * at 1 indicates a read operation. 522 */ 523 addr = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | ADI_AXI_REG_READ_BIT; 524 axi_adc_raw_write(back, addr); 525 axi_adc_raw_read(back, ®_val); 526 527 *val = FIELD_GET(ADI_AXI_REG_VALUE_MASK, reg_val); 528 529 /* Write 0x0 on the bus to get back to ADC mode */ 530 axi_adc_raw_write(back, 0); 531 532 return 0; 533 } 534 535 static int ad7606_bus_reg_write(struct iio_backend *back, u32 reg, u32 val) 536 { 537 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 538 u32 buf; 539 540 guard(mutex)(&st->lock); 541 542 /* Write any register to switch to register mode */ 543 axi_adc_raw_write(back, 0xaf00); 544 545 buf = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | 546 FIELD_PREP(ADI_AXI_REG_VALUE_MASK, val); 547 axi_adc_raw_write(back, buf); 548 549 /* Write 0x0 on the bus to get back to ADC mode */ 550 axi_adc_raw_write(back, 0); 551 552 return 0; 553 } 554 555 static void axi_adc_free_buffer(struct iio_backend *back, 556 struct iio_buffer *buffer) 557 { 558 iio_dmaengine_buffer_teardown(buffer); 559 } 560 561 static int axi_adc_reg_access(struct iio_backend *back, unsigned int reg, 562 unsigned int writeval, unsigned int *readval) 563 { 564 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 565 566 if (readval) 567 return regmap_read(st->regmap, reg, readval); 568 569 return regmap_write(st->regmap, reg, writeval); 570 } 571 572 static const struct regmap_config axi_adc_regmap_config = { 573 .val_bits = 32, 574 .reg_bits = 32, 575 .reg_stride = 4, 576 }; 577 578 static void axi_adc_child_remove(void *data) 579 { 580 platform_device_unregister(data); 581 } 582 583 static int axi_adc_create_platform_device(struct adi_axi_adc_state *st, 584 struct fwnode_handle *child) 585 { 586 struct platform_device_info pi = { 587 .parent = st->dev, 588 .name = fwnode_get_name(child), 589 .id = PLATFORM_DEVID_AUTO, 590 .fwnode = child, 591 .data = st->info->pdata, 592 .size_data = st->info->pdata_sz, 593 }; 594 struct platform_device *pdev; 595 int ret; 596 597 pdev = platform_device_register_full(&pi); 598 if (IS_ERR(pdev)) 599 return PTR_ERR(pdev); 600 601 ret = devm_add_action_or_reset(st->dev, axi_adc_child_remove, pdev); 602 if (ret) 603 return ret; 604 605 return 0; 606 } 607 608 static const struct iio_backend_ops adi_axi_adc_ops = { 609 .enable = axi_adc_enable, 610 .disable = axi_adc_disable, 611 .data_format_set = axi_adc_data_format_set, 612 .chan_enable = axi_adc_chan_enable, 613 .chan_disable = axi_adc_chan_disable, 614 .request_buffer = axi_adc_request_buffer, 615 .free_buffer = axi_adc_free_buffer, 616 .data_sample_trigger = axi_adc_data_sample_trigger, 617 .iodelay_set = axi_adc_iodelays_set, 618 .test_pattern_set = axi_adc_test_pattern_set, 619 .chan_status = axi_adc_chan_status, 620 .interface_type_get = axi_adc_interface_type_get, 621 .oversampling_ratio_set = axi_adc_oversampling_ratio_set, 622 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access), 623 .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), 624 }; 625 626 static const struct iio_backend_info adi_axi_adc_generic = { 627 .name = "axi-adc", 628 .ops = &adi_axi_adc_ops, 629 }; 630 631 static const struct iio_backend_ops adi_ad485x_ops = { 632 .enable = axi_adc_enable, 633 .disable = axi_adc_disable, 634 .data_format_set = axi_adc_data_format_set, 635 .chan_enable = axi_adc_chan_enable, 636 .chan_disable = axi_adc_chan_disable, 637 .request_buffer = axi_adc_request_buffer, 638 .free_buffer = axi_adc_free_buffer, 639 .data_sample_trigger = axi_adc_data_sample_trigger, 640 .iodelay_set = axi_adc_iodelays_set, 641 .chan_status = axi_adc_chan_status, 642 .interface_type_get = axi_adc_interface_type_get, 643 .data_size_set = axi_adc_ad485x_data_size_set, 644 .oversampling_ratio_set = axi_adc_ad485x_oversampling_ratio_set, 645 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access), 646 .debugfs_print_chan_status = 647 iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), 648 }; 649 650 static const struct iio_backend_info axi_ad485x = { 651 .name = "axi-ad485x", 652 .ops = &adi_ad485x_ops, 653 }; 654 655 static const struct iio_backend_ops adi_ad408x_ops = { 656 .enable = axi_adc_enable, 657 .disable = axi_adc_disable, 658 .chan_enable = axi_adc_chan_enable, 659 .chan_disable = axi_adc_chan_disable, 660 .request_buffer = axi_adc_request_buffer, 661 .free_buffer = axi_adc_free_buffer, 662 .data_sample_trigger = axi_adc_data_sample_trigger, 663 .filter_type_set = axi_adc_ad408x_filter_type_set, 664 .interface_data_align = axi_adc_ad408x_interface_data_align, 665 .num_lanes_set = axi_adc_num_lanes_set, 666 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access), 667 .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), 668 }; 669 670 static const struct iio_backend_info axi_ad408x = { 671 .name = "axi-ad408x", 672 .ops = &adi_ad408x_ops, 673 }; 674 675 static int adi_axi_adc_probe(struct platform_device *pdev) 676 { 677 struct adi_axi_adc_state *st; 678 void __iomem *base; 679 unsigned int ver; 680 struct clk *clk; 681 int ret; 682 683 st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL); 684 if (!st) 685 return -ENOMEM; 686 687 base = devm_platform_ioremap_resource(pdev, 0); 688 if (IS_ERR(base)) 689 return PTR_ERR(base); 690 691 st->dev = &pdev->dev; 692 st->regmap = devm_regmap_init_mmio(&pdev->dev, base, 693 &axi_adc_regmap_config); 694 if (IS_ERR(st->regmap)) 695 return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap), 696 "failed to init register map\n"); 697 698 st->info = device_get_match_data(&pdev->dev); 699 if (!st->info) 700 return -ENODEV; 701 702 clk = devm_clk_get_enabled(&pdev->dev, NULL); 703 if (IS_ERR(clk)) 704 return dev_err_probe(&pdev->dev, PTR_ERR(clk), 705 "failed to get clock\n"); 706 707 /* 708 * Force disable the core. Up to the frontend to enable us. And we can 709 * still read/write registers... 710 */ 711 ret = regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0); 712 if (ret) 713 return ret; 714 715 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); 716 if (ret) 717 return ret; 718 719 if (ADI_AXI_PCORE_VER_MAJOR(ver) != 720 ADI_AXI_PCORE_VER_MAJOR(st->info->version)) { 721 dev_err(&pdev->dev, 722 "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", 723 ADI_AXI_PCORE_VER_MAJOR(st->info->version), 724 ADI_AXI_PCORE_VER_MINOR(st->info->version), 725 ADI_AXI_PCORE_VER_PATCH(st->info->version), 726 ADI_AXI_PCORE_VER_MAJOR(ver), 727 ADI_AXI_PCORE_VER_MINOR(ver), 728 ADI_AXI_PCORE_VER_PATCH(ver)); 729 return -ENODEV; 730 } 731 732 ret = devm_iio_backend_register(&pdev->dev, st->info->backend_info, st); 733 if (ret) 734 return dev_err_probe(&pdev->dev, ret, 735 "failed to register iio backend\n"); 736 737 device_for_each_child_node_scoped(&pdev->dev, child) { 738 int val; 739 740 if (!st->info->has_child_nodes) 741 return dev_err_probe(&pdev->dev, -EINVAL, 742 "invalid fdt axi-dac compatible."); 743 744 /* Processing only reg 0 node */ 745 ret = fwnode_property_read_u32(child, "reg", &val); 746 if (ret) 747 return dev_err_probe(&pdev->dev, ret, 748 "invalid reg property."); 749 if (val != 0) 750 return dev_err_probe(&pdev->dev, -EINVAL, 751 "invalid node address."); 752 753 ret = axi_adc_create_platform_device(st, child); 754 if (ret) 755 return dev_err_probe(&pdev->dev, -EINVAL, 756 "cannot create device."); 757 } 758 759 dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n", 760 ADI_AXI_PCORE_VER_MAJOR(ver), 761 ADI_AXI_PCORE_VER_MINOR(ver), 762 ADI_AXI_PCORE_VER_PATCH(ver)); 763 764 return 0; 765 } 766 767 static const struct axi_adc_info adc_generic = { 768 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 769 .backend_info = &adi_axi_adc_generic, 770 }; 771 772 static const struct axi_adc_info adi_axi_ad485x = { 773 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 774 .backend_info = &axi_ad485x, 775 }; 776 777 static const struct ad7606_platform_data ad7606_pdata = { 778 .bus_reg_read = ad7606_bus_reg_read, 779 .bus_reg_write = ad7606_bus_reg_write, 780 }; 781 782 static const struct axi_adc_info adc_ad7606 = { 783 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 784 .backend_info = &adi_axi_adc_generic, 785 .pdata = &ad7606_pdata, 786 .pdata_sz = sizeof(ad7606_pdata), 787 .has_child_nodes = true, 788 }; 789 790 static const struct axi_adc_info adi_axi_ad408x = { 791 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 792 .backend_info = &axi_ad408x, 793 }; 794 795 /* Match table for of_platform binding */ 796 static const struct of_device_id adi_axi_adc_of_match[] = { 797 { .compatible = "adi,axi-adc-10.0.a", .data = &adc_generic }, 798 { .compatible = "adi,axi-ad408x", .data = &adi_axi_ad408x }, 799 { .compatible = "adi,axi-ad485x", .data = &adi_axi_ad485x }, 800 { .compatible = "adi,axi-ad7606x", .data = &adc_ad7606 }, 801 { } 802 }; 803 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match); 804 805 static struct platform_driver adi_axi_adc_driver = { 806 .driver = { 807 .name = KBUILD_MODNAME, 808 .of_match_table = adi_axi_adc_of_match, 809 }, 810 .probe = adi_axi_adc_probe, 811 }; 812 module_platform_driver(adi_axi_adc_driver); 813 814 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 815 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver"); 816 MODULE_LICENSE("GPL v2"); 817 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 818 MODULE_IMPORT_NS("IIO_BACKEND"); 819