1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD9467 SPI ADC driver 4 * 5 * Copyright 2012-2020 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitmap.h> 10 #include <linux/bitops.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/err.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/mutex.h> 21 #include <linux/of.h> 22 #include <linux/seq_file.h> 23 #include <linux/slab.h> 24 #include <linux/spi/spi.h> 25 #include <linux/units.h> 26 27 #include <linux/iio/backend.h> 28 #include <linux/iio/iio.h> 29 #include <linux/iio/sysfs.h> 30 31 /* 32 * ADI High-Speed ADC common spi interface registers 33 * See Application-Note AN-877: 34 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf 35 */ 36 37 #define AN877_ADC_REG_CHIP_PORT_CONF 0x00 38 #define AN877_ADC_REG_CHIP_ID 0x01 39 #define AN877_ADC_REG_CHIP_GRADE 0x02 40 #define AN877_ADC_REG_CHAN_INDEX 0x05 41 #define AN877_ADC_REG_TRANSFER 0xFF 42 #define AN877_ADC_REG_MODES 0x08 43 #define AN877_ADC_REG_TEST_IO 0x0D 44 #define AN877_ADC_REG_ADC_INPUT 0x0F 45 #define AN877_ADC_REG_OFFSET 0x10 46 #define AN877_ADC_REG_OUTPUT_MODE 0x14 47 #define AN877_ADC_REG_OUTPUT_ADJUST 0x15 48 #define AN877_ADC_REG_OUTPUT_PHASE 0x16 49 #define AN877_ADC_REG_OUTPUT_DELAY 0x17 50 #define AN877_ADC_REG_VREF 0x18 51 #define AN877_ADC_REG_ANALOG_INPUT 0x2C 52 53 /* AN877_ADC_REG_TEST_IO */ 54 #define AN877_ADC_TESTMODE_OFF 0x0 55 #define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1 56 #define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2 57 #define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3 58 #define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4 59 #define AN877_ADC_TESTMODE_PN23_SEQ 0x5 60 #define AN877_ADC_TESTMODE_PN9_SEQ 0x6 61 #define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7 62 #define AN877_ADC_TESTMODE_USER 0x8 63 #define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9 64 #define AN877_ADC_TESTMODE_SYNC 0xA 65 #define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB 66 #define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC 67 #define AN877_ADC_TESTMODE_RAMP 0xF 68 69 /* AN877_ADC_REG_TRANSFER */ 70 #define AN877_ADC_TRANSFER_SYNC 0x1 71 72 /* AN877_ADC_REG_OUTPUT_MODE */ 73 #define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0 74 #define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1 75 #define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2 76 #define AN877_ADC_OUTPUT_MODE_MASK GENMASK(1, 0) 77 78 /* AN877_ADC_REG_OUTPUT_PHASE */ 79 #define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20 80 #define AN877_ADC_INVERT_DCO_CLK 0x80 81 82 /* AN877_ADC_REG_OUTPUT_DELAY */ 83 #define AN877_ADC_DCO_DELAY_ENABLE 0x80 84 85 /* 86 * Analog Devices AD9211 10-Bit, 200/250/300 MSPS ADC 87 */ 88 89 #define CHIPID_AD9211 0x06 90 #define AD9211_DEF_OUTPUT_MODE 0x01 91 #define AD9211_REG_VREF_MASK GENMASK(4, 0) 92 93 /* 94 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC 95 */ 96 97 #define CHIPID_AD9265 0x64 98 #define AD9265_DEF_OUTPUT_MODE 0x41 99 #define AD9265_REG_VREF_MASK 0xC0 100 101 /* 102 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC 103 */ 104 105 #define CHIPID_AD9434 0x6A 106 #define AD9434_DEF_OUTPUT_MODE 0x01 107 #define AD9434_REG_VREF_MASK GENMASK(4, 0) 108 109 /* 110 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC 111 */ 112 113 #define CHIPID_AD9467 0x50 114 #define AD9467_DEF_OUTPUT_MODE 0x09 115 #define AD9467_REG_VREF_MASK 0x0F 116 117 /* 118 * Analog Devices AD9643 14-Bit, 170/210/250 MSPS ADC 119 */ 120 121 #define CHIPID_AD9643 0x82 122 #define AD9643_DEF_OUTPUT_MODE 0x01 123 #define AD9643_REG_VREF_MASK 0x1F 124 125 /* 126 * Analog Devices AD9652 16-bit 310 MSPS ADC 127 */ 128 129 #define CHIPID_AD9652 0xC1 130 #define AD9652_DEF_OUTPUT_MODE 0x01 131 #define AD9652_REG_VREF_MASK 0xC0 132 133 /* 134 * Analog Devices AD9649 14-bit 20/40/65/80 MSPS ADC 135 */ 136 137 #define CHIPID_AD9649 0x6F 138 #define AD9649_DEF_OUTPUT_MODE 0x01 139 #define AD9649_TEST_POINTS 8 140 141 #define AD9647_MAX_TEST_POINTS 32 142 #define AD9467_CAN_INVERT(st) \ 143 (!(st)->info->has_dco || (st)->info->has_dco_invert) 144 145 struct ad9467_chip_info { 146 const char *name; 147 unsigned int id; 148 const struct iio_chan_spec *channels; 149 unsigned int num_channels; 150 const unsigned int (*scale_table)[2]; 151 int num_scales; 152 unsigned long test_mask; 153 unsigned int test_mask_len; 154 unsigned long max_rate; 155 unsigned int default_output_mode; 156 unsigned int vref_mask; 157 unsigned int num_lanes; 158 unsigned int dco_en; 159 unsigned int test_points; 160 const int *offset_range; 161 /* data clock output */ 162 bool has_dco; 163 bool has_dco_invert; 164 }; 165 166 struct ad9467_chan_test_mode { 167 struct ad9467_state *st; 168 unsigned int idx; 169 u8 mode; 170 }; 171 172 struct ad9467_state { 173 const struct ad9467_chip_info *info; 174 struct iio_backend *back; 175 struct spi_device *spi; 176 struct clk *clk; 177 /* used for debugfs */ 178 struct ad9467_chan_test_mode *chan_test; 179 unsigned int (*scales)[2]; 180 /* 181 * Times 2 because we may also invert the signal polarity and run the 182 * calibration again. For some reference on the test points (ad9265) see: 183 * https://www.analog.com/media/en/technical-documentation/data-sheets/ad9265.pdf 184 * at page 38 for the dco output delay. On devices as ad9467, the 185 * calibration is done at the backend level. For the ADI axi-adc: 186 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 187 * at the io delay control section. 188 */ 189 DECLARE_BITMAP(calib_map, AD9647_MAX_TEST_POINTS * 2); 190 /* number of bits of the map */ 191 unsigned int calib_map_size; 192 struct gpio_desc *pwrdown_gpio; 193 /* ensure consistent state obtained on multiple related accesses */ 194 struct mutex lock; 195 u8 buf[3] __aligned(IIO_DMA_MINALIGN); 196 }; 197 198 static int ad9467_spi_read(struct ad9467_state *st, unsigned int reg) 199 { 200 unsigned char tbuf[2], rbuf[1]; 201 int ret; 202 203 tbuf[0] = 0x80 | (reg >> 8); 204 tbuf[1] = reg & 0xFF; 205 206 ret = spi_write_then_read(st->spi, 207 tbuf, ARRAY_SIZE(tbuf), 208 rbuf, ARRAY_SIZE(rbuf)); 209 210 if (ret < 0) 211 return ret; 212 213 return rbuf[0]; 214 } 215 216 static int ad9467_spi_write(struct ad9467_state *st, unsigned int reg, 217 unsigned int val) 218 { 219 st->buf[0] = reg >> 8; 220 st->buf[1] = reg & 0xFF; 221 st->buf[2] = val; 222 223 return spi_write(st->spi, st->buf, ARRAY_SIZE(st->buf)); 224 } 225 226 static int ad9467_reg_access(struct iio_dev *indio_dev, unsigned int reg, 227 unsigned int writeval, unsigned int *readval) 228 { 229 struct ad9467_state *st = iio_priv(indio_dev); 230 int ret; 231 232 if (!readval) { 233 guard(mutex)(&st->lock); 234 ret = ad9467_spi_write(st, reg, writeval); 235 if (ret) 236 return ret; 237 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 238 AN877_ADC_TRANSFER_SYNC); 239 } 240 241 ret = ad9467_spi_read(st, reg); 242 if (ret < 0) 243 return ret; 244 *readval = ret; 245 246 return 0; 247 } 248 249 static const int ad9434_offset_range[] = { 250 -128, 1, 127, 251 }; 252 253 static const unsigned int ad9211_scale_table[][2] = { 254 {980, 0x10}, {1000, 0x11}, {1020, 0x12}, {1040, 0x13}, 255 {1060, 0x14}, {1080, 0x15}, {1100, 0x16}, {1120, 0x17}, 256 {1140, 0x18}, {1160, 0x19}, {1180, 0x1A}, {1190, 0x1B}, 257 {1200, 0x1C}, {1210, 0x1D}, {1220, 0x1E}, {1230, 0x1F}, 258 {1250, 0x0}, {1270, 0x1}, {1290, 0x2}, {1310, 0x3}, 259 {1330, 0x4}, {1350, 0x5}, {1370, 0x6}, {1390, 0x7}, 260 {1410, 0x8}, {1430, 0x9}, {1450, 0xA}, {1460, 0xB}, 261 {1470, 0xC}, {1480, 0xD}, {1490, 0xE}, {1500, 0xF}, 262 }; 263 264 static const unsigned int ad9265_scale_table[][2] = { 265 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0}, 266 }; 267 268 static const unsigned int ad9434_scale_table[][2] = { 269 {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00}, 270 {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05}, 271 {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A}, 272 {1200, 0x0B}, {1180, 0x0C}, 273 }; 274 275 static const unsigned int ad9467_scale_table[][2] = { 276 {2000, 0}, {2100, 6}, {2200, 7}, 277 {2300, 8}, {2400, 9}, {2500, 10}, 278 }; 279 280 static const unsigned int ad9643_scale_table[][2] = { 281 {2087, 0x0F}, {2065, 0x0E}, {2042, 0x0D}, {2020, 0x0C}, {1997, 0x0B}, 282 {1975, 0x0A}, {1952, 0x09}, {1930, 0x08}, {1907, 0x07}, {1885, 0x06}, 283 {1862, 0x05}, {1840, 0x04}, {1817, 0x03}, {1795, 0x02}, {1772, 0x01}, 284 {1750, 0x00}, {1727, 0x1F}, {1704, 0x1E}, {1681, 0x1D}, {1658, 0x1C}, 285 {1635, 0x1B}, {1612, 0x1A}, {1589, 0x19}, {1567, 0x18}, {1544, 0x17}, 286 {1521, 0x16}, {1498, 0x15}, {1475, 0x14}, {1452, 0x13}, {1429, 0x12}, 287 {1406, 0x11}, {1383, 0x10}, 288 }; 289 290 static const unsigned int ad9649_scale_table[][2] = { 291 {2000, 0}, 292 }; 293 294 static const unsigned int ad9652_scale_table[][2] = { 295 {1250, 0}, {1125, 1}, {1200, 2}, {1250, 3}, {1000, 5}, 296 }; 297 298 static void __ad9467_get_scale(struct ad9467_state *st, int index, 299 unsigned int *val, unsigned int *val2) 300 { 301 const struct ad9467_chip_info *info = st->info; 302 const struct iio_chan_spec *chan = &info->channels[0]; 303 unsigned int tmp; 304 305 tmp = (info->scale_table[index][0] * 1000000ULL) >> 306 chan->scan_type.realbits; 307 *val = tmp / 1000000; 308 *val2 = tmp % 1000000; 309 } 310 311 #define AD9467_CHAN(_chan, avai_mask, _si, _bits, _sign) \ 312 { \ 313 .type = IIO_VOLTAGE, \ 314 .indexed = 1, \ 315 .channel = _chan, \ 316 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 317 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 318 .info_mask_shared_by_type_available = avai_mask, \ 319 .scan_index = _si, \ 320 .scan_type = { \ 321 .sign = _sign, \ 322 .realbits = _bits, \ 323 .storagebits = 16, \ 324 }, \ 325 } 326 327 static const struct iio_chan_spec ad9211_channels[] = { 328 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 10, 's'), 329 }; 330 331 static const struct iio_chan_spec ad9434_channels[] = { 332 { 333 .type = IIO_VOLTAGE, 334 .indexed = 1, 335 .channel = 0, 336 .info_mask_shared_by_type = 337 BIT(IIO_CHAN_INFO_SCALE) | 338 BIT(IIO_CHAN_INFO_SAMP_FREQ) | 339 BIT(IIO_CHAN_INFO_CALIBBIAS), 340 .info_mask_shared_by_type_available = 341 BIT(IIO_CHAN_INFO_SCALE) | 342 BIT(IIO_CHAN_INFO_CALIBBIAS), 343 .scan_index = 0, 344 .scan_type = { 345 .sign = 's', 346 .realbits = 12, 347 .storagebits = 16, 348 }, 349 }, 350 }; 351 352 static const struct iio_chan_spec ad9467_channels[] = { 353 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 16, 's'), 354 }; 355 356 static const struct iio_chan_spec ad9643_channels[] = { 357 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 14, 's'), 358 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE), 1, 14, 's'), 359 }; 360 361 static const struct iio_chan_spec ad9649_channels[] = { 362 AD9467_CHAN(0, 0, 0, 14, 's'), 363 }; 364 365 static const struct iio_chan_spec ad9652_channels[] = { 366 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 16, 's'), 367 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE), 1, 16, 's'), 368 }; 369 370 static const char * const ad9467_test_modes[] = { 371 [AN877_ADC_TESTMODE_OFF] = "off", 372 [AN877_ADC_TESTMODE_MIDSCALE_SHORT] = "midscale_short", 373 [AN877_ADC_TESTMODE_POS_FULLSCALE] = "pos_fullscale", 374 [AN877_ADC_TESTMODE_NEG_FULLSCALE] = "neg_fullscale", 375 [AN877_ADC_TESTMODE_ALT_CHECKERBOARD] = "checkerboard", 376 [AN877_ADC_TESTMODE_PN23_SEQ] = "prbs23", 377 [AN877_ADC_TESTMODE_PN9_SEQ] = "prbs9", 378 [AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE] = "one_zero_toggle", 379 [AN877_ADC_TESTMODE_USER] = "user", 380 [AN877_ADC_TESTMODE_BIT_TOGGLE] = "bit_toggle", 381 [AN877_ADC_TESTMODE_SYNC] = "sync", 382 [AN877_ADC_TESTMODE_ONE_BIT_HIGH] = "one_bit_high", 383 [AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY] = "mixed_bit_frequency", 384 [AN877_ADC_TESTMODE_RAMP] = "ramp", 385 }; 386 387 static const struct ad9467_chip_info ad9467_chip_tbl = { 388 .name = "ad9467", 389 .id = CHIPID_AD9467, 390 .max_rate = 250000000UL, 391 .scale_table = ad9467_scale_table, 392 .num_scales = ARRAY_SIZE(ad9467_scale_table), 393 .channels = ad9467_channels, 394 .num_channels = ARRAY_SIZE(ad9467_channels), 395 .test_points = AD9647_MAX_TEST_POINTS, 396 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, 397 AN877_ADC_TESTMODE_OFF), 398 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, 399 .default_output_mode = AD9467_DEF_OUTPUT_MODE, 400 .vref_mask = AD9467_REG_VREF_MASK, 401 .num_lanes = 8, 402 }; 403 404 static const struct ad9467_chip_info ad9434_chip_tbl = { 405 .name = "ad9434", 406 .id = CHIPID_AD9434, 407 .max_rate = 500000000UL, 408 .scale_table = ad9434_scale_table, 409 .num_scales = ARRAY_SIZE(ad9434_scale_table), 410 .channels = ad9434_channels, 411 .num_channels = ARRAY_SIZE(ad9434_channels), 412 .test_points = AD9647_MAX_TEST_POINTS, 413 .test_mask = GENMASK(AN877_ADC_TESTMODE_USER, AN877_ADC_TESTMODE_OFF), 414 .test_mask_len = AN877_ADC_TESTMODE_USER + 1, 415 .default_output_mode = AD9434_DEF_OUTPUT_MODE, 416 .vref_mask = AD9434_REG_VREF_MASK, 417 .num_lanes = 6, 418 .offset_range = ad9434_offset_range, 419 }; 420 421 static const struct ad9467_chip_info ad9211_chip_tbl = { 422 .name = "ad9211", 423 .id = CHIPID_AD9211, 424 .max_rate = 300 * HZ_PER_MHZ, 425 .scale_table = ad9211_scale_table, 426 .num_scales = ARRAY_SIZE(ad9211_scale_table), 427 .channels = ad9211_channels, 428 .num_channels = ARRAY_SIZE(ad9211_channels), 429 .test_points = AD9647_MAX_TEST_POINTS, 430 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, 431 AN877_ADC_TESTMODE_OFF), 432 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, 433 .default_output_mode = AD9211_DEF_OUTPUT_MODE, 434 .vref_mask = AD9211_REG_VREF_MASK, 435 .has_dco = true, 436 }; 437 438 static const struct ad9467_chip_info ad9265_chip_tbl = { 439 .name = "ad9265", 440 .id = CHIPID_AD9265, 441 .max_rate = 125000000UL, 442 .scale_table = ad9265_scale_table, 443 .num_scales = ARRAY_SIZE(ad9265_scale_table), 444 .channels = ad9467_channels, 445 .num_channels = ARRAY_SIZE(ad9467_channels), 446 .test_points = AD9647_MAX_TEST_POINTS, 447 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, 448 AN877_ADC_TESTMODE_OFF), 449 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, 450 .default_output_mode = AD9265_DEF_OUTPUT_MODE, 451 .vref_mask = AD9265_REG_VREF_MASK, 452 .has_dco = true, 453 .has_dco_invert = true, 454 }; 455 456 static const struct ad9467_chip_info ad9643_chip_tbl = { 457 .name = "ad9643", 458 .id = CHIPID_AD9643, 459 .max_rate = 250000000UL, 460 .scale_table = ad9643_scale_table, 461 .num_scales = ARRAY_SIZE(ad9643_scale_table), 462 .channels = ad9643_channels, 463 .num_channels = ARRAY_SIZE(ad9643_channels), 464 .test_points = AD9647_MAX_TEST_POINTS, 465 .test_mask = BIT(AN877_ADC_TESTMODE_RAMP) | 466 GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY, AN877_ADC_TESTMODE_OFF), 467 .test_mask_len = AN877_ADC_TESTMODE_RAMP + 1, 468 .default_output_mode = AD9643_DEF_OUTPUT_MODE, 469 .vref_mask = AD9643_REG_VREF_MASK, 470 .has_dco = true, 471 .has_dco_invert = true, 472 .dco_en = AN877_ADC_DCO_DELAY_ENABLE, 473 }; 474 475 static const struct ad9467_chip_info ad9649_chip_tbl = { 476 .name = "ad9649", 477 .id = CHIPID_AD9649, 478 .max_rate = 80000000UL, 479 .scale_table = ad9649_scale_table, 480 .num_scales = ARRAY_SIZE(ad9649_scale_table), 481 .channels = ad9649_channels, 482 .num_channels = ARRAY_SIZE(ad9649_channels), 483 .test_points = AD9649_TEST_POINTS, 484 .test_mask = GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY, 485 AN877_ADC_TESTMODE_OFF), 486 .test_mask_len = AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY + 1, 487 .default_output_mode = AD9649_DEF_OUTPUT_MODE, 488 .has_dco = true, 489 .has_dco_invert = true, 490 .dco_en = AN877_ADC_DCO_DELAY_ENABLE, 491 }; 492 493 static const struct ad9467_chip_info ad9652_chip_tbl = { 494 .name = "ad9652", 495 .id = CHIPID_AD9652, 496 .max_rate = 310000000UL, 497 .scale_table = ad9652_scale_table, 498 .num_scales = ARRAY_SIZE(ad9652_scale_table), 499 .channels = ad9652_channels, 500 .num_channels = ARRAY_SIZE(ad9652_channels), 501 .test_points = AD9647_MAX_TEST_POINTS, 502 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, 503 AN877_ADC_TESTMODE_OFF), 504 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, 505 .default_output_mode = AD9652_DEF_OUTPUT_MODE, 506 .vref_mask = AD9652_REG_VREF_MASK, 507 .has_dco = true, 508 }; 509 510 static int ad9467_get_scale(struct ad9467_state *st, int *val, int *val2) 511 { 512 const struct ad9467_chip_info *info = st->info; 513 unsigned int vref_val; 514 unsigned int i = 0; 515 int ret; 516 517 /* nothing to read if we only have one possible scale */ 518 if (info->num_scales == 1) 519 goto out_get_scale; 520 521 ret = ad9467_spi_read(st, AN877_ADC_REG_VREF); 522 if (ret < 0) 523 return ret; 524 525 vref_val = ret & info->vref_mask; 526 527 for (i = 0; i < info->num_scales; i++) { 528 if (vref_val == info->scale_table[i][1]) 529 break; 530 } 531 532 if (i == info->num_scales) 533 return -ERANGE; 534 535 out_get_scale: 536 __ad9467_get_scale(st, i, val, val2); 537 538 return IIO_VAL_INT_PLUS_MICRO; 539 } 540 541 static int ad9467_set_scale(struct ad9467_state *st, int val, int val2) 542 { 543 const struct ad9467_chip_info *info = st->info; 544 unsigned int scale_val[2]; 545 unsigned int i; 546 int ret; 547 548 if (val != 0) 549 return -EINVAL; 550 if (info->num_scales == 1) 551 return -EOPNOTSUPP; 552 553 for (i = 0; i < info->num_scales; i++) { 554 __ad9467_get_scale(st, i, &scale_val[0], &scale_val[1]); 555 if (scale_val[0] != val || scale_val[1] != val2) 556 continue; 557 558 guard(mutex)(&st->lock); 559 ret = ad9467_spi_write(st, AN877_ADC_REG_VREF, 560 info->scale_table[i][1]); 561 if (ret < 0) 562 return ret; 563 564 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 565 AN877_ADC_TRANSFER_SYNC); 566 } 567 568 return -EINVAL; 569 } 570 571 static int ad9467_get_offset(struct ad9467_state *st, int *val) 572 { 573 int ret; 574 575 ret = ad9467_spi_read(st, AN877_ADC_REG_OFFSET); 576 if (ret < 0) 577 return ret; 578 *val = ret; 579 580 return IIO_VAL_INT; 581 } 582 583 static int ad9467_set_offset(struct ad9467_state *st, int val) 584 { 585 int ret; 586 587 if (val < st->info->offset_range[0] || val > st->info->offset_range[2]) 588 return -EINVAL; 589 590 ret = ad9467_spi_write(st, AN877_ADC_REG_OFFSET, val); 591 if (ret < 0) 592 return ret; 593 594 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 595 AN877_ADC_TRANSFER_SYNC); 596 } 597 598 static int ad9467_outputmode_set(struct ad9467_state *st, unsigned int mode) 599 { 600 int ret; 601 602 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_MODE, mode); 603 if (ret < 0) 604 return ret; 605 606 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 607 AN877_ADC_TRANSFER_SYNC); 608 } 609 610 static int ad9467_testmode_set(struct ad9467_state *st, unsigned int chan, 611 unsigned int test_mode) 612 { 613 int ret; 614 615 if (st->info->num_channels > 1) { 616 /* so that the test mode is only applied to one channel */ 617 ret = ad9467_spi_write(st, AN877_ADC_REG_CHAN_INDEX, BIT(chan)); 618 if (ret) 619 return ret; 620 } 621 622 ret = ad9467_spi_write(st, AN877_ADC_REG_TEST_IO, test_mode); 623 if (ret) 624 return ret; 625 626 if (st->info->num_channels > 1) { 627 /* go to default state where all channels get write commands */ 628 ret = ad9467_spi_write(st, AN877_ADC_REG_CHAN_INDEX, 629 GENMASK(st->info->num_channels - 1, 0)); 630 if (ret) 631 return ret; 632 } 633 634 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 635 AN877_ADC_TRANSFER_SYNC); 636 } 637 638 static int ad9467_backend_testmode_on(struct ad9467_state *st, 639 unsigned int chan, 640 enum iio_backend_test_pattern pattern) 641 { 642 struct iio_backend_data_fmt data = { 643 .enable = false, 644 }; 645 int ret; 646 647 ret = iio_backend_data_format_set(st->back, chan, &data); 648 if (ret) 649 return ret; 650 651 ret = iio_backend_test_pattern_set(st->back, chan, pattern); 652 if (ret) 653 return ret; 654 655 return iio_backend_chan_enable(st->back, chan); 656 } 657 658 static int ad9467_backend_testmode_off(struct ad9467_state *st, 659 unsigned int chan) 660 { 661 struct iio_backend_data_fmt data = { 662 .enable = true, 663 .sign_extend = true, 664 }; 665 int ret; 666 667 ret = iio_backend_chan_disable(st->back, chan); 668 if (ret) 669 return ret; 670 671 ret = iio_backend_test_pattern_set(st->back, chan, 672 IIO_BACKEND_NO_TEST_PATTERN); 673 if (ret) 674 return ret; 675 676 return iio_backend_data_format_set(st->back, chan, &data); 677 } 678 679 static int ad9647_calibrate_prepare(struct ad9467_state *st) 680 { 681 unsigned int cmode; 682 unsigned int c; 683 int ret; 684 685 cmode = st->info->default_output_mode; 686 FIELD_MODIFY(AN877_ADC_OUTPUT_MODE_MASK, &cmode, 687 AN877_ADC_OUTPUT_MODE_OFFSET_BINARY); 688 ret = ad9467_outputmode_set(st, cmode); 689 if (ret) 690 return ret; 691 692 for (c = 0; c < st->info->num_channels; c++) { 693 ret = ad9467_testmode_set(st, c, AN877_ADC_TESTMODE_PN9_SEQ); 694 if (ret) 695 return ret; 696 697 ret = ad9467_backend_testmode_on(st, c, 698 IIO_BACKEND_ADI_PRBS_9A); 699 if (ret) 700 return ret; 701 } 702 703 return 0; 704 } 705 706 static int ad9647_calibrate_polarity_set(struct ad9467_state *st, 707 bool invert) 708 { 709 enum iio_backend_sample_trigger trigger; 710 711 if (st->info->has_dco) { 712 unsigned int phase = AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN; 713 714 if (invert) 715 phase |= AN877_ADC_INVERT_DCO_CLK; 716 717 return ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_PHASE, 718 phase); 719 } 720 721 if (invert) 722 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING; 723 else 724 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING; 725 726 return iio_backend_data_sample_trigger(st->back, trigger); 727 } 728 729 /* 730 * The idea is pretty simple. Find the max number of successful points in a row 731 * and get the one in the middle. 732 */ 733 static unsigned int ad9467_find_optimal_point(const unsigned long *calib_map, 734 unsigned int start, 735 unsigned int nbits, 736 unsigned int *val) 737 { 738 unsigned int bit = start, end, start_cnt, cnt = 0; 739 740 for_each_clear_bitrange_from(bit, end, calib_map, nbits + start) { 741 if (end - bit > cnt) { 742 cnt = end - bit; 743 start_cnt = bit; 744 } 745 } 746 747 if (cnt) 748 *val = start_cnt + cnt / 2; 749 750 return cnt; 751 } 752 753 static int ad9467_calibrate_apply(struct ad9467_state *st, unsigned int val) 754 { 755 unsigned int lane; 756 int ret; 757 758 if (st->info->has_dco) { 759 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_DELAY, 760 val | st->info->dco_en); 761 if (ret) 762 return ret; 763 764 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 765 AN877_ADC_TRANSFER_SYNC); 766 } 767 768 for (lane = 0; lane < st->info->num_lanes; lane++) { 769 ret = iio_backend_iodelay_set(st->back, lane, val); 770 if (ret) 771 return ret; 772 } 773 774 return 0; 775 } 776 777 static int ad9647_calibrate_stop(struct ad9467_state *st) 778 { 779 unsigned int c, mode; 780 int ret; 781 782 for (c = 0; c < st->info->num_channels; c++) { 783 ret = ad9467_backend_testmode_off(st, c); 784 if (ret) 785 return ret; 786 787 ret = ad9467_testmode_set(st, c, AN877_ADC_TESTMODE_OFF); 788 if (ret) 789 return ret; 790 } 791 792 mode = st->info->default_output_mode; 793 return ad9467_outputmode_set(st, mode); 794 } 795 796 static int ad9467_calibrate(struct ad9467_state *st) 797 { 798 unsigned int point, val, inv_val, cnt, inv_cnt = 0, c; 799 /* 800 * Half of the bitmap is for the inverted signal. The number of test 801 * points is the same though... 802 */ 803 unsigned int test_points = st->info->test_points; 804 unsigned long sample_rate = clk_get_rate(st->clk); 805 struct device *dev = &st->spi->dev; 806 bool invert = false, stat; 807 int ret; 808 809 /* all points invalid */ 810 bitmap_fill(st->calib_map, st->calib_map_size); 811 812 ret = ad9647_calibrate_prepare(st); 813 if (ret) 814 return ret; 815 retune: 816 ret = ad9647_calibrate_polarity_set(st, invert); 817 if (ret) 818 return ret; 819 820 for (point = 0; point < st->info->test_points; point++) { 821 ret = ad9467_calibrate_apply(st, point); 822 if (ret) 823 return ret; 824 825 for (c = 0; c < st->info->num_channels; c++) { 826 ret = iio_backend_chan_status(st->back, c, &stat); 827 if (ret) 828 return ret; 829 830 /* 831 * A point is considered valid if all channels report no 832 * error. If one reports an error, then we consider the 833 * point as invalid and we can break the loop right away. 834 */ 835 if (stat) { 836 dev_dbg(dev, "Invalid point(%u, inv:%u) for CH:%u\n", 837 point, invert, c); 838 break; 839 } 840 841 if (c == st->info->num_channels - 1) 842 __clear_bit(point + invert * test_points, 843 st->calib_map); 844 } 845 } 846 847 if (!invert) { 848 cnt = ad9467_find_optimal_point(st->calib_map, 0, test_points, 849 &val); 850 /* 851 * We're happy if we find, at least, three good test points in 852 * a row. 853 */ 854 if (cnt < 3) { 855 if (AD9467_CAN_INVERT(st)) { 856 invert = true; 857 goto retune; 858 } 859 860 if (!cnt) 861 return -EIO; 862 } 863 } else { 864 inv_cnt = ad9467_find_optimal_point(st->calib_map, test_points, 865 test_points, &inv_val); 866 if (!inv_cnt && !cnt) 867 return -EIO; 868 } 869 870 if (inv_cnt < cnt) { 871 ret = ad9647_calibrate_polarity_set(st, false); 872 if (ret) 873 return ret; 874 } else { 875 /* 876 * polarity inverted is the last test to run. Hence, there's no 877 * need to re-do any configuration. We just need to "normalize" 878 * the selected value. 879 */ 880 val = inv_val - test_points; 881 } 882 883 if (st->info->has_dco) 884 dev_dbg(dev, "%sDCO 0x%X CLK %lu Hz\n", inv_cnt >= cnt ? "INVERT " : "", 885 val, sample_rate); 886 else 887 dev_dbg(dev, "%sIDELAY 0x%x\n", inv_cnt >= cnt ? "INVERT " : "", 888 val); 889 890 ret = ad9467_calibrate_apply(st, val); 891 if (ret) 892 return ret; 893 894 /* finally apply the optimal value */ 895 return ad9647_calibrate_stop(st); 896 } 897 898 static int ad9467_read_raw(struct iio_dev *indio_dev, 899 struct iio_chan_spec const *chan, 900 int *val, int *val2, long m) 901 { 902 struct ad9467_state *st = iio_priv(indio_dev); 903 904 switch (m) { 905 case IIO_CHAN_INFO_CALIBBIAS: 906 return ad9467_get_offset(st, val); 907 case IIO_CHAN_INFO_SCALE: 908 return ad9467_get_scale(st, val, val2); 909 case IIO_CHAN_INFO_SAMP_FREQ: 910 *val = clk_get_rate(st->clk); 911 912 return IIO_VAL_INT; 913 default: 914 return -EINVAL; 915 } 916 } 917 918 static int __ad9467_update_clock(struct ad9467_state *st, long r_clk) 919 { 920 int ret; 921 922 ret = clk_set_rate(st->clk, r_clk); 923 if (ret) 924 return ret; 925 926 guard(mutex)(&st->lock); 927 928 if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) 929 return ad9467_calibrate(st); 930 931 return 0; 932 } 933 934 static int ad9467_write_raw(struct iio_dev *indio_dev, 935 struct iio_chan_spec const *chan, 936 int val, int val2, long mask) 937 { 938 struct ad9467_state *st = iio_priv(indio_dev); 939 const struct ad9467_chip_info *info = st->info; 940 unsigned long sample_rate; 941 long r_clk; 942 int ret; 943 944 switch (mask) { 945 case IIO_CHAN_INFO_CALIBBIAS: 946 return ad9467_set_offset(st, val); 947 case IIO_CHAN_INFO_SCALE: 948 return ad9467_set_scale(st, val, val2); 949 case IIO_CHAN_INFO_SAMP_FREQ: 950 r_clk = clk_round_rate(st->clk, val); 951 if (r_clk < 0 || r_clk > info->max_rate) { 952 dev_warn(&st->spi->dev, 953 "Error setting ADC sample rate %ld", r_clk); 954 return -EINVAL; 955 } 956 957 sample_rate = clk_get_rate(st->clk); 958 /* 959 * clk_set_rate() would also do this but since we would still 960 * need it for avoiding an unnecessary calibration, do it now. 961 */ 962 if (sample_rate == r_clk) 963 return 0; 964 965 if (!iio_device_claim_direct(indio_dev)) 966 return -EBUSY; 967 968 ret = __ad9467_update_clock(st, r_clk); 969 iio_device_release_direct(indio_dev); 970 return ret; 971 default: 972 return -EINVAL; 973 } 974 } 975 976 static int ad9467_read_avail(struct iio_dev *indio_dev, 977 struct iio_chan_spec const *chan, 978 const int **vals, int *type, int *length, 979 long mask) 980 { 981 struct ad9467_state *st = iio_priv(indio_dev); 982 const struct ad9467_chip_info *info = st->info; 983 984 switch (mask) { 985 case IIO_CHAN_INFO_CALIBBIAS: 986 *type = IIO_VAL_INT; 987 *vals = info->offset_range; 988 return IIO_AVAIL_RANGE; 989 case IIO_CHAN_INFO_SCALE: 990 *vals = (const int *)st->scales; 991 *type = IIO_VAL_INT_PLUS_MICRO; 992 /* Values are stored in a 2D matrix */ 993 *length = info->num_scales * 2; 994 return IIO_AVAIL_LIST; 995 default: 996 return -EINVAL; 997 } 998 } 999 1000 static int ad9467_update_scan_mode(struct iio_dev *indio_dev, 1001 const unsigned long *scan_mask) 1002 { 1003 struct ad9467_state *st = iio_priv(indio_dev); 1004 unsigned int c; 1005 int ret; 1006 1007 for (c = 0; c < st->info->num_channels; c++) { 1008 if (test_bit(c, scan_mask)) 1009 ret = iio_backend_chan_enable(st->back, c); 1010 else 1011 ret = iio_backend_chan_disable(st->back, c); 1012 if (ret) 1013 return ret; 1014 } 1015 1016 return 0; 1017 } 1018 1019 static const struct iio_info ad9467_info = { 1020 .read_raw = ad9467_read_raw, 1021 .write_raw = ad9467_write_raw, 1022 .update_scan_mode = ad9467_update_scan_mode, 1023 .debugfs_reg_access = ad9467_reg_access, 1024 .read_avail = ad9467_read_avail, 1025 }; 1026 1027 /* Same as above, but without .read_avail */ 1028 static const struct iio_info ad9467_info_no_read_avail = { 1029 .read_raw = ad9467_read_raw, 1030 .write_raw = ad9467_write_raw, 1031 .update_scan_mode = ad9467_update_scan_mode, 1032 .debugfs_reg_access = ad9467_reg_access, 1033 }; 1034 1035 static int ad9467_scale_fill(struct ad9467_state *st) 1036 { 1037 const struct ad9467_chip_info *info = st->info; 1038 unsigned int i, val1, val2; 1039 1040 st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales, 1041 sizeof(*st->scales), GFP_KERNEL); 1042 if (!st->scales) 1043 return -ENOMEM; 1044 1045 for (i = 0; i < info->num_scales; i++) { 1046 __ad9467_get_scale(st, i, &val1, &val2); 1047 st->scales[i][0] = val1; 1048 st->scales[i][1] = val2; 1049 } 1050 1051 return 0; 1052 } 1053 1054 static int ad9467_reset(struct device *dev) 1055 { 1056 struct gpio_desc *gpio; 1057 1058 gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1059 if (IS_ERR_OR_NULL(gpio)) 1060 return PTR_ERR_OR_ZERO(gpio); 1061 1062 fsleep(1); 1063 gpiod_set_value_cansleep(gpio, 0); 1064 fsleep(10 * USEC_PER_MSEC); 1065 1066 return 0; 1067 } 1068 1069 static int ad9467_iio_backend_get(struct ad9467_state *st) 1070 { 1071 struct device *dev = &st->spi->dev; 1072 struct device_node *__back; 1073 1074 st->back = devm_iio_backend_get(dev, NULL); 1075 if (!IS_ERR(st->back)) 1076 return 0; 1077 /* If not found, don't error out as we might have legacy DT property */ 1078 if (PTR_ERR(st->back) != -ENOENT) 1079 return PTR_ERR(st->back); 1080 1081 /* 1082 * if we don't get the backend using the normal API's, use the legacy 1083 * 'adi,adc-dev' property. So we get all nodes with that property, and 1084 * look for the one pointing at us. Then we directly lookup that fwnode 1085 * on the backend list of registered devices. This is done so we don't 1086 * make io-backends mandatory which would break DT ABI. 1087 */ 1088 for_each_node_with_property(__back, "adi,adc-dev") { 1089 struct device_node *__me; 1090 1091 __me = of_parse_phandle(__back, "adi,adc-dev", 0); 1092 if (!__me) 1093 continue; 1094 1095 if (!device_match_of_node(dev, __me)) { 1096 of_node_put(__me); 1097 continue; 1098 } 1099 1100 of_node_put(__me); 1101 st->back = __devm_iio_backend_get_from_fwnode_lookup(dev, 1102 of_fwnode_handle(__back)); 1103 of_node_put(__back); 1104 return PTR_ERR_OR_ZERO(st->back); 1105 } 1106 1107 return -ENODEV; 1108 } 1109 1110 static int ad9467_test_mode_available_show(struct seq_file *s, void *ignored) 1111 { 1112 struct ad9467_state *st = s->private; 1113 unsigned int bit; 1114 1115 for_each_set_bit(bit, &st->info->test_mask, st->info->test_mask_len) 1116 seq_printf(s, "%s\n", ad9467_test_modes[bit]); 1117 1118 return 0; 1119 } 1120 DEFINE_SHOW_ATTRIBUTE(ad9467_test_mode_available); 1121 1122 static ssize_t ad9467_chan_test_mode_read(struct file *file, 1123 char __user *userbuf, size_t count, 1124 loff_t *ppos) 1125 { 1126 struct ad9467_chan_test_mode *chan = file->private_data; 1127 struct ad9467_state *st = chan->st; 1128 char buf[128] = {0}; 1129 size_t len; 1130 int ret; 1131 1132 if (chan->mode == AN877_ADC_TESTMODE_PN9_SEQ || 1133 chan->mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1134 len = scnprintf(buf, sizeof(buf), "Running \"%s\" Test:\n\t", 1135 ad9467_test_modes[chan->mode]); 1136 1137 if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) { 1138 ret = iio_backend_debugfs_print_chan_status(st->back, 1139 chan->idx, 1140 buf + len, 1141 sizeof(buf) - len); 1142 if (ret < 0) 1143 return ret; 1144 len += ret; 1145 } 1146 } else if (chan->mode == AN877_ADC_TESTMODE_OFF) { 1147 len = scnprintf(buf, sizeof(buf), "No test Running...\n"); 1148 } else { 1149 len = scnprintf(buf, sizeof(buf), "Running \"%s\" Test on CH:%u\n", 1150 ad9467_test_modes[chan->mode], chan->idx); 1151 } 1152 1153 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 1154 } 1155 1156 static ssize_t ad9467_chan_test_mode_write(struct file *file, 1157 const char __user *userbuf, 1158 size_t count, loff_t *ppos) 1159 { 1160 struct ad9467_chan_test_mode *chan = file->private_data; 1161 struct ad9467_state *st = chan->st; 1162 char test_mode[32] = {0}; 1163 unsigned int mode; 1164 int ret; 1165 1166 ret = simple_write_to_buffer(test_mode, sizeof(test_mode) - 1, ppos, 1167 userbuf, count); 1168 if (ret < 0) 1169 return ret; 1170 1171 for_each_set_bit(mode, &st->info->test_mask, st->info->test_mask_len) { 1172 if (sysfs_streq(test_mode, ad9467_test_modes[mode])) 1173 break; 1174 } 1175 1176 if (mode == st->info->test_mask_len) 1177 return -EINVAL; 1178 1179 guard(mutex)(&st->lock); 1180 1181 if (mode == AN877_ADC_TESTMODE_OFF) { 1182 unsigned int out_mode; 1183 1184 if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) { 1185 if (chan->mode == AN877_ADC_TESTMODE_PN9_SEQ || 1186 chan->mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1187 ret = ad9467_backend_testmode_off(st, chan->idx); 1188 if (ret) 1189 return ret; 1190 } 1191 } 1192 1193 ret = ad9467_testmode_set(st, chan->idx, mode); 1194 if (ret) 1195 return ret; 1196 1197 out_mode = st->info->default_output_mode; 1198 ret = ad9467_outputmode_set(st, out_mode); 1199 if (ret) 1200 return ret; 1201 } else { 1202 unsigned int cmode; 1203 1204 cmode = st->info->default_output_mode; 1205 FIELD_MODIFY(AN877_ADC_OUTPUT_MODE_MASK, &cmode, 1206 AN877_ADC_OUTPUT_MODE_OFFSET_BINARY); 1207 ret = ad9467_outputmode_set(st, cmode); 1208 if (ret) 1209 return ret; 1210 1211 ret = ad9467_testmode_set(st, chan->idx, mode); 1212 if (ret) 1213 return ret; 1214 1215 /* some patterns have a backend matching monitoring block */ 1216 if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) { 1217 if (mode == AN877_ADC_TESTMODE_PN9_SEQ) { 1218 ret = ad9467_backend_testmode_on(st, chan->idx, 1219 IIO_BACKEND_ADI_PRBS_9A); 1220 if (ret) 1221 return ret; 1222 } else if (mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1223 ret = ad9467_backend_testmode_on(st, chan->idx, 1224 IIO_BACKEND_ADI_PRBS_23A); 1225 if (ret) 1226 return ret; 1227 } 1228 } 1229 } 1230 1231 chan->mode = mode; 1232 1233 return count; 1234 } 1235 1236 static const struct file_operations ad9467_chan_test_mode_fops = { 1237 .open = simple_open, 1238 .read = ad9467_chan_test_mode_read, 1239 .write = ad9467_chan_test_mode_write, 1240 .llseek = default_llseek, 1241 .owner = THIS_MODULE, 1242 }; 1243 1244 static ssize_t ad9467_dump_calib_table(struct file *file, 1245 char __user *userbuf, 1246 size_t count, loff_t *ppos) 1247 { 1248 struct ad9467_state *st = file->private_data; 1249 unsigned int bit; 1250 /* +2 for the newline and +1 for the string termination */ 1251 unsigned char map[AD9647_MAX_TEST_POINTS * 2 + 3]; 1252 ssize_t len = 0; 1253 1254 guard(mutex)(&st->lock); 1255 if (*ppos) 1256 goto out_read; 1257 1258 for (bit = 0; bit < st->calib_map_size; bit++) { 1259 if (AD9467_CAN_INVERT(st) && bit == st->calib_map_size / 2) 1260 len += scnprintf(map + len, sizeof(map) - len, "\n"); 1261 1262 len += scnprintf(map + len, sizeof(map) - len, "%c", 1263 test_bit(bit, st->calib_map) ? 'x' : 'o'); 1264 } 1265 1266 len += scnprintf(map + len, sizeof(map) - len, "\n"); 1267 out_read: 1268 return simple_read_from_buffer(userbuf, count, ppos, map, len); 1269 } 1270 1271 static const struct file_operations ad9467_calib_table_fops = { 1272 .open = simple_open, 1273 .read = ad9467_dump_calib_table, 1274 .llseek = default_llseek, 1275 .owner = THIS_MODULE, 1276 }; 1277 1278 static void ad9467_debugfs_init(struct iio_dev *indio_dev) 1279 { 1280 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 1281 struct ad9467_state *st = iio_priv(indio_dev); 1282 char attr_name[32]; 1283 unsigned int chan; 1284 1285 if (!IS_ENABLED(CONFIG_DEBUG_FS)) 1286 return; 1287 1288 st->chan_test = devm_kcalloc(&st->spi->dev, st->info->num_channels, 1289 sizeof(*st->chan_test), GFP_KERNEL); 1290 if (!st->chan_test) 1291 return; 1292 1293 if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) 1294 debugfs_create_file("calibration_table_dump", 0400, d, st, 1295 &ad9467_calib_table_fops); 1296 1297 for (chan = 0; chan < st->info->num_channels; chan++) { 1298 snprintf(attr_name, sizeof(attr_name), "in_voltage%u_test_mode", 1299 chan); 1300 st->chan_test[chan].idx = chan; 1301 st->chan_test[chan].st = st; 1302 debugfs_create_file(attr_name, 0600, d, &st->chan_test[chan], 1303 &ad9467_chan_test_mode_fops); 1304 } 1305 1306 debugfs_create_file("in_voltage_test_mode_available", 0400, d, st, 1307 &ad9467_test_mode_available_fops); 1308 1309 iio_backend_debugfs_add(st->back, indio_dev); 1310 } 1311 1312 static int ad9467_probe(struct spi_device *spi) 1313 { 1314 struct device *dev = &spi->dev; 1315 struct iio_dev *indio_dev; 1316 struct ad9467_state *st; 1317 unsigned int id; 1318 int ret; 1319 1320 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1321 if (!indio_dev) 1322 return -ENOMEM; 1323 1324 st = iio_priv(indio_dev); 1325 st->spi = spi; 1326 1327 st->info = spi_get_device_match_data(spi); 1328 if (!st->info) 1329 return -ENODEV; 1330 1331 st->calib_map_size = st->info->test_points; 1332 if (AD9467_CAN_INVERT(st)) 1333 st->calib_map_size *= 2; 1334 1335 st->clk = devm_clk_get_enabled(dev, "adc-clk"); 1336 if (IS_ERR(st->clk)) 1337 return PTR_ERR(st->clk); 1338 1339 st->pwrdown_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_LOW); 1340 if (IS_ERR(st->pwrdown_gpio)) 1341 return PTR_ERR(st->pwrdown_gpio); 1342 1343 ret = ad9467_reset(dev); 1344 if (ret) 1345 return ret; 1346 1347 ret = ad9467_scale_fill(st); 1348 if (ret) 1349 return ret; 1350 1351 id = ad9467_spi_read(st, AN877_ADC_REG_CHIP_ID); 1352 if (id != st->info->id) { 1353 dev_err(dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n", 1354 id, st->info->id); 1355 return -ENODEV; 1356 } 1357 1358 if (st->info->num_scales > 1) 1359 indio_dev->info = &ad9467_info; 1360 else 1361 indio_dev->info = &ad9467_info_no_read_avail; 1362 indio_dev->name = st->info->name; 1363 indio_dev->channels = st->info->channels; 1364 indio_dev->num_channels = st->info->num_channels; 1365 1366 ret = ad9467_iio_backend_get(st); 1367 if (ret) 1368 return ret; 1369 1370 if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_BUFFER)) { 1371 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev); 1372 if (ret) 1373 return ret; 1374 } 1375 1376 if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_ENABLE)) { 1377 ret = devm_iio_backend_enable(dev, st->back); 1378 if (ret) 1379 return ret; 1380 } 1381 1382 if (iio_backend_has_caps(st->back, IIO_BACKEND_CAP_CALIBRATION)) { 1383 ret = ad9467_calibrate(st); 1384 if (ret) 1385 return ret; 1386 } 1387 1388 ret = devm_iio_device_register(dev, indio_dev); 1389 if (ret) 1390 return ret; 1391 1392 ad9467_debugfs_init(indio_dev); 1393 1394 return 0; 1395 } 1396 1397 static const struct of_device_id ad9467_of_match[] = { 1398 { .compatible = "adi,ad9211", .data = &ad9211_chip_tbl, }, 1399 { .compatible = "adi,ad9265", .data = &ad9265_chip_tbl, }, 1400 { .compatible = "adi,ad9434", .data = &ad9434_chip_tbl, }, 1401 { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl, }, 1402 { .compatible = "adi,ad9643", .data = &ad9643_chip_tbl, }, 1403 { .compatible = "adi,ad9649", .data = &ad9649_chip_tbl, }, 1404 { .compatible = "adi,ad9652", .data = &ad9652_chip_tbl, }, 1405 { } 1406 }; 1407 MODULE_DEVICE_TABLE(of, ad9467_of_match); 1408 1409 static const struct spi_device_id ad9467_ids[] = { 1410 { "ad9211", (kernel_ulong_t)&ad9211_chip_tbl }, 1411 { "ad9265", (kernel_ulong_t)&ad9265_chip_tbl }, 1412 { "ad9434", (kernel_ulong_t)&ad9434_chip_tbl }, 1413 { "ad9467", (kernel_ulong_t)&ad9467_chip_tbl }, 1414 { "ad9643", (kernel_ulong_t)&ad9643_chip_tbl }, 1415 { "ad9649", (kernel_ulong_t)&ad9649_chip_tbl, }, 1416 { "ad9652", (kernel_ulong_t)&ad9652_chip_tbl, }, 1417 { } 1418 }; 1419 MODULE_DEVICE_TABLE(spi, ad9467_ids); 1420 1421 static struct spi_driver ad9467_driver = { 1422 .driver = { 1423 .name = "ad9467", 1424 .of_match_table = ad9467_of_match, 1425 }, 1426 .probe = ad9467_probe, 1427 .id_table = ad9467_ids, 1428 }; 1429 module_spi_driver(ad9467_driver); 1430 1431 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1432 MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); 1433 MODULE_LICENSE("GPL v2"); 1434 MODULE_IMPORT_NS("IIO_BACKEND"); 1435